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bruteforce.ys
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bruteforce.ys
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read_verilog {{FILE}}
#map to basic cells
proc;;
techmap;;
opt;;
splitnets;;
#If required export some images
#show -prefix ./temp/{{MODULE}}_bruteforce_aig_{{LIBERTY_USED}} -color orange t:$_NOT_ -color darkred t:$_AND_ -color purple t:$ge -color darkblue t:$ne -color blue t:$le -color maroon t:$add -enum
write_blif ./temp/{{FILE_BASENAME}}.blif
abc -exe ./abc/abc -script "+source ./abc.rc;compress2rs"
#if you want to do whole design at once.
#exec -- ./abc/abc -c "read_blif ./temp/{{FILE_BASENAME}}.blif; compress2rs; write_blif ./temp/{{FILE_BASENAME}}_abc.blif"
#if required export equation and truth table"
#abc -liberty ./nem_liberty/{{LIBERTY_FILE}} -script "+strash; &get -n; collapse; write_eqn ./temp/{{FILE_BASENAME}}.eqn; &write_truths -x ./temp/{{FILE_BASENAME}}.truth"
delete
#Perform mockturtle muxig conversion
exec -- ./mockturtle_binaries/sim_resubstitution ./temp/{{FILE_BASENAME}}.blif
#Map the exported design back to yosys format to help with SAT mitters test.
exec -- python3 ./yosys/map_ports.py ./temp/{{FILE_BASENAME}}.blif ./temp/{{FILE_BASENAME}}_mockturtle.blif
#read back into Yosys
read_blif ./temp/mapped_{{FILE_BASENAME}}_mockturtle.blif
rename top {{MODULE}}_nem
#map the exported blif format back to Yosys basic cells
techmap -map ./yosys/mockturtle_map.v
techmap
#Mockturtle creates constant 1 by taking a constant 0 and inverting it. opt_expr changes these to a constant 1 to avoid this inverter.
opt_expr
clean -purge
abc -liberty ./nem_liberty/{{LIBERTY_FILE}} -script "+attach"
clean -purge
write_verilog -selected ./temp/{{FILE_BASENAME}}_nem.v
#Output stats
tee -o ./temp/{{FILE_BASENAME}}_MUX.stat stat -liberty ./nem_liberty/{{LIBERTY_FILE}}

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