bruteforce.ys
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bruteforce.ys
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	read_verilog {{FILE}}

	#map to basic cells
	techmap
	opt;;

	write_blif ./temp/{{FILE_BASENAME}}.blif
	abc -liberty ./{{LIBERTY_FILE}} -script "+strash; &get -n; collapse; write_eqn ./temp/{{FILE_BASENAME}}.eqn;"
	delete

	exec -- ./mockturtle/build/experiments/muxig_rewriting ./temp/{{FILE_BASENAME}}.blif
	exec -- python3 ./yosys/map_ports.py ./temp/{{FILE_BASENAME}}.blif ./temp/{{FILE_BASENAME}}_mockturtle.blif

	read_blif ./temp/mapped_{{FILE_BASENAME}}_mockturtle.blif

	rename top {{MODULE}}_nem

	techmap -map ./yosys/mockturtle_map.v

	techmap

	opt_expr

	clean -purge




	abc -liberty {{LIBERTY_FILE}} -script "+attach"

	clean -purge




	write_verilog -selected ./temp/{{FILE_BASENAME}}_nem.v
	#Output stats
	tee -o ./temp/{{FILE_BASENAME}}_MUX.stat stat -liberty ./{{LIBERTY_FILE}}