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mockturtle_map.v
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mockturtle_map.v
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(* techmap_celltype = "$lut" *)
module \$lut_1 (A, Y);
parameter LUT = 0;
parameter WIDTH = 3;
wire _TECHMAP_FAIL_ = (WIDTH != 3) || LUT != 8'b11100100;
input [WIDTH-1:0] A;
output Y;
$mux #(.WIDTH(1)) switch_mux_1 (.A(A[2]),.B(A[1]),.S(~A[0]),.Y(Y));
endmodule
(* techmap_celltype = "$lut" *)
module \$lut_2 (A, Y);
parameter LUT = 0;
parameter WIDTH = 3;
wire _TECHMAP_FAIL_ = (WIDTH != 3) || LUT != 8'b01001110;
input [WIDTH-1:0] A;
output Y;
$mux_4T #(.WIDTH(1)) switch_mux_2 (.A(~A[2]),.B(A[1]),.S(~A[0]),.Y(Y));
endmodule
(* techmap_celltype = "$lut" *)
module \$lut_3 (A, Y);
parameter LUT = 0;
parameter WIDTH = 3;
wire _TECHMAP_FAIL_ = (WIDTH != 3) || LUT != 8'b10001101;
input [WIDTH-1:0] A;
output Y;
$mux_4T #(.WIDTH(1)) switch_mux_3 (.A(~A[2]),.B(A[1]),.S(A[0]),.Y(Y));
endmodule
(* techmap_celltype = "$lut" *)
module \$lut_4 (A, Y);
parameter LUT = 0;
parameter WIDTH = 3;
wire _TECHMAP_FAIL_ = (WIDTH != 1) || LUT != 2'b01;
input [WIDTH-1:0] A;
output Y;
assign Y = ~A;
endmodule

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