mealy_onehot_5.v
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mealy_onehot_5.v
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	module fsm (
	input wire clk,
	input wire reset,
	input wire in1,
	input wire in2,
	output reg out
	);
	// Define state encoding using parameters
	parameter S0 = 5'b00000,
	S1 = 5'b00010,
	S2 = 5'b00100,
	S3 = 5'b01000,
	S4 = 5'b10000;

	reg [2:0] state, next_state;

	// Sequential block: state transitions on clock or reset
	always @(posedge clk or posedge reset) begin
	if (reset)
	state <= S0; // Reset to S0
	else
	state <= next_state; // Move to next state
	end

	// Combinational block: next state logic
	always @(*) begin
	case (state)
	S0: next_state = in1 ? S1 : S0;
	S1: next_state = in2 ? S2 : S1;
	S2: next_state = in1 ? S3 : S2;
	S3: next_state = in2 ? S4 : S3;
	S4: next_state = S0; // Cycle back to S0
	default: next_state = S0; // Safe default
	endcase
	end

	// Mealy output logic depends on state and input
	always @(*) begin
	out = (state == S2 && in1) \|\| (state == S4 && in2);
	end
	endmodule