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# 1. NEM synthesis
This utility was written to use yosys to synthesize from verilog to a netlist existing out of all standard cells available in the current library of NEM cells. It only uses the freely available yosys oss suite. No license required
# 2. data structure
The application is ordered as follows:
```
\bruteforce_approach\: contains all the c script's and a python script to run bruteforce approach on very small functions
\sources\ : All the verilog files for synthesis have to be stored here
\temp\ : Contains all the output files after synthesis or intermediate yosys / graphviz dots files.
\yosys\ : Script that are executed for synthesis, visual, and sat testing.
\nem_basic_yosys.lib : This is the file of all the standard cells used in nem
\nem_basic_yosys_extended.lib : this is the additional cells added based on some new concepts
```
As a user put the desired source files in .\sources\ and had to the next sessions
# 3. How to run
Pull the repository to your local working directory.
run:
```bash
source <oss-suite-location>/enviroment
./run.sh
```
and enter the file you want to use. Auto-complete is aviable, an example would be `sources/test_set/adder2.v`. Then enter the main module name. Just press enter if it is the same as the file name, (in the example `adder2`).
You will be presented with the following options:
```bash
--------------------------------------------------------------
Current file: sources/test_set/adder2.v with module: adder2
Please select your options (you can choose multiple options):
1) Synthesize to NEM technology
2) Print initial design
3) Print out NEM optimized design
4) Perform SAT comparison
5) Export FSM as KISS2 format
6) Start shell with modules
7) Switch from normal 3T gate library to new 4T
8) Run test
9) export truth table and MUXIG run
10) export truth table and MIG run
11) Select a new Verilog file
0) Exit the program
--------------------------------------------------------------
Enter your choices (e.g., 1 2 3, or 0 to finish):
```
1: As the text explains option 1 will run the synthesis script under `\yosys\` and will output the file as `_nem.v` extension in the `\temp\` folder. Next to that it will output statistics in the `.stat` file under `\temp\`.
2: Shows the abstract design before any syntehsis is done
3: Shows the final synthesized solution
4: Checks if the original verilog file matches the output of the final synthesised solution.
5: search for fsm model and view it
6: Compile plugins and start a shell to run them
7: Switch to extended liberty file with pass through muxiplexers
8: run synthesis and visual for both liberty files
9: pass the circuit to mockturtle to process it into MuxIG graph
10: pass the circuit to mockturtle to process it into MIG graph
11: switch to different verilog file
# 4. CLI
You can also call the `./run.sh` with some arguments to work as a in-line tool if you want to automate stuff. The options are:
-d [DIRECTORY] synthesise all the files in the directory
-f [FILE_PATH] syntehsise specific path
-m [MODULE_NAME] When -f argument used
-v when present will also visuale the file.
-x Switch liberty file to extended version
# 5. Optimisation adjusments
the new extended libary makes use of trivial boolean equivalent muxiplexers and operators for AND and OR operations. More info will be added later.
# Bruteforce approach
In \bruteforce_approach\ are a couple c files to help with small bruteforce approaches to check a minimal circuit.
# 6. Troubleshooting
## 6.1. SAT comparison
If the SAT comparison gives a comment that it is not aware of a certain `_DFF_` cell such as `_DFF_PP0` then this specific memeory cell does not exist in the standard cell library therefore it does not have the function to simulate it. These register often have asynchronous reset therefore make sure that your design does not use
```
always@(posedge clk or posedge rst)
if (rst) begin
result <= 0;
......
```
but instead
```
always@(posedge clk)
if (rst) begin
result <= 0;
......
```
So that reset happens on the same clk as a normal `_DFF_` register.

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