synth_nem.ys
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synth_nem.ys
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	echo on

	# read the information
	read_verilog {{FILE}}
	hierarchy -top {{MODULE}}

	#unroll the information
	proc;
	opt -full;;

	#flatten the counter to its lower parts
	flatten;;

	fsm

	##show -prefix ./temp/{{MODULE}}_post_flatten {{MODULE}}

	#optimize
	opt -full;;

	##show -prefix ./temp/{{MODULE}}_post_flatten_opt {{MODULE}}

	#Map to gates using the standard techmap available
	techmap

	#opt -full;;

	#mapping memory
	dfflibmap -liberty ./nem_liberty/{{LIBERTY_FILE}};;

	#optimizing possible memory mapping
	opt -full;;

	##show -prefix ./temp/{{MODULE}}_post_techmap {{MODULE}}

	#USE BLIF TO IMPORT TO ABC
	#write_blif ./temp/{{MODULE}}_intermediate.blif

	#USE JSON TO IMPORT TO SVG TOOL: https://neilturley.dev/netlistsvg/
	#write_json ./temp/{{FILE_BASENAME}}_{{LIBERTY_USED}}.json

	#Replace basic combinational gates with those in our standard cell library
	#abc -liberty ./nem_basic_yosys.lib -script ./abc_script -showtmp
	abc -liberty ./nem_liberty/{{LIBERTY_FILE}}

	##show -prefix ./temp/{{MODULE}}_post_opt {{MODULE}}

	#Check if we can optimize further
	opt -full;;

	clean -purge

	#Write to file
	rename {{MODULE}} {{MODULE}}_nem
	write_verilog ./temp/{{FILE_BASENAME}}_nem.v

	#Output stats
	tee -o ./temp/{{FILE_BASENAME}}_{{LIBERTY_USED}}.stat stat -liberty ./nem_liberty/{{LIBERTY_FILE}}