No OneTemporary
Actions

Size

388 KB

Referenced Files

None

Subscribers

None

View Options

This file is larger than 256 KB, so syntax highlighting was skipped.

	diff --git a/ISCAS_but_muxig/c1355.ratio b/ISCAS_but_muxig/c1355.ratio
	deleted file mode 100644
	index 10eb8c3..0000000
	--- a/ISCAS_but_muxig/c1355.ratio
	+++ /dev/null
	@@ -1,85 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c1355_nem ===
	-
	- Number of wires: 227
	- Number of wire bits: 227
	- Number of public wires: 73
	- Number of public wire bits: 73
	- Number of ports: 73
	- Number of port bits: 73
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 186
	- and_3T 2
	- inv_3T 5
	- nand_3T 41
	- nor_3T 30
	- or_3T 3
	- xnor_3T 77
	- xor_3T 28
	-
	- Chip area for module '\c1355_nem': 1048072.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c1355_nem ===
	-
	- Number of wires: 221
	- Number of wire bits: 221
	- Number of public wires: 73
	- Number of public wire bits: 73
	- Number of ports: 73
	- Number of port bits: 73
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 180
	- and_4T 49
	- and_not_4T 18
	- inv_3T 1
	- or_4T 7
	- xnor_4T 91
	- xor_4T 14
	-
	- Chip area for module '\c1355_nem': 353512.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-
	-16. Printing statistics.
	-
	-=== c1355_nem ===
	-
	- Number of wires: 904
	- Number of wire bits: 904
	- Number of public wires: 73
	- Number of public wire bits: 73
	- Number of ports: 73
	- Number of port bits: 73
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 863
	- inv_3T 359
	- mux_4T 504
	-
	- Chip area for module '\c1355_nem': 1065592.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Stats ---------------
	-Area 3T: 1048072.000000
	-Area 4T: 353512.000000
	-Ratio 4T->3T: .33729743758062423192%
	-Area MUX: 1065592.000000
	-Ratio MUX->3T: 1.01671640879634223602%
	diff --git a/ISCAS_but_muxig/c17.ratio b/ISCAS_but_muxig/c17.ratio
	deleted file mode 100644
	index 8edc515..0000000
	--- a/ISCAS_but_muxig/c17.ratio
	+++ /dev/null
	@@ -1,76 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c17_nem ===
	-
	- Number of wires: 11
	- Number of wire bits: 11
	- Number of public wires: 7
	- Number of public wire bits: 7
	- Number of ports: 7
	- Number of port bits: 7
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 6
	- nand_3T 6
	-
	- Chip area for module '\c17_nem': 16992.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c17_nem ===
	-
	- Number of wires: 11
	- Number of wire bits: 11
	- Number of public wires: 7
	- Number of public wire bits: 7
	- Number of ports: 7
	- Number of port bits: 7
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 6
	- and_4T 2
	- and_not_4T 2
	- or_4T 2
	-
	- Chip area for module '\c17_nem': 7728.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-
	-16. Printing statistics.
	-
	-=== c17_nem ===
	-
	- Number of wires: 17
	- Number of wire bits: 17
	- Number of public wires: 7
	- Number of public wire bits: 7
	- Number of ports: 7
	- Number of port bits: 7
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 12
	- inv_3T 6
	- mux_4T 6
	-
	- Chip area for module '\c17_nem': 14688.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Stats ---------------
	-Area 3T: 16992.000000
	-Area 4T: 7728.000000
	-Ratio 4T->3T: .45480225988700564971%
	-Area MUX: 14688.000000
	-Ratio MUX->3T: .86440677966101694915%
	diff --git a/ISCAS_but_muxig/c1908.ratio b/ISCAS_but_muxig/c1908.ratio
	deleted file mode 100644
	index 54b84de..0000000
	--- a/ISCAS_but_muxig/c1908.ratio
	+++ /dev/null
	@@ -1,89 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c1908_nem ===
	-
	- Number of wires: 253
	- Number of wire bits: 253
	- Number of public wires: 58
	- Number of public wire bits: 58
	- Number of ports: 58
	- Number of port bits: 58
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 220
	- and_3T 12
	- inv_3T 9
	- mux_3T 2
	- nand_3T 58
	- nor_3T 54
	- or_3T 11
	- xnor_3T 58
	- xor_3T 16
	-
	- Chip area for module '\c1908_nem': 1013016.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c1908_nem ===
	-
	- Number of wires: 246
	- Number of wire bits: 246
	- Number of public wires: 58
	- Number of public wire bits: 58
	- Number of ports: 58
	- Number of port bits: 58
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 213
	- and_4T 48
	- and_not_4T 21
	- inv_3T 4
	- mux_4T 2
	- nor_3T 1
	- or_4T 39
	- or_not_4T 26
	- xnor_4T 56
	- xor_4T 16
	-
	- Chip area for module '\c1908_nem': 358896.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-
	-16. Printing statistics.
	-
	-=== c1908_nem ===
	-
	- Number of wires: 659
	- Number of wire bits: 659
	- Number of public wires: 58
	- Number of public wire bits: 58
	- Number of ports: 58
	- Number of port bits: 58
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 626
	- inv_3T 212
	- mux_4T 414
	-
	- Chip area for module '\c1908_nem': 779152.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Stats ---------------
	-Area 3T: 1013016.000000
	-Area 4T: 358896.000000
	-Ratio 4T->3T: .35428463123978298467%
	-Area MUX: 779152.000000
	-Ratio MUX->3T: .76914086253326699677%
	diff --git a/ISCAS_but_muxig/c2670.ratio b/ISCAS_but_muxig/c2670.ratio
	deleted file mode 100644
	index d232ad4..0000000
	--- a/ISCAS_but_muxig/c2670.ratio
	+++ /dev/null
	@@ -1,89 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c2670_nem ===
	-
	- Number of wires: 692
	- Number of wire bits: 692
	- Number of public wires: 373
	- Number of public wire bits: 373
	- Number of ports: 373
	- Number of port bits: 373
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 369
	- and_3T 30
	- inv_3T 31
	- mux_3T 64
	- nand_3T 103
	- nor_3T 81
	- or_3T 16
	- xnor_3T 33
	- xor_3T 11
	-
	- Chip area for module '\c2670_nem': 1593896.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c2670_nem ===
	-
	- Number of wires: 680
	- Number of wire bits: 680
	- Number of public wires: 373
	- Number of public wire bits: 373
	- Number of ports: 373
	- Number of port bits: 373
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 357
	- and_4T 89
	- and_not_4T 21
	- inv_3T 28
	- mux_4T 65
	- nand_4T 1
	- or_4T 61
	- or_not_4T 44
	- xnor_4T 32
	- xor_4T 16
	-
	- Chip area for module '\c2670_nem': 513072.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-
	-16. Printing statistics.
	-
	-=== c2670_nem ===
	-
	- Number of wires: 1441
	- Number of wire bits: 1441
	- Number of public wires: 373
	- Number of public wire bits: 373
	- Number of ports: 373
	- Number of port bits: 373
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1122
	- inv_3T 405
	- mux_4T 717
	-
	- Chip area for module '\c2670_nem': 1393296.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Stats ---------------
	-Area 3T: 1593896.000000
	-Area 4T: 513072.000000
	-Ratio 4T->3T: .32189804102651615914%
	-Area MUX: 1393296.000000
	-Ratio MUX->3T: .87414486265101361694%
	diff --git a/ISCAS_but_muxig/c3540.ratio b/ISCAS_but_muxig/c3540.ratio
	deleted file mode 100644
	index 9f6ddd6..0000000
	--- a/ISCAS_but_muxig/c3540.ratio
	+++ /dev/null
	@@ -1,88 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c3540_nem ===
	-
	- Number of wires: 882
	- Number of wire bits: 882
	- Number of public wires: 72
	- Number of public wire bits: 72
	- Number of ports: 72
	- Number of port bits: 72
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 832
	- and_3T 68
	- inv_3T 32
	- mux_3T 28
	- nand_3T 397
	- nor_3T 237
	- or_3T 32
	- xnor_3T 29
	- xor_3T 9
	-
	- Chip area for module '\c3540_nem': 2746400.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c3540_nem ===
	-
	- Number of wires: 830
	- Number of wire bits: 830
	- Number of public wires: 72
	- Number of public wire bits: 72
	- Number of ports: 72
	- Number of port bits: 72
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 780
	- and_4T 202
	- and_not_4T 148
	- inv_3T 17
	- mux_4T 46
	- or_4T 258
	- or_not_4T 62
	- xnor_4T 33
	- xor_4T 14
	-
	- Chip area for module '\c3540_nem': 1056984.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-
	-16. Printing statistics.
	-
	-=== c3540_nem ===
	-
	- Number of wires: 1566
	- Number of wire bits: 1566
	- Number of public wires: 72
	- Number of public wire bits: 72
	- Number of ports: 72
	- Number of port bits: 72
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1516
	- inv_3T 478
	- mux_4T 1038
	-
	- Chip area for module '\c3540_nem': 1891424.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Stats ---------------
	-Area 3T: 2746400.000000
	-Area 4T: 1056984.000000
	-Ratio 4T->3T: .38486163705214098456%
	-Area MUX: 1891424.000000
	-Ratio MUX->3T: .68869210602971162248%
	diff --git a/ISCAS_but_muxig/c432.ratio b/ISCAS_but_muxig/c432.ratio
	deleted file mode 100644
	index ee8e8fb..0000000
	--- a/ISCAS_but_muxig/c432.ratio
	+++ /dev/null
	@@ -1,82 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c432_nem ===
	-
	- Number of wires: 171
	- Number of wire bits: 171
	- Number of public wires: 43
	- Number of public wire bits: 43
	- Number of ports: 43
	- Number of port bits: 43
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 135
	- and_3T 8
	- inv_3T 12
	- nand_3T 40
	- nor_3T 72
	- or_3T 3
	-
	- Chip area for module '\c432_nem': 374256.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c432_nem ===
	-
	- Number of wires: 160
	- Number of wire bits: 160
	- Number of public wires: 43
	- Number of public wire bits: 43
	- Number of ports: 43
	- Number of port bits: 43
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 124
	- and_4T 31
	- and_not_4T 30
	- inv_3T 2
	- or_4T 44
	- or_not_4T 17
	-
	- Chip area for module '\c432_nem': 159456.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-
	-16. Printing statistics.
	-
	-=== c432_nem ===
	-
	- Number of wires: 352
	- Number of wire bits: 352
	- Number of public wires: 43
	- Number of public wire bits: 43
	- Number of ports: 43
	- Number of port bits: 43
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 316
	- inv_3T 107
	- mux_4T 209
	-
	- Chip area for module '\c432_nem': 393312.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Stats ---------------
	-Area 3T: 374256.000000
	-Area 4T: 159456.000000
	-Ratio 4T->3T: .42606130563037065538%
	-Area MUX: 393312.000000
	-Ratio MUX->3T: 1.05091701936642298319%
	diff --git a/ISCAS_but_muxig/c499.ratio b/ISCAS_but_muxig/c499.ratio
	deleted file mode 100644
	index 5a6518c..0000000
	--- a/ISCAS_but_muxig/c499.ratio
	+++ /dev/null
	@@ -1,86 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c499_nem ===
	-
	- Number of wires: 225
	- Number of wire bits: 225
	- Number of public wires: 73
	- Number of public wire bits: 73
	- Number of ports: 73
	- Number of port bits: 73
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 184
	- and_3T 1
	- inv_3T 4
	- nand_3T 54
	- nor_3T 14
	- or_3T 6
	- xnor_3T 99
	- xor_3T 6
	-
	- Chip area for module '\c499_nem': 1046360.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c499_nem ===
	-
	- Number of wires: 220
	- Number of wire bits: 220
	- Number of public wires: 73
	- Number of public wire bits: 73
	- Number of ports: 73
	- Number of port bits: 73
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 179
	- and_4T 38
	- and_not_4T 9
	- inv_3T 1
	- or_4T 9
	- or_not_4T 17
	- xnor_4T 79
	- xor_4T 26
	-
	- Chip area for module '\c499_nem': 352224.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-
	-16. Printing statistics.
	-
	-=== c499_nem ===
	-
	- Number of wires: 658
	- Number of wire bits: 658
	- Number of public wires: 73
	- Number of public wire bits: 73
	- Number of ports: 73
	- Number of port bits: 73
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 617
	- inv_3T 217
	- mux_4T 400
	-
	- Chip area for module '\c499_nem': 766920.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Stats ---------------
	-Area 3T: 1046360.000000
	-Area 4T: 352224.000000
	-Ratio 4T->3T: .33661837226193661837%
	-Area MUX: 766920.000000
	-Ratio MUX->3T: .73294086165373294086%
	diff --git a/ISCAS_but_muxig/c5315.ratio b/ISCAS_but_muxig/c5315.ratio
	deleted file mode 100644
	index adf7641..0000000
	--- a/ISCAS_but_muxig/c5315.ratio
	+++ /dev/null
	@@ -1,90 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c5315_nem ===
	-
	- Number of wires: 1203
	- Number of wire bits: 1203
	- Number of public wires: 301
	- Number of public wire bits: 301
	- Number of ports: 301
	- Number of port bits: 301
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1008
	- and_3T 67
	- inv_3T 74
	- mux_3T 121
	- nand_3T 348
	- nor_3T 266
	- or_3T 40
	- xnor_3T 72
	- xor_3T 20
	-
	- Chip area for module '\c5315_nem': 3932680.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c5315_nem ===
	-
	- Number of wires: 1158
	- Number of wire bits: 1158
	- Number of public wires: 301
	- Number of public wire bits: 301
	- Number of ports: 301
	- Number of port bits: 301
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 963
	- and_4T 207
	- and_not_4T 86
	- inv_3T 69
	- mux_4T 139
	- nand_4T 5
	- nor_3T 2
	- or_4T 244
	- or_not_4T 106
	- xnor_4T 75
	- xor_4T 30
	-
	- Chip area for module '\c5315_nem': 1362200.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-
	-16. Printing statistics.
	-
	-=== c5315_nem ===
	-
	- Number of wires: 2885
	- Number of wire bits: 2885
	- Number of public wires: 301
	- Number of public wire bits: 301
	- Number of ports: 301
	- Number of port bits: 301
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 2694
	- inv_3T 921
	- mux_4T 1773
	-
	- Chip area for module '\c5315_nem': 3351984.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Stats ---------------
	-Area 3T: 3932680.000000
	-Area 4T: 1362200.000000
	-Ratio 4T->3T: .34637956813165576655%
	-Area MUX: 3351984.000000
	-Ratio MUX->3T: .85234089730158568711%
	diff --git a/ISCAS_but_muxig/c6288.ratio b/ISCAS_but_muxig/c6288.ratio
	deleted file mode 100644
	index 0b75d26..0000000
	--- a/ISCAS_but_muxig/c6288.ratio
	+++ /dev/null
	@@ -1,88 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c6288_nem ===
	-
	- Number of wires: 1691
	- Number of wire bits: 1691
	- Number of public wires: 64
	- Number of public wire bits: 64
	- Number of ports: 64
	- Number of port bits: 64
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1659
	- and_3T 235
	- inv_3T 20
	- mux_3T 1
	- nand_3T 331
	- nor_3T 654
	- or_3T 189
	- xnor_3T 76
	- xor_3T 153
	-
	- Chip area for module '\c6288_nem': 6278664.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c6288_nem ===
	-
	- Number of wires: 1439
	- Number of wire bits: 1439
	- Number of public wires: 64
	- Number of public wire bits: 64
	- Number of ports: 64
	- Number of port bits: 64
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1407
	- and_4T 494
	- and_not_4T 17
	- mux_4T 1
	- nand_4T 154
	- or_4T 223
	- or_not_4T 57
	- xnor_4T 97
	- xor_4T 364
	-
	- Chip area for module '\c6288_nem': 2525616.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-
	-16. Printing statistics.
	-
	-=== c6288_nem ===
	-
	- Number of wires: 4435
	- Number of wire bits: 4435
	- Number of public wires: 64
	- Number of public wire bits: 64
	- Number of ports: 64
	- Number of port bits: 64
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 4403
	- inv_3T 2066
	- mux_4T 2337
	-
	- Chip area for module '\c6288_nem': 5406616.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Stats ---------------
	-Area 3T: 6278664.000000
	-Area 4T: 2525616.000000
	-Ratio 4T->3T: .40225372786312502150%
	-Area MUX: 5406616.000000
	-Ratio MUX->3T: .86110930605619284612%
	diff --git a/ISCAS_but_muxig/c7552.ratio b/ISCAS_but_muxig/c7552.ratio
	deleted file mode 100644
	index bbdd01b..0000000
	--- a/ISCAS_but_muxig/c7552.ratio
	+++ /dev/null
	@@ -1,89 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c7552_nem ===
	-
	- Number of wires: 1292
	- Number of wire bits: 1292
	- Number of public wires: 315
	- Number of public wire bits: 315
	- Number of ports: 315
	- Number of port bits: 315
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1035
	- and_3T 69
	- inv_3T 82
	- mux_3T 73
	- nand_3T 291
	- nor_3T 282
	- or_3T 63
	- xnor_3T 134
	- xor_3T 41
	-
	- Chip area for module '\c7552_nem': 4189960.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c7552_nem ===
	-
	- Number of wires: 1168
	- Number of wire bits: 1168
	- Number of public wires: 315
	- Number of public wire bits: 315
	- Number of ports: 315
	- Number of port bits: 315
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 911
	- and_4T 165
	- and_not_4T 102
	- inv_3T 48
	- mux_4T 127
	- nand_4T 5
	- or_4T 151
	- or_not_4T 100
	- xnor_4T 165
	- xor_4T 48
	-
	- Chip area for module '\c7552_nem': 1420104.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-
	-16. Printing statistics.
	-
	-=== c7552_nem ===
	-
	- Number of wires: 3594
	- Number of wire bits: 3594
	- Number of public wires: 315
	- Number of public wire bits: 315
	- Number of ports: 315
	- Number of port bits: 315
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 3344
	- inv_3T 1270
	- mux_4T 2074
	-
	- Chip area for module '\c7552_nem': 4144512.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Stats ---------------
	-Area 3T: 4189960.000000
	-Area 4T: 1420104.000000
	-Ratio 4T->3T: .33893020458429197414%
	-Area MUX: 4144512.000000
	-Ratio MUX->3T: .98915311840685829936%
	diff --git a/ISCAS_but_muxig/c880.ratio b/ISCAS_but_muxig/c880.ratio
	deleted file mode 100644
	index 76e3aaf..0000000
	--- a/ISCAS_but_muxig/c880.ratio
	+++ /dev/null
	@@ -1,87 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c880_nem ===
	-
	- Number of wires: 328
	- Number of wire bits: 328
	- Number of public wires: 86
	- Number of public wire bits: 86
	- Number of ports: 86
	- Number of port bits: 86
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 268
	- and_3T 30
	- inv_3T 14
	- nand_3T 119
	- nor_3T 77
	- or_3T 2
	- xnor_3T 13
	- xor_3T 13
	-
	- Chip area for module '\c880_nem': 900000.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c880_nem ===
	-
	- Number of wires: 316
	- Number of wire bits: 316
	- Number of public wires: 86
	- Number of public wire bits: 86
	- Number of ports: 86
	- Number of port bits: 86
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 256
	- and_4T 120
	- and_not_4T 13
	- inv_3T 2
	- nand_4T 1
	- or_4T 82
	- or_not_4T 5
	- xnor_4T 12
	- xor_4T 21
	-
	- Chip area for module '\c880_nem': 368912.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-
	-16. Printing statistics.
	-
	-=== c880_nem ===
	-
	- Number of wires: 556
	- Number of wire bits: 556
	- Number of public wires: 86
	- Number of public wire bits: 86
	- Number of ports: 86
	- Number of port bits: 86
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 496
	- inv_3T 169
	- mux_4T 327
	-
	- Chip area for module '\c880_nem': 617216.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Stats ---------------
	-Area 3T: 900000.000000
	-Area 4T: 368912.000000
	-Ratio 4T->3T: .40990222222222222222%
	-Area MUX: 617216.000000
	-Ratio MUX->3T: .68579555555555555555%
	diff --git a/ISCAS_but_muxig/output_report.csv b/ISCAS_but_muxig/output_report.csv
	deleted file mode 100644
	index f814c7a..0000000
	--- a/ISCAS_but_muxig/output_report.csv
	+++ /dev/null
	@@ -1,12 +0,0 @@
	-Module,3T,4T,Ratio
	-c1355_nem,1048072.000000,353512.000000,.33729743758062423192,1065592.000000,1.01671640879634223602
	-c17_nem,16992.000000,7728.000000,.45480225988700564971,14688.000000,.86440677966101694915
	-c1908_nem,1013016.000000,358896.000000,.35428463123978298467,779152.000000,.76914086253326699677
	-c2670_nem,1593896.000000,513072.000000,.32189804102651615914,1393296.000000,.87414486265101361694
	-c3540_nem,2746400.000000,1056984.000000,.38486163705214098456,1891424.000000,.68869210602971162248
	-c432_nem,374256.000000,159456.000000,.42606130563037065538,393312.000000,1.05091701936642298319
	-c499_nem,1046360.000000,352224.000000,.33661837226193661837,766920.000000,.73294086165373294086
	-c5315_nem,3932680.000000,1362200.000000,.34637956813165576655,3351984.000000,.85234089730158568711
	-c6288_nem,6278664.000000,2525616.000000,.40225372786312502150,5406616.000000,.86110930605619284612
	-c7552_nem,4189960.000000,1420104.000000,.33893020458429197414,4144512.000000,.98915311840685829936
	-c880_nem,900000.000000,368912.000000,.40990222222222222222,617216.000000,.68579555555555555555
	diff --git a/ISCAS_but_no_mux4T/c1355.ratio b/ISCAS_but_no_mux4T/c1355.ratio
	deleted file mode 100644
	index 9d188d4..0000000
	--- a/ISCAS_but_no_mux4T/c1355.ratio
	+++ /dev/null
	@@ -1,64 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c1355_nem ===
	-
	- Number of wires: 227
	- Number of wire bits: 227
	- Number of public wires: 73
	- Number of public wire bits: 73
	- Number of ports: 73
	- Number of port bits: 73
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 186
	- and_3T 2
	- inv_3T 5
	- nand_3T 41
	- nor_3T 30
	- or_3T 3
	- xnor_3T 77
	- xor_3T 28
	-
	- Chip area for module '\c1355_nem': 1048072.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c1355_nem ===
	-
	- Number of wires: 221
	- Number of wire bits: 221
	- Number of public wires: 73
	- Number of public wire bits: 73
	- Number of ports: 73
	- Number of port bits: 73
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 180
	- and_4T 49
	- and_not_4T 18
	- inv_3T 1
	- or_4T 7
	- xnor_4T 91
	- xor_4T 14
	-
	- Chip area for module '\c1355_nem': 353512.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 1048072.000000
	-Area 4T: 353512.000000
	-Ratio 4T->3T: .33729743758062423192%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/c17.ratio b/ISCAS_but_no_mux4T/c17.ratio
	deleted file mode 100644
	index 8f5fb09..0000000
	--- a/ISCAS_but_no_mux4T/c17.ratio
	+++ /dev/null
	@@ -1,55 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c17_nem ===
	-
	- Number of wires: 11
	- Number of wire bits: 11
	- Number of public wires: 7
	- Number of public wire bits: 7
	- Number of ports: 7
	- Number of port bits: 7
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 6
	- nand_3T 6
	-
	- Chip area for module '\c17_nem': 16992.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c17_nem ===
	-
	- Number of wires: 11
	- Number of wire bits: 11
	- Number of public wires: 7
	- Number of public wire bits: 7
	- Number of ports: 7
	- Number of port bits: 7
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 6
	- and_4T 2
	- and_not_4T 2
	- or_4T 2
	-
	- Chip area for module '\c17_nem': 7728.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 16992.000000
	-Area 4T: 7728.000000
	-Ratio 4T->3T: .45480225988700564971%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/c1908.ratio b/ISCAS_but_no_mux4T/c1908.ratio
	deleted file mode 100644
	index 7b9a07c..0000000
	--- a/ISCAS_but_no_mux4T/c1908.ratio
	+++ /dev/null
	@@ -1,68 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c1908_nem ===
	-
	- Number of wires: 253
	- Number of wire bits: 253
	- Number of public wires: 58
	- Number of public wire bits: 58
	- Number of ports: 58
	- Number of port bits: 58
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 220
	- and_3T 12
	- inv_3T 9
	- mux_3T 2
	- nand_3T 58
	- nor_3T 54
	- or_3T 11
	- xnor_3T 58
	- xor_3T 16
	-
	- Chip area for module '\c1908_nem': 1013016.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c1908_nem ===
	-
	- Number of wires: 246
	- Number of wire bits: 246
	- Number of public wires: 58
	- Number of public wire bits: 58
	- Number of ports: 58
	- Number of port bits: 58
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 213
	- and_4T 48
	- and_not_4T 21
	- inv_3T 4
	- mux_4T 2
	- nor_3T 1
	- or_4T 39
	- or_not_4T 26
	- xnor_4T 56
	- xor_4T 16
	-
	- Chip area for module '\c1908_nem': 358896.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 1013016.000000
	-Area 4T: 358896.000000
	-Ratio 4T->3T: .35428463123978298467%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/c2670.ratio b/ISCAS_but_no_mux4T/c2670.ratio
	deleted file mode 100644
	index 1ecaeb3..0000000
	--- a/ISCAS_but_no_mux4T/c2670.ratio
	+++ /dev/null
	@@ -1,68 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c2670_nem ===
	-
	- Number of wires: 692
	- Number of wire bits: 692
	- Number of public wires: 373
	- Number of public wire bits: 373
	- Number of ports: 373
	- Number of port bits: 373
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 369
	- and_3T 30
	- inv_3T 31
	- mux_3T 64
	- nand_3T 103
	- nor_3T 81
	- or_3T 16
	- xnor_3T 33
	- xor_3T 11
	-
	- Chip area for module '\c2670_nem': 1593896.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c2670_nem ===
	-
	- Number of wires: 680
	- Number of wire bits: 680
	- Number of public wires: 373
	- Number of public wire bits: 373
	- Number of ports: 373
	- Number of port bits: 373
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 357
	- and_4T 89
	- and_not_4T 21
	- inv_3T 28
	- mux_4T 65
	- nand_4T 1
	- or_4T 61
	- or_not_4T 44
	- xnor_4T 32
	- xor_4T 16
	-
	- Chip area for module '\c2670_nem': 513072.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 1593896.000000
	-Area 4T: 513072.000000
	-Ratio 4T->3T: .32189804102651615914%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/c3540.ratio b/ISCAS_but_no_mux4T/c3540.ratio
	deleted file mode 100644
	index 2524973..0000000
	--- a/ISCAS_but_no_mux4T/c3540.ratio
	+++ /dev/null
	@@ -1,67 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c3540_nem ===
	-
	- Number of wires: 882
	- Number of wire bits: 882
	- Number of public wires: 72
	- Number of public wire bits: 72
	- Number of ports: 72
	- Number of port bits: 72
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 832
	- and_3T 68
	- inv_3T 32
	- mux_3T 28
	- nand_3T 397
	- nor_3T 237
	- or_3T 32
	- xnor_3T 29
	- xor_3T 9
	-
	- Chip area for module '\c3540_nem': 2746400.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c3540_nem ===
	-
	- Number of wires: 830
	- Number of wire bits: 830
	- Number of public wires: 72
	- Number of public wire bits: 72
	- Number of ports: 72
	- Number of port bits: 72
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 780
	- and_4T 202
	- and_not_4T 148
	- inv_3T 17
	- mux_4T 46
	- or_4T 258
	- or_not_4T 62
	- xnor_4T 33
	- xor_4T 14
	-
	- Chip area for module '\c3540_nem': 1056984.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 2746400.000000
	-Area 4T: 1056984.000000
	-Ratio 4T->3T: .38486163705214098456%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/c432.ratio b/ISCAS_but_no_mux4T/c432.ratio
	deleted file mode 100644
	index 71b1e2b..0000000
	--- a/ISCAS_but_no_mux4T/c432.ratio
	+++ /dev/null
	@@ -1,61 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c432_nem ===
	-
	- Number of wires: 171
	- Number of wire bits: 171
	- Number of public wires: 43
	- Number of public wire bits: 43
	- Number of ports: 43
	- Number of port bits: 43
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 135
	- and_3T 8
	- inv_3T 12
	- nand_3T 40
	- nor_3T 72
	- or_3T 3
	-
	- Chip area for module '\c432_nem': 374256.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c432_nem ===
	-
	- Number of wires: 160
	- Number of wire bits: 160
	- Number of public wires: 43
	- Number of public wire bits: 43
	- Number of ports: 43
	- Number of port bits: 43
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 124
	- and_4T 31
	- and_not_4T 30
	- inv_3T 2
	- or_4T 44
	- or_not_4T 17
	-
	- Chip area for module '\c432_nem': 159456.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 374256.000000
	-Area 4T: 159456.000000
	-Ratio 4T->3T: .42606130563037065538%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/c499.ratio b/ISCAS_but_no_mux4T/c499.ratio
	deleted file mode 100644
	index ca68f4a..0000000
	--- a/ISCAS_but_no_mux4T/c499.ratio
	+++ /dev/null
	@@ -1,65 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c499_nem ===
	-
	- Number of wires: 225
	- Number of wire bits: 225
	- Number of public wires: 73
	- Number of public wire bits: 73
	- Number of ports: 73
	- Number of port bits: 73
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 184
	- and_3T 1
	- inv_3T 4
	- nand_3T 54
	- nor_3T 14
	- or_3T 6
	- xnor_3T 99
	- xor_3T 6
	-
	- Chip area for module '\c499_nem': 1046360.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c499_nem ===
	-
	- Number of wires: 220
	- Number of wire bits: 220
	- Number of public wires: 73
	- Number of public wire bits: 73
	- Number of ports: 73
	- Number of port bits: 73
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 179
	- and_4T 38
	- and_not_4T 9
	- inv_3T 1
	- or_4T 9
	- or_not_4T 17
	- xnor_4T 79
	- xor_4T 26
	-
	- Chip area for module '\c499_nem': 352224.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 1046360.000000
	-Area 4T: 352224.000000
	-Ratio 4T->3T: .33661837226193661837%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/c5315.ratio b/ISCAS_but_no_mux4T/c5315.ratio
	deleted file mode 100644
	index 1e038e6..0000000
	--- a/ISCAS_but_no_mux4T/c5315.ratio
	+++ /dev/null
	@@ -1,69 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c5315_nem ===
	-
	- Number of wires: 1203
	- Number of wire bits: 1203
	- Number of public wires: 301
	- Number of public wire bits: 301
	- Number of ports: 301
	- Number of port bits: 301
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1008
	- and_3T 67
	- inv_3T 74
	- mux_3T 121
	- nand_3T 348
	- nor_3T 266
	- or_3T 40
	- xnor_3T 72
	- xor_3T 20
	-
	- Chip area for module '\c5315_nem': 3932680.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c5315_nem ===
	-
	- Number of wires: 1158
	- Number of wire bits: 1158
	- Number of public wires: 301
	- Number of public wire bits: 301
	- Number of ports: 301
	- Number of port bits: 301
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 963
	- and_4T 207
	- and_not_4T 86
	- inv_3T 69
	- mux_4T 139
	- nand_4T 5
	- nor_3T 2
	- or_4T 244
	- or_not_4T 106
	- xnor_4T 75
	- xor_4T 30
	-
	- Chip area for module '\c5315_nem': 1362200.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 3932680.000000
	-Area 4T: 1362200.000000
	-Ratio 4T->3T: .34637956813165576655%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/c6288.ratio b/ISCAS_but_no_mux4T/c6288.ratio
	deleted file mode 100644
	index f8feb88..0000000
	--- a/ISCAS_but_no_mux4T/c6288.ratio
	+++ /dev/null
	@@ -1,67 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c6288_nem ===
	-
	- Number of wires: 1691
	- Number of wire bits: 1691
	- Number of public wires: 64
	- Number of public wire bits: 64
	- Number of ports: 64
	- Number of port bits: 64
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1659
	- and_3T 235
	- inv_3T 20
	- mux_3T 1
	- nand_3T 331
	- nor_3T 654
	- or_3T 189
	- xnor_3T 76
	- xor_3T 153
	-
	- Chip area for module '\c6288_nem': 6278664.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c6288_nem ===
	-
	- Number of wires: 1439
	- Number of wire bits: 1439
	- Number of public wires: 64
	- Number of public wire bits: 64
	- Number of ports: 64
	- Number of port bits: 64
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1407
	- and_4T 494
	- and_not_4T 17
	- mux_4T 1
	- nand_4T 154
	- or_4T 223
	- or_not_4T 57
	- xnor_4T 97
	- xor_4T 364
	-
	- Chip area for module '\c6288_nem': 2525616.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 6278664.000000
	-Area 4T: 2525616.000000
	-Ratio 4T->3T: .40225372786312502150%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/c7552.ratio b/ISCAS_but_no_mux4T/c7552.ratio
	deleted file mode 100644
	index 85c9a8d..0000000
	--- a/ISCAS_but_no_mux4T/c7552.ratio
	+++ /dev/null
	@@ -1,68 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c7552_nem ===
	-
	- Number of wires: 1292
	- Number of wire bits: 1292
	- Number of public wires: 315
	- Number of public wire bits: 315
	- Number of ports: 315
	- Number of port bits: 315
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1035
	- and_3T 69
	- inv_3T 82
	- mux_3T 73
	- nand_3T 291
	- nor_3T 282
	- or_3T 63
	- xnor_3T 134
	- xor_3T 41
	-
	- Chip area for module '\c7552_nem': 4189960.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c7552_nem ===
	-
	- Number of wires: 1168
	- Number of wire bits: 1168
	- Number of public wires: 315
	- Number of public wire bits: 315
	- Number of ports: 315
	- Number of port bits: 315
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 911
	- and_4T 165
	- and_not_4T 102
	- inv_3T 48
	- mux_4T 127
	- nand_4T 5
	- or_4T 151
	- or_not_4T 100
	- xnor_4T 165
	- xor_4T 48
	-
	- Chip area for module '\c7552_nem': 1420104.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 4189960.000000
	-Area 4T: 1420104.000000
	-Ratio 4T->3T: .33893020458429197414%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/c880.ratio b/ISCAS_but_no_mux4T/c880.ratio
	deleted file mode 100644
	index ae1dd95..0000000
	--- a/ISCAS_but_no_mux4T/c880.ratio
	+++ /dev/null
	@@ -1,66 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c880_nem ===
	-
	- Number of wires: 328
	- Number of wire bits: 328
	- Number of public wires: 86
	- Number of public wire bits: 86
	- Number of ports: 86
	- Number of port bits: 86
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 268
	- and_3T 30
	- inv_3T 14
	- nand_3T 119
	- nor_3T 77
	- or_3T 2
	- xnor_3T 13
	- xor_3T 13
	-
	- Chip area for module '\c880_nem': 900000.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c880_nem ===
	-
	- Number of wires: 316
	- Number of wire bits: 316
	- Number of public wires: 86
	- Number of public wire bits: 86
	- Number of ports: 86
	- Number of port bits: 86
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 256
	- and_4T 120
	- and_not_4T 13
	- inv_3T 2
	- nand_4T 1
	- or_4T 82
	- or_not_4T 5
	- xnor_4T 12
	- xor_4T 21
	-
	- Chip area for module '\c880_nem': 368912.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 900000.000000
	-Area 4T: 368912.000000
	-Ratio 4T->3T: .40990222222222222222%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/output_report.csv b/ISCAS_but_no_mux4T/output_report.csv
	deleted file mode 100644
	index 9f53773..0000000
	--- a/ISCAS_but_no_mux4T/output_report.csv
	+++ /dev/null
	@@ -1,27 +0,0 @@
	-Module,3T,4T,Ratio
	-c1355_nem,1048072.000000,353512.000000,.33729743758062423192,,
	-c17_nem,16992.000000,7728.000000,.45480225988700564971,,
	-c1908_nem,1013016.000000,358896.000000,.35428463123978298467,,
	-c2670_nem,1593896.000000,513072.000000,.32189804102651615914,,
	-c3540_nem,2746400.000000,1056984.000000,.38486163705214098456,,
	-c432_nem,374256.000000,159456.000000,.42606130563037065538,,
	-c499_nem,1046360.000000,352224.000000,.33661837226193661837,,
	-c5315_nem,3932680.000000,1362200.000000,.34637956813165576655,,
	-c6288_nem,6278664.000000,2525616.000000,.40225372786312502150,,
	-c7552_nem,4189960.000000,1420104.000000,.33893020458429197414,,
	-c880_nem,900000.000000,368912.000000,.40990222222222222222,,
	-s1238_nem,1804408.000000,965480.000000,.53506745702745720480,,
	-s13207_nem,15906776.000000,12011112.000000,.75509405551445497189,,
	-s1423_nem,2854152.000000,1978632.000000,.69324689084533689866,,
	-s1488_nem,1922200.000000,872016.000000,.45365518676516491520,,
	-s15850_nem,18551424.000000,13091264.000000,.70567434607715289133,,
	-s27_nem,84552.000000,71504.000000,.84568076449995269183,,
	-s35932_nem,58830640.000000,42941576.000000,.72991855944453434468,,
	-s382_nem,783040.000000,560032.000000,.71520228851655087862,,
	-s38417_nem,53702264.000000,38505624.000000,.71702049656602932047,,
	-s38584_nem,58685760.000000,40057032.000000,.68256817326724575092,,
	-s420_nem,713176.000000,457688.000000,.64176023870685496988,,
	-s5378_nem,6285504.000000,4483744.000000,.71334677378297746688,,
	-s641_nem,728536.000000,516520.000000,.70898349566802464119,,
	-s713_nem,735368.000000,515360.000000,.70081918168862392706,,
	-s9234_nem,5215368.000000,3654304.000000,.70067999036693096249,,
	diff --git a/ISCAS_but_no_mux4T/s1238.ratio b/ISCAS_but_no_mux4T/s1238.ratio
	deleted file mode 100644
	index 5a8277b..0000000
	--- a/ISCAS_but_no_mux4T/s1238.ratio
	+++ /dev/null
	@@ -1,74 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s1238_nem ===
	-
	- Number of wires: 553
	- Number of wire bits: 553
	- Number of public wires: 71
	- Number of public wire bits: 71
	- Number of ports: 29
	- Number of port bits: 29
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 538
	- $scopeinfo 18
	- D_FF 18
	- and_3T 29
	- inv_3T 30
	- mux_3T 2
	- nand_3T 218
	- nor_3T 196
	- or_3T 27
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s1238_nem': 1804408.000000
	- of which used for sequential elements: 361008.000000 (20.01%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s1238_nem ===
	-
	- Number of wires: 517
	- Number of wire bits: 517
	- Number of public wires: 71
	- Number of public wire bits: 71
	- Number of ports: 29
	- Number of port bits: 29
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 502
	- $scopeinfo 18
	- D_FF 18
	- and_4T 169
	- and_not_4T 86
	- inv_3T 12
	- mux_4T 15
	- nand_4T 1
	- or_4T 120
	- or_not_4T 59
	- xnor_4T 2
	- xor_4T 2
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s1238_nem': 965480.000000
	- of which used for sequential elements: 361008.000000 (37.39%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 1804408.000000
	-Area 4T: 965480.000000
	-Ratio 4T->3T: .53506745702745720480%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/s13207.ratio b/ISCAS_but_no_mux4T/s13207.ratio
	deleted file mode 100644
	index a7bafad..0000000
	--- a/ISCAS_but_no_mux4T/s13207.ratio
	+++ /dev/null
	@@ -1,79 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s13207_nem ===
	-
	- Number of wires: 2840
	- Number of wire bits: 2840
	- Number of public wires: 1126
	- Number of public wire bits: 1126
	- Number of ports: 215
	- Number of port bits: 215
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 2867
	- $scopeinfo 627
	- D_FF 484
	- and_3T 143
	- buf_3T 1
	- inv_3T 112
	- mux_3T 142
	- nand_3T 710
	- nor_3T 472
	- or_3T 91
	- xnor_3T 46
	- xor_3T 39
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s13207_nem': 15906776.000000
	- of which used for sequential elements: 9707104.000000 (61.02%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s13207_nem ===
	-
	- Number of wires: 2782
	- Number of wire bits: 2782
	- Number of public wires: 1126
	- Number of public wire bits: 1126
	- Number of ports: 215
	- Number of port bits: 215
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 2809
	- $scopeinfo 627
	- D_FF 484
	- and_4T 666
	- and_not_4T 120
	- buf_3T 1
	- inv_3T 39
	- mux_4T 143
	- nand_4T 5
	- nor_3T 1
	- or_4T 526
	- or_not_4T 99
	- xnor_4T 47
	- xor_4T 51
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s13207_nem': 12011112.000000
	- of which used for sequential elements: 9707104.000000 (80.82%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 15906776.000000
	-Area 4T: 12011112.000000
	-Ratio 4T->3T: .75509405551445497189%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/s1423.ratio b/ISCAS_but_no_mux4T/s1423.ratio
	deleted file mode 100644
	index 08c4af7..0000000
	--- a/ISCAS_but_no_mux4T/s1423.ratio
	+++ /dev/null
	@@ -1,76 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s1423_nem ===
	-
	- Number of wires: 573
	- Number of wire bits: 573
	- Number of public wires: 186
	- Number of public wire bits: 186
	- Number of ports: 23
	- Number of port bits: 23
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 555
	- $scopeinfo 74
	- D_FF 74
	- and_3T 42
	- inv_3T 37
	- mux_3T 26
	- nand_3T 89
	- nor_3T 176
	- or_3T 22
	- xnor_3T 12
	- xor_3T 3
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s1423_nem': 2854152.000000
	- of which used for sequential elements: 1484144.000000 (52.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s1423_nem ===
	-
	- Number of wires: 527
	- Number of wire bits: 527
	- Number of public wires: 186
	- Number of public wire bits: 186
	- Number of ports: 23
	- Number of port bits: 23
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 509
	- $scopeinfo 74
	- D_FF 74
	- and_4T 141
	- and_not_4T 54
	- inv_3T 5
	- mux_4T 27
	- nand_4T 1
	- or_4T 85
	- or_not_4T 23
	- xnor_4T 13
	- xor_4T 12
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s1423_nem': 1978632.000000
	- of which used for sequential elements: 1484144.000000 (75.01%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 2854152.000000
	-Area 4T: 1978632.000000
	-Ratio 4T->3T: .69324689084533689866%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/s1488.ratio b/ISCAS_but_no_mux4T/s1488.ratio
	deleted file mode 100644
	index 1e6044d..0000000
	--- a/ISCAS_but_no_mux4T/s1488.ratio
	+++ /dev/null
	@@ -1,71 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s1488_nem ===
	-
	- Number of wires: 647
	- Number of wire bits: 647
	- Number of public wires: 46
	- Number of public wire bits: 46
	- Number of ports: 28
	- Number of port bits: 28
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 638
	- $scopeinfo 6
	- D_FF 6
	- and_3T 50
	- inv_3T 29
	- nand_3T 301
	- nor_3T 225
	- or_3T 21
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s1488_nem': 1922200.000000
	- of which used for sequential elements: 120336.000000 (6.26%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s1488_nem ===
	-
	- Number of wires: 604
	- Number of wire bits: 604
	- Number of public wires: 46
	- Number of public wire bits: 46
	- Number of ports: 28
	- Number of port bits: 28
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 595
	- $scopeinfo 6
	- D_FF 6
	- and_4T 225
	- and_not_4T 100
	- inv_3T 3
	- mux_4T 3
	- or_4T 187
	- or_not_4T 64
	- xor_4T 1
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s1488_nem': 872016.000000
	- of which used for sequential elements: 120336.000000 (13.80%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 1922200.000000
	-Area 4T: 872016.000000
	-Ratio 4T->3T: .45365518676516491520%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/s15850.ratio b/ISCAS_but_no_mux4T/s15850.ratio
	deleted file mode 100644
	index 59c1a5b..0000000
	--- a/ISCAS_but_no_mux4T/s15850.ratio
	+++ /dev/null
	@@ -1,78 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s15850_nem ===
	-
	- Number of wires: 3430
	- Number of wire bits: 3430
	- Number of public wires: 1306
	- Number of public wire bits: 1306
	- Number of ports: 228
	- Number of port bits: 228
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 3283
	- $scopeinfo 527
	- D_FF 515
	- and_3T 211
	- buf_3T 11
	- inv_3T 154
	- mux_3T 216
	- nand_3T 811
	- nor_3T 601
	- or_3T 100
	- xnor_3T 90
	- xor_3T 47
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s15850_nem': 18551424.000000
	- of which used for sequential elements: 10328840.000000 (55.68%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s15850_nem ===
	-
	- Number of wires: 3196
	- Number of wire bits: 3196
	- Number of public wires: 1306
	- Number of public wire bits: 1306
	- Number of ports: 228
	- Number of port bits: 228
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 3049
	- $scopeinfo 527
	- D_FF 515
	- and_4T 693
	- and_not_4T 229
	- buf_3T 11
	- inv_3T 28
	- mux_4T 275
	- nand_4T 2
	- or_4T 542
	- or_not_4T 82
	- xnor_4T 72
	- xor_4T 73
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s15850_nem': 13091264.000000
	- of which used for sequential elements: 10328840.000000 (78.90%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 18551424.000000
	-Area 4T: 13091264.000000
	-Ratio 4T->3T: .70567434607715289133%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/s27.ratio b/ISCAS_but_no_mux4T/s27.ratio
	deleted file mode 100644
	index 7aeff4e..0000000
	--- a/ISCAS_but_no_mux4T/s27.ratio
	+++ /dev/null
	@@ -1,68 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s27_nem ===
	-
	- Number of wires: 21
	- Number of wire bits: 21
	- Number of public wires: 12
	- Number of public wire bits: 12
	- Number of ports: 6
	- Number of port bits: 6
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 16
	- $scopeinfo 3
	- D_FF 3
	- and_3T 1
	- inv_3T 3
	- nand_3T 4
	- nor_3T 2
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s27_nem': 84552.000000
	- of which used for sequential elements: 60168.000000 (71.16%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s27_nem ===
	-
	- Number of wires: 20
	- Number of wire bits: 20
	- Number of public wires: 12
	- Number of public wire bits: 12
	- Number of ports: 6
	- Number of port bits: 6
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 15
	- $scopeinfo 3
	- D_FF 3
	- and_4T 2
	- and_not_4T 2
	- inv_3T 2
	- or_4T 2
	- or_not_4T 1
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s27_nem': 71504.000000
	- of which used for sequential elements: 60168.000000 (84.15%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 84552.000000
	-Area 4T: 71504.000000
	-Ratio 4T->3T: .84568076449995269183%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/s35932.ratio b/ISCAS_but_no_mux4T/s35932.ratio
	deleted file mode 100644
	index 2419ba4..0000000
	--- a/ISCAS_but_no_mux4T/s35932.ratio
	+++ /dev/null
	@@ -1,75 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s35932_nem ===
	-
	- Number of wires: 9206
	- Number of wire bits: 9206
	- Number of public wires: 3821
	- Number of public wire bits: 3821
	- Number of ports: 356
	- Number of port bits: 356
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 9170
	- $scopeinfo 1728
	- D_FF 1728
	- and_3T 1685
	- inv_3T 1
	- mux_3T 32
	- nand_3T 1446
	- nor_3T 1334
	- or_3T 16
	- xnor_3T 592
	- xor_3T 608
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s35932_nem': 58830640.000000
	- of which used for sequential elements: 34656768.000000 (58.91%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s35932_nem ===
	-
	- Number of wires: 8853
	- Number of wire bits: 8853
	- Number of public wires: 3821
	- Number of public wire bits: 3821
	- Number of ports: 356
	- Number of port bits: 356
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 8817
	- $scopeinfo 1728
	- D_FF 1728
	- and_4T 2251
	- and_not_4T 155
	- inv_3T 240
	- mux_4T 384
	- or_4T 507
	- or_not_4T 608
	- xnor_4T 768
	- xor_4T 448
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s35932_nem': 42941576.000000
	- of which used for sequential elements: 34656768.000000 (80.71%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 58830640.000000
	-Area 4T: 42941576.000000
	-Ratio 4T->3T: .72991855944453434468%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/s382.ratio b/ISCAS_but_no_mux4T/s382.ratio
	deleted file mode 100644
	index 46c701f..0000000
	--- a/ISCAS_but_no_mux4T/s382.ratio
	+++ /dev/null
	@@ -1,75 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s382_nem ===
	-
	- Number of wires: 154
	- Number of wire bits: 154
	- Number of public wires: 63
	- Number of public wire bits: 63
	- Number of ports: 10
	- Number of port bits: 10
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 150
	- $scopeinfo 21
	- D_FF 21
	- and_3T 10
	- inv_3T 7
	- mux_3T 1
	- nand_3T 18
	- nor_3T 50
	- or_3T 15
	- xnor_3T 2
	- xor_3T 5
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s382_nem': 783040.000000
	- of which used for sequential elements: 421176.000000 (53.79%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s382_nem ===
	-
	- Number of wires: 147
	- Number of wire bits: 147
	- Number of public wires: 63
	- Number of public wire bits: 63
	- Number of ports: 10
	- Number of port bits: 10
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 143
	- $scopeinfo 21
	- D_FF 21
	- and_4T 29
	- and_not_4T 19
	- inv_3T 4
	- mux_4T 3
	- or_4T 28
	- or_not_4T 10
	- xnor_4T 5
	- xor_4T 3
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s382_nem': 560032.000000
	- of which used for sequential elements: 421176.000000 (75.21%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 783040.000000
	-Area 4T: 560032.000000
	-Ratio 4T->3T: .71520228851655087862%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/s38417.ratio b/ISCAS_but_no_mux4T/s38417.ratio
	deleted file mode 100644
	index 655db41..0000000
	--- a/ISCAS_but_no_mux4T/s38417.ratio
	+++ /dev/null
	@@ -1,76 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s38417_nem ===
	-
	- Number of wires: 10029
	- Number of wire bits: 10029
	- Number of public wires: 3862
	- Number of public wire bits: 3862
	- Number of ports: 135
	- Number of port bits: 135
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 10052
	- $scopeinfo 1564
	- D_FF 1463
	- and_3T 993
	- inv_3T 639
	- mux_3T 562
	- nand_3T 3110
	- nor_3T 1278
	- or_3T 169
	- xnor_3T 177
	- xor_3T 97
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s38417_nem': 53702264.000000
	- of which used for sequential elements: 29341928.000000 (54.64%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s38417_nem ===
	-
	- Number of wires: 9824
	- Number of wire bits: 9824
	- Number of public wires: 3862
	- Number of public wire bits: 3862
	- Number of ports: 135
	- Number of port bits: 135
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 9847
	- $scopeinfo 1564
	- D_FF 1463
	- and_4T 1982
	- and_not_4T 913
	- inv_3T 533
	- mux_4T 600
	- nand_4T 103
	- or_4T 1451
	- or_not_4T 955
	- xnor_4T 148
	- xor_4T 135
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s38417_nem': 38505624.000000
	- of which used for sequential elements: 29341928.000000 (76.20%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 53702264.000000
	-Area 4T: 38505624.000000
	-Ratio 4T->3T: .71702049656602932047%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/s38584.ratio b/ISCAS_but_no_mux4T/s38584.ratio
	deleted file mode 100644
	index 5e4cb3d..0000000
	--- a/ISCAS_but_no_mux4T/s38584.ratio
	+++ /dev/null
	@@ -1,79 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s38584_nem ===
	-
	- Number of wires: 12224
	- Number of wire bits: 12224
	- Number of public wires: 3793
	- Number of public wire bits: 3793
	- Number of ports: 343
	- Number of port bits: 343
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 12099
	- $scopeinfo 1426
	- D_FF 1423
	- and_3T 483
	- buf_3T 7
	- inv_3T 444
	- mux_3T 554
	- nand_3T 4302
	- nor_3T 2828
	- or_3T 476
	- xnor_3T 55
	- xor_3T 101
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s38584_nem': 58685760.000000
	- of which used for sequential elements: 28539688.000000 (48.63%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s38584_nem ===
	-
	- Number of wires: 11740
	- Number of wire bits: 11740
	- Number of public wires: 3793
	- Number of public wire bits: 3793
	- Number of ports: 343
	- Number of port bits: 343
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 11615
	- $scopeinfo 1426
	- D_FF 1423
	- and_4T 2838
	- and_not_4T 1473
	- buf_3T 7
	- inv_3T 78
	- mux_4T 635
	- nand_4T 32
	- nor_3T 4
	- or_4T 2537
	- or_not_4T 1001
	- xnor_4T 51
	- xor_4T 110
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s38584_nem': 40057032.000000
	- of which used for sequential elements: 28539688.000000 (71.25%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 58685760.000000
	-Area 4T: 40057032.000000
	-Ratio 4T->3T: .68256817326724575092%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/s420.ratio b/ISCAS_but_no_mux4T/s420.ratio
	deleted file mode 100644
	index 6939115..0000000
	--- a/ISCAS_but_no_mux4T/s420.ratio
	+++ /dev/null
	@@ -1,74 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s420_nem ===
	-
	- Number of wires: 179
	- Number of wire bits: 179
	- Number of public wires: 68
	- Number of public wire bits: 68
	- Number of ports: 20
	- Number of port bits: 20
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 160
	- $scopeinfo 16
	- D_FF 16
	- and_3T 14
	- inv_3T 21
	- mux_3T 5
	- nand_3T 44
	- nor_3T 33
	- or_3T 8
	- xnor_3T 2
	- xor_3T 1
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s420_nem': 713176.000000
	- of which used for sequential elements: 320896.000000 (45.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s420_nem ===
	-
	- Number of wires: 155
	- Number of wire bits: 155
	- Number of public wires: 68
	- Number of public wire bits: 68
	- Number of ports: 20
	- Number of port bits: 20
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 136
	- $scopeinfo 16
	- D_FF 16
	- and_4T 21
	- and_not_4T 27
	- inv_3T 5
	- mux_4T 13
	- or_4T 31
	- or_not_4T 4
	- xnor_4T 3
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s420_nem': 457688.000000
	- of which used for sequential elements: 320896.000000 (70.11%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 713176.000000
	-Area 4T: 457688.000000
	-Ratio 4T->3T: .64176023870685496988%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/s5378.ratio b/ISCAS_but_no_mux4T/s5378.ratio
	deleted file mode 100644
	index 0ef2c19..0000000
	--- a/ISCAS_but_no_mux4T/s5378.ratio
	+++ /dev/null
	@@ -1,76 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s5378_nem ===
	-
	- Number of wires: 1384
	- Number of wire bits: 1384
	- Number of public wires: 489
	- Number of public wire bits: 489
	- Number of ports: 85
	- Number of port bits: 85
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1361
	- $scopeinfo 179
	- D_FF 160
	- and_3T 52
	- inv_3T 74
	- mux_3T 17
	- nand_3T 311
	- nor_3T 496
	- or_3T 51
	- xnor_3T 17
	- xor_3T 4
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s5378_nem': 6285504.000000
	- of which used for sequential elements: 3208960.000000 (51.05%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s5378_nem ===
	-
	- Number of wires: 1326
	- Number of wire bits: 1326
	- Number of public wires: 489
	- Number of public wire bits: 489
	- Number of ports: 85
	- Number of port bits: 85
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1303
	- $scopeinfo 179
	- D_FF 160
	- and_4T 242
	- and_not_4T 123
	- inv_3T 31
	- mux_4T 27
	- nand_4T 10
	- or_4T 407
	- or_not_4T 102
	- xnor_4T 15
	- xor_4T 7
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s5378_nem': 4483744.000000
	- of which used for sequential elements: 3208960.000000 (71.57%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 6285504.000000
	-Area 4T: 4483744.000000
	-Ratio 4T->3T: .71334677378297746688%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/s641.ratio b/ISCAS_but_no_mux4T/s641.ratio
	deleted file mode 100644
	index 058417a..0000000
	--- a/ISCAS_but_no_mux4T/s641.ratio
	+++ /dev/null
	@@ -1,70 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s641_nem ===
	-
	- Number of wires: 216
	- Number of wire bits: 216
	- Number of public wires: 93
	- Number of public wire bits: 93
	- Number of ports: 60
	- Number of port bits: 60
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 180
	- $scopeinfo 19
	- D_FF 17
	- and_3T 6
	- inv_3T 22
	- nand_3T 67
	- nor_3T 40
	- or_3T 9
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s641_nem': 728536.000000
	- of which used for sequential elements: 340952.000000 (46.80%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s641_nem ===
	-
	- Number of wires: 210
	- Number of wire bits: 210
	- Number of public wires: 93
	- Number of public wire bits: 93
	- Number of ports: 60
	- Number of port bits: 60
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 174
	- $scopeinfo 19
	- D_FF 17
	- and_4T 40
	- and_not_4T 21
	- inv_3T 17
	- mux_4T 3
	- or_4T 34
	- or_not_4T 23
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s641_nem': 516520.000000
	- of which used for sequential elements: 340952.000000 (66.01%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 728536.000000
	-Area 4T: 516520.000000
	-Ratio 4T->3T: .70898349566802464119%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/s713.ratio b/ISCAS_but_no_mux4T/s713.ratio
	deleted file mode 100644
	index a00809d..0000000
	--- a/ISCAS_but_no_mux4T/s713.ratio
	+++ /dev/null
	@@ -1,70 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s713_nem ===
	-
	- Number of wires: 215
	- Number of wire bits: 215
	- Number of public wires: 93
	- Number of public wire bits: 93
	- Number of ports: 59
	- Number of port bits: 59
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 179
	- $scopeinfo 19
	- D_FF 17
	- and_3T 16
	- inv_3T 20
	- nand_3T 61
	- nor_3T 41
	- or_3T 5
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s713_nem': 735368.000000
	- of which used for sequential elements: 340952.000000 (46.36%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s713_nem ===
	-
	- Number of wires: 209
	- Number of wire bits: 209
	- Number of public wires: 93
	- Number of public wire bits: 93
	- Number of ports: 59
	- Number of port bits: 59
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 173
	- $scopeinfo 19
	- D_FF 17
	- and_4T 39
	- and_not_4T 20
	- inv_3T 16
	- mux_4T 3
	- or_4T 35
	- or_not_4T 24
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s713_nem': 515360.000000
	- of which used for sequential elements: 340952.000000 (66.16%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 735368.000000
	-Area 4T: 515360.000000
	-Ratio 4T->3T: .70081918168862392706%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_but_no_mux4T/s9234.ratio b/ISCAS_but_no_mux4T/s9234.ratio
	deleted file mode 100644
	index 724333c..0000000
	--- a/ISCAS_but_no_mux4T/s9234.ratio
	+++ /dev/null
	@@ -1,78 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s9234_nem ===
	-
	- Number of wires: 1058
	- Number of wire bits: 1058
	- Number of public wires: 355
	- Number of public wire bits: 355
	- Number of ports: 76
	- Number of port bits: 76
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1010
	- $scopeinfo 145
	- D_FF 135
	- and_3T 68
	- buf_3T 8
	- inv_3T 42
	- mux_3T 35
	- nand_3T 322
	- nor_3T 174
	- or_3T 37
	- xnor_3T 27
	- xor_3T 17
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s9234_nem': 5215368.000000
	- of which used for sequential elements: 2707560.000000 (51.92%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s9234_nem ===
	-
	- Number of wires: 1011
	- Number of wire bits: 1011
	- Number of public wires: 355
	- Number of public wire bits: 355
	- Number of ports: 76
	- Number of port bits: 76
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 963
	- $scopeinfo 145
	- D_FF 135
	- and_4T 258
	- and_not_4T 99
	- buf_3T 8
	- inv_3T 7
	- mux_4T 35
	- nand_4T 2
	- or_4T 166
	- or_not_4T 58
	- xnor_4T 32
	- xor_4T 18
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s9234_nem': 3654304.000000
	- of which used for sequential elements: 2707560.000000 (74.09%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 5215368.000000
	-Area 4T: 3654304.000000
	-Ratio 4T->3T: .70067999036693096249%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/c1355.ratio b/ISCAS_results/c1355.ratio
	deleted file mode 100644
	index 9d188d4..0000000
	--- a/ISCAS_results/c1355.ratio
	+++ /dev/null
	@@ -1,64 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c1355_nem ===
	-
	- Number of wires: 227
	- Number of wire bits: 227
	- Number of public wires: 73
	- Number of public wire bits: 73
	- Number of ports: 73
	- Number of port bits: 73
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 186
	- and_3T 2
	- inv_3T 5
	- nand_3T 41
	- nor_3T 30
	- or_3T 3
	- xnor_3T 77
	- xor_3T 28
	-
	- Chip area for module '\c1355_nem': 1048072.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c1355_nem ===
	-
	- Number of wires: 221
	- Number of wire bits: 221
	- Number of public wires: 73
	- Number of public wire bits: 73
	- Number of ports: 73
	- Number of port bits: 73
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 180
	- and_4T 49
	- and_not_4T 18
	- inv_3T 1
	- or_4T 7
	- xnor_4T 91
	- xor_4T 14
	-
	- Chip area for module '\c1355_nem': 353512.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 1048072.000000
	-Area 4T: 353512.000000
	-Ratio 4T->3T: .33729743758062423192%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/c17.ratio b/ISCAS_results/c17.ratio
	deleted file mode 100644
	index 8f5fb09..0000000
	--- a/ISCAS_results/c17.ratio
	+++ /dev/null
	@@ -1,55 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c17_nem ===
	-
	- Number of wires: 11
	- Number of wire bits: 11
	- Number of public wires: 7
	- Number of public wire bits: 7
	- Number of ports: 7
	- Number of port bits: 7
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 6
	- nand_3T 6
	-
	- Chip area for module '\c17_nem': 16992.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c17_nem ===
	-
	- Number of wires: 11
	- Number of wire bits: 11
	- Number of public wires: 7
	- Number of public wire bits: 7
	- Number of ports: 7
	- Number of port bits: 7
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 6
	- and_4T 2
	- and_not_4T 2
	- or_4T 2
	-
	- Chip area for module '\c17_nem': 7728.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 16992.000000
	-Area 4T: 7728.000000
	-Ratio 4T->3T: .45480225988700564971%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/c1908.ratio b/ISCAS_results/c1908.ratio
	deleted file mode 100644
	index 873a4b3..0000000
	--- a/ISCAS_results/c1908.ratio
	+++ /dev/null
	@@ -1,68 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c1908_nem ===
	-
	- Number of wires: 253
	- Number of wire bits: 253
	- Number of public wires: 58
	- Number of public wire bits: 58
	- Number of ports: 58
	- Number of port bits: 58
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 220
	- and_3T 12
	- inv_3T 9
	- mux_4T 2
	- nand_3T 58
	- nor_3T 54
	- or_3T 11
	- xnor_3T 58
	- xor_3T 16
	-
	- Chip area for module '\c1908_nem': 1003960.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c1908_nem ===
	-
	- Number of wires: 246
	- Number of wire bits: 246
	- Number of public wires: 58
	- Number of public wire bits: 58
	- Number of ports: 58
	- Number of port bits: 58
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 213
	- and_4T 48
	- and_not_4T 21
	- inv_3T 4
	- mux_4T 2
	- nor_3T 1
	- or_4T 39
	- or_not_4T 26
	- xnor_4T 56
	- xor_4T 16
	-
	- Chip area for module '\c1908_nem': 358896.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 1003960.000000
	-Area 4T: 358896.000000
	-Ratio 4T->3T: .35748037770429100760%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/c2670.ratio b/ISCAS_results/c2670.ratio
	deleted file mode 100644
	index 177a66e..0000000
	--- a/ISCAS_results/c2670.ratio
	+++ /dev/null
	@@ -1,68 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c2670_nem ===
	-
	- Number of wires: 692
	- Number of wire bits: 692
	- Number of public wires: 373
	- Number of public wire bits: 373
	- Number of ports: 373
	- Number of port bits: 373
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 369
	- and_3T 30
	- inv_3T 31
	- mux_4T 64
	- nand_3T 104
	- nor_3T 80
	- or_3T 16
	- xnor_3T 32
	- xor_3T 12
	-
	- Chip area for module '\c2670_nem': 1304104.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c2670_nem ===
	-
	- Number of wires: 680
	- Number of wire bits: 680
	- Number of public wires: 373
	- Number of public wire bits: 373
	- Number of ports: 373
	- Number of port bits: 373
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 357
	- and_4T 89
	- and_not_4T 21
	- inv_3T 28
	- mux_4T 65
	- nand_4T 1
	- or_4T 61
	- or_not_4T 44
	- xnor_4T 32
	- xor_4T 16
	-
	- Chip area for module '\c2670_nem': 513072.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 1304104.000000
	-Area 4T: 513072.000000
	-Ratio 4T->3T: .39342874494672204057%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/c3540.ratio b/ISCAS_results/c3540.ratio
	deleted file mode 100644
	index f84b4b0..0000000
	--- a/ISCAS_results/c3540.ratio
	+++ /dev/null
	@@ -1,67 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c3540_nem ===
	-
	- Number of wires: 855
	- Number of wire bits: 855
	- Number of public wires: 72
	- Number of public wire bits: 72
	- Number of ports: 72
	- Number of port bits: 72
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 805
	- and_3T 64
	- inv_3T 31
	- mux_4T 44
	- nand_3T 377
	- nor_3T 216
	- or_3T 33
	- xnor_3T 27
	- xor_3T 13
	-
	- Chip area for module '\c3540_nem': 2561848.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c3540_nem ===
	-
	- Number of wires: 830
	- Number of wire bits: 830
	- Number of public wires: 72
	- Number of public wire bits: 72
	- Number of ports: 72
	- Number of port bits: 72
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 780
	- and_4T 202
	- and_not_4T 148
	- inv_3T 17
	- mux_4T 46
	- or_4T 258
	- or_not_4T 62
	- xnor_4T 33
	- xor_4T 14
	-
	- Chip area for module '\c3540_nem': 1056984.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 2561848.000000
	-Area 4T: 1056984.000000
	-Ratio 4T->3T: .41258653909209289544%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/c432.ratio b/ISCAS_results/c432.ratio
	deleted file mode 100644
	index 71b1e2b..0000000
	--- a/ISCAS_results/c432.ratio
	+++ /dev/null
	@@ -1,61 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c432_nem ===
	-
	- Number of wires: 171
	- Number of wire bits: 171
	- Number of public wires: 43
	- Number of public wire bits: 43
	- Number of ports: 43
	- Number of port bits: 43
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 135
	- and_3T 8
	- inv_3T 12
	- nand_3T 40
	- nor_3T 72
	- or_3T 3
	-
	- Chip area for module '\c432_nem': 374256.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c432_nem ===
	-
	- Number of wires: 160
	- Number of wire bits: 160
	- Number of public wires: 43
	- Number of public wire bits: 43
	- Number of ports: 43
	- Number of port bits: 43
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 124
	- and_4T 31
	- and_not_4T 30
	- inv_3T 2
	- or_4T 44
	- or_not_4T 17
	-
	- Chip area for module '\c432_nem': 159456.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 374256.000000
	-Area 4T: 159456.000000
	-Ratio 4T->3T: .42606130563037065538%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/c499.ratio b/ISCAS_results/c499.ratio
	deleted file mode 100644
	index ca68f4a..0000000
	--- a/ISCAS_results/c499.ratio
	+++ /dev/null
	@@ -1,65 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c499_nem ===
	-
	- Number of wires: 225
	- Number of wire bits: 225
	- Number of public wires: 73
	- Number of public wire bits: 73
	- Number of ports: 73
	- Number of port bits: 73
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 184
	- and_3T 1
	- inv_3T 4
	- nand_3T 54
	- nor_3T 14
	- or_3T 6
	- xnor_3T 99
	- xor_3T 6
	-
	- Chip area for module '\c499_nem': 1046360.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c499_nem ===
	-
	- Number of wires: 220
	- Number of wire bits: 220
	- Number of public wires: 73
	- Number of public wire bits: 73
	- Number of ports: 73
	- Number of port bits: 73
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 179
	- and_4T 38
	- and_not_4T 9
	- inv_3T 1
	- or_4T 9
	- or_not_4T 17
	- xnor_4T 79
	- xor_4T 26
	-
	- Chip area for module '\c499_nem': 352224.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 1046360.000000
	-Area 4T: 352224.000000
	-Ratio 4T->3T: .33661837226193661837%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/c5315.ratio b/ISCAS_results/c5315.ratio
	deleted file mode 100644
	index d1ec24f..0000000
	--- a/ISCAS_results/c5315.ratio
	+++ /dev/null
	@@ -1,69 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c5315_nem ===
	-
	- Number of wires: 1181
	- Number of wire bits: 1181
	- Number of public wires: 301
	- Number of public wire bits: 301
	- Number of ports: 301
	- Number of port bits: 301
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 986
	- and_3T 73
	- inv_3T 79
	- mux_4T 140
	- nand_3T 329
	- nor_3T 242
	- or_3T 31
	- xnor_3T 73
	- xor_3T 19
	-
	- Chip area for module '\c5315_nem': 3322688.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c5315_nem ===
	-
	- Number of wires: 1158
	- Number of wire bits: 1158
	- Number of public wires: 301
	- Number of public wire bits: 301
	- Number of ports: 301
	- Number of port bits: 301
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 963
	- and_4T 207
	- and_not_4T 86
	- inv_3T 69
	- mux_4T 139
	- nand_4T 5
	- nor_3T 2
	- or_4T 244
	- or_not_4T 106
	- xnor_4T 75
	- xor_4T 30
	-
	- Chip area for module '\c5315_nem': 1362200.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 3322688.000000
	-Area 4T: 1362200.000000
	-Ratio 4T->3T: .40996927788585627058%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/c6288.ratio b/ISCAS_results/c6288.ratio
	deleted file mode 100644
	index cec050b..0000000
	--- a/ISCAS_results/c6288.ratio
	+++ /dev/null
	@@ -1,67 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c6288_nem ===
	-
	- Number of wires: 1695
	- Number of wire bits: 1695
	- Number of public wires: 64
	- Number of public wire bits: 64
	- Number of ports: 64
	- Number of port bits: 64
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1663
	- and_3T 235
	- inv_3T 18
	- mux_4T 1
	- nand_3T 315
	- nor_3T 681
	- or_3T 190
	- xnor_3T 62
	- xor_3T 161
	-
	- Chip area for module '\c6288_nem': 6259976.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c6288_nem ===
	-
	- Number of wires: 1439
	- Number of wire bits: 1439
	- Number of public wires: 64
	- Number of public wire bits: 64
	- Number of ports: 64
	- Number of port bits: 64
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1407
	- and_4T 494
	- and_not_4T 17
	- mux_4T 1
	- nand_4T 154
	- or_4T 223
	- or_not_4T 57
	- xnor_4T 97
	- xor_4T 364
	-
	- Chip area for module '\c6288_nem': 2525616.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 6259976.000000
	-Area 4T: 2525616.000000
	-Ratio 4T->3T: .40345458193449942939%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/c7552.ratio b/ISCAS_results/c7552.ratio
	deleted file mode 100644
	index b9c27dd..0000000
	--- a/ISCAS_results/c7552.ratio
	+++ /dev/null
	@@ -1,68 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c7552_nem ===
	-
	- Number of wires: 1217
	- Number of wire bits: 1217
	- Number of public wires: 315
	- Number of public wire bits: 315
	- Number of ports: 315
	- Number of port bits: 315
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 960
	- and_3T 63
	- inv_3T 78
	- mux_4T 126
	- nand_3T 191
	- nor_3T 268
	- or_3T 59
	- xnor_3T 140
	- xor_3T 35
	-
	- Chip area for module '\c7552_nem': 3676664.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c7552_nem ===
	-
	- Number of wires: 1168
	- Number of wire bits: 1168
	- Number of public wires: 315
	- Number of public wire bits: 315
	- Number of ports: 315
	- Number of port bits: 315
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 911
	- and_4T 165
	- and_not_4T 102
	- inv_3T 48
	- mux_4T 127
	- nand_4T 5
	- or_4T 151
	- or_not_4T 100
	- xnor_4T 165
	- xor_4T 48
	-
	- Chip area for module '\c7552_nem': 1420104.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 3676664.000000
	-Area 4T: 1420104.000000
	-Ratio 4T->3T: .38624796826688541569%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/c880.ratio b/ISCAS_results/c880.ratio
	deleted file mode 100644
	index ae1dd95..0000000
	--- a/ISCAS_results/c880.ratio
	+++ /dev/null
	@@ -1,66 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== c880_nem ===
	-
	- Number of wires: 328
	- Number of wire bits: 328
	- Number of public wires: 86
	- Number of public wire bits: 86
	- Number of ports: 86
	- Number of port bits: 86
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 268
	- and_3T 30
	- inv_3T 14
	- nand_3T 119
	- nor_3T 77
	- or_3T 2
	- xnor_3T 13
	- xor_3T 13
	-
	- Chip area for module '\c880_nem': 900000.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== c880_nem ===
	-
	- Number of wires: 316
	- Number of wire bits: 316
	- Number of public wires: 86
	- Number of public wire bits: 86
	- Number of ports: 86
	- Number of port bits: 86
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 256
	- and_4T 120
	- and_not_4T 13
	- inv_3T 2
	- nand_4T 1
	- or_4T 82
	- or_not_4T 5
	- xnor_4T 12
	- xor_4T 21
	-
	- Chip area for module '\c880_nem': 368912.000000
	- of which used for sequential elements: 0.000000 (0.00%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 900000.000000
	-Area 4T: 368912.000000
	-Ratio 4T->3T: .40990222222222222222%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/output_report.csv b/ISCAS_results/output_report.csv
	deleted file mode 100644
	index 7dfa144..0000000
	--- a/ISCAS_results/output_report.csv
	+++ /dev/null
	@@ -1,27 +0,0 @@
	-Module,3T,4T,Ratio
	-c1355_nem,1048072.000000,353512.000000,.33729743758062423192,,
	-c17_nem,16992.000000,7728.000000,.45480225988700564971,,
	-c1908_nem,1003960.000000,358896.000000,.35748037770429100760,,
	-c2670_nem,1304104.000000,513072.000000,.39342874494672204057,,
	-c3540_nem,2561848.000000,1056984.000000,.41258653909209289544,,
	-c432_nem,374256.000000,159456.000000,.42606130563037065538,,
	-c499_nem,1046360.000000,352224.000000,.33661837226193661837,,
	-c5315_nem,3322688.000000,1362200.000000,.40996927788585627058,,
	-c6288_nem,6259976.000000,2525616.000000,.40345458193449942939,,
	-c7552_nem,3676664.000000,1420104.000000,.38624796826688541569,,
	-c880_nem,900000.000000,368912.000000,.40990222222222222222,,
	-s1238_nem,1766776.000000,965480.000000,.54646429428518386031,,
	-s13207_nem,15260912.000000,12011112.000000,.78705073458257278464,,
	-s1423_nem,2732480.000000,1978632.000000,.72411582152476870827,,
	-s1488_nem,1909368.000000,872016.000000,.45670399839109066455,,
	-s15850_nem,17354904.000000,13091264.000000,.75432650045197599479,,
	-s27_nem,84552.000000,71504.000000,.84568076449995269183,,
	-s35932_nem,58162608.000000,42941576.000000,.73830210639797995303,,
	-s382_nem,770256.000000,560032.000000,.72707255769510396543,,
	-s38417_nem,51028280.000000,38505624.000000,.75459380563091681710,,
	-s38584_nem,55924648.000000,40057032.000000,.71626793252234685500,,
	-s420_nem,659720.000000,457688.000000,.69376098951070150973,,
	-s5378_nem,6175224.000000,4483744.000000,.72608604967204428535,,
	-s641_nem,721960.000000,516520.000000,.71544129868690786193,,
	-s713_nem,728792.000000,515360.000000,.70714277873522212098,,
	-s9234_nem,5044400.000000,3654304.000000,.72442788042185393703,,
	diff --git a/ISCAS_results/s1238.ratio b/ISCAS_results/s1238.ratio
	deleted file mode 100644
	index 5330b83..0000000
	--- a/ISCAS_results/s1238.ratio
	+++ /dev/null
	@@ -1,74 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s1238_nem ===
	-
	- Number of wires: 537
	- Number of wire bits: 537
	- Number of public wires: 71
	- Number of public wire bits: 71
	- Number of ports: 29
	- Number of port bits: 29
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 522
	- $scopeinfo 18
	- D_FF 18
	- and_3T 28
	- inv_3T 27
	- mux_4T 15
	- nand_3T 191
	- nor_3T 194
	- or_3T 31
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s1238_nem': 1766776.000000
	- of which used for sequential elements: 361008.000000 (20.43%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s1238_nem ===
	-
	- Number of wires: 517
	- Number of wire bits: 517
	- Number of public wires: 71
	- Number of public wire bits: 71
	- Number of ports: 29
	- Number of port bits: 29
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 502
	- $scopeinfo 18
	- D_FF 18
	- and_4T 169
	- and_not_4T 86
	- inv_3T 12
	- mux_4T 15
	- nand_4T 1
	- or_4T 120
	- or_not_4T 59
	- xnor_4T 2
	- xor_4T 2
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s1238_nem': 965480.000000
	- of which used for sequential elements: 361008.000000 (37.39%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 1766776.000000
	-Area 4T: 965480.000000
	-Ratio 4T->3T: .54646429428518386031%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/s13207.ratio b/ISCAS_results/s13207.ratio
	deleted file mode 100644
	index df6e277..0000000
	--- a/ISCAS_results/s13207.ratio
	+++ /dev/null
	@@ -1,79 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s13207_nem ===
	-
	- Number of wires: 2837
	- Number of wire bits: 2837
	- Number of public wires: 1126
	- Number of public wire bits: 1126
	- Number of ports: 215
	- Number of port bits: 215
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 2864
	- $scopeinfo 627
	- D_FF 484
	- and_3T 145
	- buf_3T 1
	- inv_3T 113
	- mux_4T 143
	- nand_3T 706
	- nor_3T 465
	- or_3T 95
	- xnor_3T 47
	- xor_3T 38
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s13207_nem': 15260912.000000
	- of which used for sequential elements: 9707104.000000 (63.61%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s13207_nem ===
	-
	- Number of wires: 2782
	- Number of wire bits: 2782
	- Number of public wires: 1126
	- Number of public wire bits: 1126
	- Number of ports: 215
	- Number of port bits: 215
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 2809
	- $scopeinfo 627
	- D_FF 484
	- and_4T 666
	- and_not_4T 120
	- buf_3T 1
	- inv_3T 39
	- mux_4T 143
	- nand_4T 5
	- nor_3T 1
	- or_4T 526
	- or_not_4T 99
	- xnor_4T 47
	- xor_4T 51
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s13207_nem': 12011112.000000
	- of which used for sequential elements: 9707104.000000 (80.82%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 15260912.000000
	-Area 4T: 12011112.000000
	-Ratio 4T->3T: .78705073458257278464%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/s1423.ratio b/ISCAS_results/s1423.ratio
	deleted file mode 100644
	index e7fc842..0000000
	--- a/ISCAS_results/s1423.ratio
	+++ /dev/null
	@@ -1,76 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s1423_nem ===
	-
	- Number of wires: 571
	- Number of wire bits: 571
	- Number of public wires: 186
	- Number of public wire bits: 186
	- Number of ports: 23
	- Number of port bits: 23
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 553
	- $scopeinfo 74
	- D_FF 74
	- and_3T 43
	- inv_3T 37
	- mux_4T 27
	- nand_3T 87
	- nor_3T 174
	- or_3T 22
	- xnor_3T 12
	- xor_3T 3
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s1423_nem': 2732480.000000
	- of which used for sequential elements: 1484144.000000 (54.31%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s1423_nem ===
	-
	- Number of wires: 527
	- Number of wire bits: 527
	- Number of public wires: 186
	- Number of public wire bits: 186
	- Number of ports: 23
	- Number of port bits: 23
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 509
	- $scopeinfo 74
	- D_FF 74
	- and_4T 141
	- and_not_4T 54
	- inv_3T 5
	- mux_4T 27
	- nand_4T 1
	- or_4T 85
	- or_not_4T 23
	- xnor_4T 13
	- xor_4T 12
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s1423_nem': 1978632.000000
	- of which used for sequential elements: 1484144.000000 (75.01%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 2732480.000000
	-Area 4T: 1978632.000000
	-Ratio 4T->3T: .72411582152476870827%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/s1488.ratio b/ISCAS_results/s1488.ratio
	deleted file mode 100644
	index 98f1e01..0000000
	--- a/ISCAS_results/s1488.ratio
	+++ /dev/null
	@@ -1,72 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s1488_nem ===
	-
	- Number of wires: 642
	- Number of wire bits: 642
	- Number of public wires: 46
	- Number of public wire bits: 46
	- Number of ports: 28
	- Number of port bits: 28
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 633
	- $scopeinfo 6
	- D_FF 6
	- and_3T 55
	- inv_3T 30
	- mux_4T 5
	- nand_3T 303
	- nor_3T 212
	- or_3T 16
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s1488_nem': 1909368.000000
	- of which used for sequential elements: 120336.000000 (6.30%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s1488_nem ===
	-
	- Number of wires: 604
	- Number of wire bits: 604
	- Number of public wires: 46
	- Number of public wire bits: 46
	- Number of ports: 28
	- Number of port bits: 28
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 595
	- $scopeinfo 6
	- D_FF 6
	- and_4T 225
	- and_not_4T 100
	- inv_3T 3
	- mux_4T 3
	- or_4T 187
	- or_not_4T 64
	- xor_4T 1
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s1488_nem': 872016.000000
	- of which used for sequential elements: 120336.000000 (13.80%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 1909368.000000
	-Area 4T: 872016.000000
	-Ratio 4T->3T: .45670399839109066455%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/s15850.ratio b/ISCAS_results/s15850.ratio
	deleted file mode 100644
	index 8c0fef4..0000000
	--- a/ISCAS_results/s15850.ratio
	+++ /dev/null
	@@ -1,78 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s15850_nem ===
	-
	- Number of wires: 3349
	- Number of wire bits: 3349
	- Number of public wires: 1306
	- Number of public wire bits: 1306
	- Number of ports: 228
	- Number of port bits: 228
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 3202
	- $scopeinfo 527
	- D_FF 515
	- and_3T 196
	- buf_3T 11
	- inv_3T 152
	- mux_4T 274
	- nand_3T 747
	- nor_3T 548
	- or_3T 97
	- xnor_3T 96
	- xor_3T 39
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s15850_nem': 17354904.000000
	- of which used for sequential elements: 10328840.000000 (59.52%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s15850_nem ===
	-
	- Number of wires: 3196
	- Number of wire bits: 3196
	- Number of public wires: 1306
	- Number of public wire bits: 1306
	- Number of ports: 228
	- Number of port bits: 228
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 3049
	- $scopeinfo 527
	- D_FF 515
	- and_4T 693
	- and_not_4T 229
	- buf_3T 11
	- inv_3T 28
	- mux_4T 275
	- nand_4T 2
	- or_4T 542
	- or_not_4T 82
	- xnor_4T 72
	- xor_4T 73
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s15850_nem': 13091264.000000
	- of which used for sequential elements: 10328840.000000 (78.90%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 17354904.000000
	-Area 4T: 13091264.000000
	-Ratio 4T->3T: .75432650045197599479%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/s27.ratio b/ISCAS_results/s27.ratio
	deleted file mode 100644
	index 7aeff4e..0000000
	--- a/ISCAS_results/s27.ratio
	+++ /dev/null
	@@ -1,68 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s27_nem ===
	-
	- Number of wires: 21
	- Number of wire bits: 21
	- Number of public wires: 12
	- Number of public wire bits: 12
	- Number of ports: 6
	- Number of port bits: 6
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 16
	- $scopeinfo 3
	- D_FF 3
	- and_3T 1
	- inv_3T 3
	- nand_3T 4
	- nor_3T 2
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s27_nem': 84552.000000
	- of which used for sequential elements: 60168.000000 (71.16%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s27_nem ===
	-
	- Number of wires: 20
	- Number of wire bits: 20
	- Number of public wires: 12
	- Number of public wire bits: 12
	- Number of ports: 6
	- Number of port bits: 6
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 15
	- $scopeinfo 3
	- D_FF 3
	- and_4T 2
	- and_not_4T 2
	- inv_3T 2
	- or_4T 2
	- or_not_4T 1
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s27_nem': 71504.000000
	- of which used for sequential elements: 60168.000000 (84.15%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 84552.000000
	-Area 4T: 71504.000000
	-Ratio 4T->3T: .84568076449995269183%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/s35932.ratio b/ISCAS_results/s35932.ratio
	deleted file mode 100644
	index ff050e5..0000000
	--- a/ISCAS_results/s35932.ratio
	+++ /dev/null
	@@ -1,74 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s35932_nem ===
	-
	- Number of wires: 9190
	- Number of wire bits: 9190
	- Number of public wires: 3821
	- Number of public wire bits: 3821
	- Number of ports: 356
	- Number of port bits: 356
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 9154
	- $scopeinfo 1728
	- D_FF 1728
	- and_3T 1701
	- inv_3T 1
	- mux_4T 160
	- nand_3T 1638
	- nor_3T 1110
	- xnor_3T 624
	- xor_3T 464
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s35932_nem': 58162608.000000
	- of which used for sequential elements: 34656768.000000 (59.59%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s35932_nem ===
	-
	- Number of wires: 8853
	- Number of wire bits: 8853
	- Number of public wires: 3821
	- Number of public wire bits: 3821
	- Number of ports: 356
	- Number of port bits: 356
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 8817
	- $scopeinfo 1728
	- D_FF 1728
	- and_4T 2251
	- and_not_4T 155
	- inv_3T 240
	- mux_4T 384
	- or_4T 507
	- or_not_4T 608
	- xnor_4T 768
	- xor_4T 448
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s35932_nem': 42941576.000000
	- of which used for sequential elements: 34656768.000000 (80.71%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 58162608.000000
	-Area 4T: 42941576.000000
	-Ratio 4T->3T: .73830210639797995303%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/s382.ratio b/ISCAS_results/s382.ratio
	deleted file mode 100644
	index 24d0ffe..0000000
	--- a/ISCAS_results/s382.ratio
	+++ /dev/null
	@@ -1,75 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s382_nem ===
	-
	- Number of wires: 152
	- Number of wire bits: 152
	- Number of public wires: 63
	- Number of public wire bits: 63
	- Number of ports: 10
	- Number of port bits: 10
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 148
	- $scopeinfo 21
	- D_FF 21
	- and_3T 9
	- inv_3T 8
	- mux_4T 3
	- nand_3T 17
	- nor_3T 48
	- or_3T 14
	- xnor_3T 2
	- xor_3T 5
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s382_nem': 770256.000000
	- of which used for sequential elements: 421176.000000 (54.68%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s382_nem ===
	-
	- Number of wires: 147
	- Number of wire bits: 147
	- Number of public wires: 63
	- Number of public wire bits: 63
	- Number of ports: 10
	- Number of port bits: 10
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 143
	- $scopeinfo 21
	- D_FF 21
	- and_4T 29
	- and_not_4T 19
	- inv_3T 4
	- mux_4T 3
	- or_4T 28
	- or_not_4T 10
	- xnor_4T 5
	- xor_4T 3
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s382_nem': 560032.000000
	- of which used for sequential elements: 421176.000000 (75.21%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 770256.000000
	-Area 4T: 560032.000000
	-Ratio 4T->3T: .72707255769510396543%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/s38417.ratio b/ISCAS_results/s38417.ratio
	deleted file mode 100644
	index 9776763..0000000
	--- a/ISCAS_results/s38417.ratio
	+++ /dev/null
	@@ -1,76 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s38417_nem ===
	-
	- Number of wires: 9972
	- Number of wire bits: 9972
	- Number of public wires: 3862
	- Number of public wire bits: 3862
	- Number of ports: 135
	- Number of port bits: 135
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 9995
	- $scopeinfo 1564
	- D_FF 1463
	- and_3T 993
	- inv_3T 637
	- mux_4T 594
	- nand_3T 3046
	- nor_3T 1251
	- or_3T 172
	- xnor_3T 173
	- xor_3T 102
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s38417_nem': 51028280.000000
	- of which used for sequential elements: 29341928.000000 (57.50%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s38417_nem ===
	-
	- Number of wires: 9824
	- Number of wire bits: 9824
	- Number of public wires: 3862
	- Number of public wire bits: 3862
	- Number of ports: 135
	- Number of port bits: 135
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 9847
	- $scopeinfo 1564
	- D_FF 1463
	- and_4T 1982
	- and_not_4T 913
	- inv_3T 533
	- mux_4T 600
	- nand_4T 103
	- or_4T 1451
	- or_not_4T 955
	- xnor_4T 148
	- xor_4T 135
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s38417_nem': 38505624.000000
	- of which used for sequential elements: 29341928.000000 (76.20%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 51028280.000000
	-Area 4T: 38505624.000000
	-Ratio 4T->3T: .75459380563091681710%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/s38584.ratio b/ISCAS_results/s38584.ratio
	deleted file mode 100644
	index 33958fa..0000000
	--- a/ISCAS_results/s38584.ratio
	+++ /dev/null
	@@ -1,79 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s38584_nem ===
	-
	- Number of wires: 12122
	- Number of wire bits: 12122
	- Number of public wires: 3793
	- Number of public wire bits: 3793
	- Number of ports: 343
	- Number of port bits: 343
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 11997
	- $scopeinfo 1426
	- D_FF 1423
	- and_3T 461
	- buf_3T 7
	- inv_3T 437
	- mux_4T 640
	- nand_3T 4235
	- nor_3T 2742
	- or_3T 470
	- xnor_3T 56
	- xor_3T 100
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s38584_nem': 55924648.000000
	- of which used for sequential elements: 28539688.000000 (51.03%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s38584_nem ===
	-
	- Number of wires: 11740
	- Number of wire bits: 11740
	- Number of public wires: 3793
	- Number of public wire bits: 3793
	- Number of ports: 343
	- Number of port bits: 343
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 11615
	- $scopeinfo 1426
	- D_FF 1423
	- and_4T 2838
	- and_not_4T 1473
	- buf_3T 7
	- inv_3T 78
	- mux_4T 635
	- nand_4T 32
	- nor_3T 4
	- or_4T 2537
	- or_not_4T 1001
	- xnor_4T 51
	- xor_4T 110
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s38584_nem': 40057032.000000
	- of which used for sequential elements: 28539688.000000 (71.25%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 55924648.000000
	-Area 4T: 40057032.000000
	-Ratio 4T->3T: .71626793252234685500%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/s420.ratio b/ISCAS_results/s420.ratio
	deleted file mode 100644
	index 6a09fa6..0000000
	--- a/ISCAS_results/s420.ratio
	+++ /dev/null
	@@ -1,74 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s420_nem ===
	-
	- Number of wires: 169
	- Number of wire bits: 169
	- Number of public wires: 68
	- Number of public wire bits: 68
	- Number of ports: 20
	- Number of port bits: 20
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 150
	- $scopeinfo 16
	- D_FF 16
	- and_3T 8
	- inv_3T 19
	- mux_4T 13
	- nand_3T 35
	- nor_3T 36
	- or_3T 4
	- xnor_3T 2
	- xor_3T 1
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s420_nem': 659720.000000
	- of which used for sequential elements: 320896.000000 (48.64%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s420_nem ===
	-
	- Number of wires: 155
	- Number of wire bits: 155
	- Number of public wires: 68
	- Number of public wire bits: 68
	- Number of ports: 20
	- Number of port bits: 20
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 136
	- $scopeinfo 16
	- D_FF 16
	- and_4T 21
	- and_not_4T 27
	- inv_3T 5
	- mux_4T 13
	- or_4T 31
	- or_not_4T 4
	- xnor_4T 3
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s420_nem': 457688.000000
	- of which used for sequential elements: 320896.000000 (70.11%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 659720.000000
	-Area 4T: 457688.000000
	-Ratio 4T->3T: .69376098951070150973%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/s5378.ratio b/ISCAS_results/s5378.ratio
	deleted file mode 100644
	index a5e7ef5..0000000
	--- a/ISCAS_results/s5378.ratio
	+++ /dev/null
	@@ -1,76 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s5378_nem ===
	-
	- Number of wires: 1370
	- Number of wire bits: 1370
	- Number of public wires: 489
	- Number of public wire bits: 489
	- Number of ports: 85
	- Number of port bits: 85
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1347
	- $scopeinfo 179
	- D_FF 160
	- and_3T 53
	- inv_3T 72
	- mux_4T 27
	- nand_3T 296
	- nor_3T 492
	- or_3T 47
	- xnor_3T 17
	- xor_3T 4
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s5378_nem': 6175224.000000
	- of which used for sequential elements: 3208960.000000 (51.97%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s5378_nem ===
	-
	- Number of wires: 1326
	- Number of wire bits: 1326
	- Number of public wires: 489
	- Number of public wire bits: 489
	- Number of ports: 85
	- Number of port bits: 85
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1303
	- $scopeinfo 179
	- D_FF 160
	- and_4T 242
	- and_not_4T 123
	- inv_3T 31
	- mux_4T 27
	- nand_4T 10
	- or_4T 407
	- or_not_4T 102
	- xnor_4T 15
	- xor_4T 7
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s5378_nem': 4483744.000000
	- of which used for sequential elements: 3208960.000000 (71.57%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 6175224.000000
	-Area 4T: 4483744.000000
	-Ratio 4T->3T: .72608604967204428535%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/s641.ratio b/ISCAS_results/s641.ratio
	deleted file mode 100644
	index c5e8fcc..0000000
	--- a/ISCAS_results/s641.ratio
	+++ /dev/null
	@@ -1,71 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s641_nem ===
	-
	- Number of wires: 213
	- Number of wire bits: 213
	- Number of public wires: 93
	- Number of public wire bits: 93
	- Number of ports: 60
	- Number of port bits: 60
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 177
	- $scopeinfo 19
	- D_FF 17
	- and_3T 6
	- inv_3T 22
	- mux_4T 3
	- nand_3T 61
	- nor_3T 40
	- or_3T 9
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s641_nem': 721960.000000
	- of which used for sequential elements: 340952.000000 (47.23%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s641_nem ===
	-
	- Number of wires: 210
	- Number of wire bits: 210
	- Number of public wires: 93
	- Number of public wire bits: 93
	- Number of ports: 60
	- Number of port bits: 60
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 174
	- $scopeinfo 19
	- D_FF 17
	- and_4T 40
	- and_not_4T 21
	- inv_3T 17
	- mux_4T 3
	- or_4T 34
	- or_not_4T 23
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s641_nem': 516520.000000
	- of which used for sequential elements: 340952.000000 (66.01%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 721960.000000
	-Area 4T: 516520.000000
	-Ratio 4T->3T: .71544129868690786193%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/s713.ratio b/ISCAS_results/s713.ratio
	deleted file mode 100644
	index b6b9734..0000000
	--- a/ISCAS_results/s713.ratio
	+++ /dev/null
	@@ -1,71 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s713_nem ===
	-
	- Number of wires: 212
	- Number of wire bits: 212
	- Number of public wires: 93
	- Number of public wire bits: 93
	- Number of ports: 59
	- Number of port bits: 59
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 176
	- $scopeinfo 19
	- D_FF 17
	- and_3T 16
	- inv_3T 20
	- mux_4T 3
	- nand_3T 55
	- nor_3T 41
	- or_3T 5
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s713_nem': 728792.000000
	- of which used for sequential elements: 340952.000000 (46.78%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s713_nem ===
	-
	- Number of wires: 209
	- Number of wire bits: 209
	- Number of public wires: 93
	- Number of public wire bits: 93
	- Number of ports: 59
	- Number of port bits: 59
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 173
	- $scopeinfo 19
	- D_FF 17
	- and_4T 39
	- and_not_4T 20
	- inv_3T 16
	- mux_4T 3
	- or_4T 35
	- or_not_4T 24
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s713_nem': 515360.000000
	- of which used for sequential elements: 340952.000000 (66.16%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 728792.000000
	-Area 4T: 515360.000000
	-Ratio 4T->3T: .70714277873522212098%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/ISCAS_results/s9234.ratio b/ISCAS_results/s9234.ratio
	deleted file mode 100644
	index bea34da..0000000
	--- a/ISCAS_results/s9234.ratio
	+++ /dev/null
	@@ -1,78 +0,0 @@
	-------------- normal 3T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib
	-
	-14. Printing statistics.
	-
	-=== s9234_nem ===
	-
	- Number of wires: 1052
	- Number of wire bits: 1052
	- Number of public wires: 355
	- Number of public wire bits: 355
	- Number of ports: 76
	- Number of port bits: 76
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 1004
	- $scopeinfo 145
	- D_FF 135
	- and_3T 67
	- buf_3T 8
	- inv_3T 40
	- mux_4T 35
	- nand_3T 321
	- nor_3T 170
	- or_3T 39
	- xnor_3T 27
	- xor_3T 17
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s9234_nem': 5044400.000000
	- of which used for sequential elements: 2707560.000000 (53.67%)
	-
	-------------- 4T ---------------
	-
	-yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib
	-
	-14. Printing statistics.
	-
	-=== s9234_nem ===
	-
	- Number of wires: 1011
	- Number of wire bits: 1011
	- Number of public wires: 355
	- Number of public wire bits: 355
	- Number of ports: 76
	- Number of port bits: 76
	- Number of memories: 0
	- Number of memory bits: 0
	- Number of processes: 0
	- Number of cells: 963
	- $scopeinfo 145
	- D_FF 135
	- and_4T 258
	- and_not_4T 99
	- buf_3T 8
	- inv_3T 7
	- mux_4T 35
	- nand_4T 2
	- or_4T 166
	- or_not_4T 58
	- xnor_4T 32
	- xor_4T 18
	-
	- Area for cell type $scopeinfo is unknown!
	-
	- Chip area for module '\s9234_nem': 3654304.000000
	- of which used for sequential elements: 2707560.000000 (74.09%)
	-
	-------------- Muxig ---------------
	-------------- Stats ---------------
	-Area 3T: 5044400.000000
	-Area 4T: 3654304.000000
	-Ratio 4T->3T: .72442788042185393703%
	-Area MUX:
	-Ratio MUX->3T: %
	diff --git a/README.md b/README.md
	index dc7b17f..eda5b8a 100644
	--- a/README.md
	+++ b/README.md
	@@ -1,103 +1,106 @@
	# 1. NEM synthesis

	This utility was written to use yosys to synthesize from verilog to a netlist existing out of all standard cells available in the current library of NEM cells. It only uses the freely available yosys oss suite. No license required

	# 2. data structure

	The application is ordered as follows:

	```
	\bruteforce_approach\: contains all the c script's and a python script to run bruteforce approach on very small functions
	\sources\ : All the verilog files for synthesis have to be stored here
	\temp\ : Contains all the output files after synthesis or intermediate yosys / graphviz dots files.
	+\output\ :Contains all the reports and summary outputs of test either performed with the interactive or bulk tool.
	+\mockturtle_binaries\ : this contains both the source and binary code that performs the MuxIG or MIG mapping.
	+\nem_liberty\ : Contains the liberty files used for mapping purposes.
	\yosys\ : Script that are executed for synthesis, visual, and sat testing.
	-\nem_basic_yosys.lib : This is the file of all the standard cells used in nem
	-\nem_basic_yosys_extended.lib : this is the additional cells added based on some new concepts
	```

	-As a user put the desired source files in .\sources\ and had to the next sessions
	+As a user put the desired source files in .\sources\ and follow the instructions to synthesize them to designs.
	+
	# 3. How to run
	+Download the current oss-suite at [this link](https://github.com/YosysHQ/oss-cad-suite-build) and extract it to a working directory.

	-Pull the repository to your local working directory.
	+Pull the repository to your local working directory. Keep oss-suite and this tool seperate.

	run:

	```bash
	source <oss-suite-location>/enviroment
	./run.sh
	```

	-and enter the file you want to use. Auto-complete is aviable, an example would be `sources/test_set/adder2.v`. Then enter the main module name. Just press enter if it is the same as the file name, (in the example `adder2`).
	+and enter the file you want to use. Auto-complete is available. An example would be `sources/test_set/adder2.v`, or `sources/ISCA85/c17.v` . Then enter the main module name. Just press enter if it is the same as the file name, (in the example `adder2`, or `c17`).

	You will be presented with the following options:

	```bash
	--------------------------------------------------------------
	Current file: sources/test_set/adder2.v with module: adder2
	Please select your options (you can choose multiple options):

	-1) Synthesize to NEM technology
	-2) Print initial design
	-3) Print out NEM optimized design
	-4) Perform SAT comparison
	-5) Export FSM as KISS2 format
	-6) Start shell with modules
	-7) Switch from normal 3T gate library to new 4T
	-8) Run test
	-9) export truth table and MUXIG run
	-10) export truth table and MIG run
	+1) Synthesize to NEM technology with normal Yosys AIG flow
	+2) Synthesize to NEM and perform MUXIG optimisaiton run
	+3) Synthesize to NEM and perform MIG optimisation run
	+4) Print initial design
	+5) Print out NEM optimized design
	+6) Perform SAT comparison
	+7) Export FSM as KISS2 format
	+8) Start shell with modules
	+9) Switch from normal 3T gate library to new 4T
	+10) Run series of test and create comparison report
	11) Select a new Verilog file
	-0) Exit the program
	+12) Exit the program
	--------------------------------------------------------------
	Enter your choices (e.g., 1 2 3, or 0 to finish):
	```

	1: As the text explains option 1 will run the synthesis script under `\yosys\` and will output the file as `_nem.v` extension in the `\temp\` folder. Next to that it will output statistics in the `.stat` file under `\temp\`.
	-2: Shows the abstract design before any syntehsis is done
	-3: Shows the final synthesized solution
	-4: Checks if the original verilog file matches the output of the final synthesised solution.
	-5: search for fsm model and view it
	-6: Compile plugins and start a shell to run them
	-7: Switch to extended liberty file with pass through muxiplexers
	-8: run synthesis and visual for both liberty files
	-9: pass the circuit to mockturtle to process it into MuxIG graph
	-10: pass the circuit to mockturtle to process it into MIG graph
	+2: pass the circuit to mockturtle to process it into MuxIG graph
	+3: pass the circuit to mockturtle to process it into MIG graph
	+4: Shows the abstract design before any syntehsis is done
	+5: Shows the final synthesized solution
	+6: Checks if the original verilog file matches the output of the final synthesised solution.
	+7: search for fsm model and view it
	+8: Compile plugins in the `\plugins\` directory and start a shell to run them on the current design
	+9: Switch to extended liberty file with pass through muxiplexers as internal cells which abc can map too.
	+10: Runs the normal test and the MuxIG synthesise. Next to that it tries the normal ABC synthesis on a liberty file which contains an optimal view of the PTL MuxIG implementaitons as normal primitive cells
	11: switch to different verilog file

	# 4. CLI

	You can also call the `./run.sh` with some arguments to work as a in-line tool if you want to automate stuff. The options are:

	-d [DIRECTORY] synthesise all the files in the directory
	--f [FILE_PATH] syntehsise specific path
	--m [MODULE_NAME] When -f argument used
	--v when present will also visuale the file.
	--x Switch liberty file to extended version
	+-f [FILE_PATH] synthesise specific path
	+-m [MODULE_NAME] When -f argument used pass the module name
	+-v when present will also visualize the file.
	+-x Switch liberty file used or pass specific version

	# 5. Optimisation adjusments

	-the new extended libary makes use of trivial boolean equivalent muxiplexers and operators for AND and OR operations. More info will be added later.
	+The tool will optimise the design already in primitive logic netlis tand perform MuxIG resynthesis with cut rewrittin to try to minimize the device count. All results can be viewed in the exported .csv generated after performing a test. This file contains the total count of all primitive cells used and provides a direct device count translation.

	-# Bruteforce approach
	-In \bruteforce_approach\ are a couple c files to help with small bruteforce approaches to check a minimal circuit.
	+# 6. Bruteforce approach
	+In \bruteforce_approach\ are a couple c files to help with bruteforce approaches to check a minimal circuit for different type of building blocks. Each is has some tautology recognition to allow it to peform faster. Next to that they all use pthread to allow for parralel processing to speed up execution.

	-# 6. Troubleshooting
	+# 7. Troubleshooting

	-## 6.1. SAT comparison
	-If the SAT comparison gives a comment that it is not aware of a certain `_DFF_` cell such as `_DFF_PP0` then this specific memeory cell does not exist in the standard cell library therefore it does not have the function to simulate it. These register often have asynchronous reset therefore make sure that your design does not use
	+## 7.1. SAT comparison
	+If the SAT comparison gives a comment that it is not aware of a certain `_DFF_` cell such as `_DFF_PP0` then this specific memory cell does not exist in the standard cell library therefore it does not have the function to simulate it. These register often have asynchronous reset therefore make sure that your design does not use

	```
	always@(posedge clk or posedge rst)
	if (rst) begin
	result <= 0;
	......
	```
	but instead
	```
	always@(posedge clk)
	if (rst) begin
	result <= 0;
	......
	```

	So that reset happens on the same clk as a normal `_DFF_` register.
	\ No newline at end of file
	diff --git a/bruteforce_approach/bruteforce_muxig.c b/bruteforce_approach/bruteforce_muxig.c
	index df632ce..2ed8f02 100644
	--- a/bruteforce_approach/bruteforce_muxig.c
	+++ b/bruteforce_approach/bruteforce_muxig.c
	@@ -1,473 +1,490 @@
	#include <stdarg.h>
	#include <stdio.h>
	#include <stdlib.h>
	#include <pthread.h>
	#include <stdint.h>
	#include <string.h>
	#include <unistd.h>

	// -------------- config

	#define MAX_AREA 15000 //Determine the initial max_area
	#define NUM_INPUTS 3 //speaks for itself
	#define MAX_GATES 5 // determine the max_amount of gates
	#define NUM_THREADS 3 //Needs to be <= 9 or 18 or 27 for efficient splitting the work load

	#define use_truth_table 1 //If 1 use the truth table below. If multiple outputs then paste the truth table after another from the [file].truth
	//#define target_truth_table "00000000" //exampe here [Target A][Target B] pasted after another.
	-#define target_truth_table "1110100010010110"
	+#define target_truth_table "10000001"
	/*
	The truth table matching this is that of a increase in value of the input variables
	Let's say 3 input variables

	I3 I2 I1 \| O2 O1
	A, B, Cin, \| S Cout
	0, 0, 0, \| 0 0
	0, 0, 1, \| 1 0
	0, 1, 0, \| 1 0
	0, 1, 1, \| 0 1
	1, 0, 0, \| 1 0
	1, 0, 1, \| 0 1
	1, 1, 0, \| 0 1
	1, 1, 1, \| 1 1

	S = 10010110
	Cout = 11101000
	MUX = 11001010
	target_truth_table = "S Cin" = "1110100010010110"
	also means that output B
	*/
	//AND = &&, OR = \|\|, XOR = ^, NOT = !
	int target_function(int inputs[]) {
	return inputs[0] ^ inputs[1];
	}

	// -------------- Auto-define

	#define NUM_COMBINATION (1 << NUM_INPUTS)
	#define NUM_OUTPUTS (sizeof(target_truth_table)-1)/NUM_COMBINATION

	// -------------- structs

	typedef struct {
	char* type;
	int area;
	} GateType;

	typedef struct {
	GateType* gate;
	int8_t in1;
	int8_t in2;
	int8_t in3;
	} Gate;

	typedef struct {
	Gate gates[MAX_GATES];
	int8_t gate_count;
	int area;
	} Circuit;

	typedef struct {
	Circuit volatile best_circuit;
	GateType *gate_types;
	int num_inputs;
	int num_gates;
	int volatile best_area;
	int8_t *truth_table;
	int8_t *target_outputs;
	int worker_id;
	int num_circuit[2]; //first is the amount in million and the second is the increment counter.
	pthread_mutex_t mutex;
	} ThreadArgs;


	// -------------- define used gates
	GateType gate_types[] = {
	{"INV", 1160},
	{"MUX", 1288}
	};

	// -------------- start functions
	void tee(FILE f, char const fmt, ...) {
	va_list ap;
	va_start(ap, fmt);
	vprintf(fmt, ap);
	va_end(ap);
	va_start(ap, fmt);
	vfprintf(f, fmt, ap);
	va_end(ap);
	}

	void print_circuit(Circuit * circuit){
	FILE *fptr;

	fptr = fopen("./output/output_bruteforce.txt", "a");

	//for(int y=0; y<circuit->gate_count; y++){
	// printf("%d: %s, in1: %d, in2: %d, in3: %d\n",y,circuit->gates[y].gate->type,circuit->gates[y].in1,circuit->gates[y].in2,circuit->gates[y].in3);
	//}

	tee(fptr,"------- Circuit area: %d -------\n",circuit->area);
	tee(fptr,"Input ");
	for(int i='a';(i-'a')<NUM_INPUTS;i++){tee(fptr,"%c, ",i);}
	tee(fptr,"\n");

	for(int y=0; y<circuit->gate_count; y++){
	int print_in1 = circuit->gates[y].in1 + '0';
	int print_in2 = circuit->gates[y].in2 + '0';
	int print_in3 = circuit->gates[y].in3 + '0';
	if((print_in1-2-'0')<NUM_INPUTS && (print_in1-2-'0')>=0){
	print_in1 = circuit->gates[y].in1-2 + 'a';
	}
	if((print_in2-2-'0')<NUM_INPUTS && (print_in2-2-'0')>=0){
	print_in2 = circuit->gates[y].in2-2 + 'a';
	}
	if((print_in3-2-'0')<NUM_INPUTS && (print_in3-2-'0')>=0){
	print_in3 = circuit->gates[y].in3-2 + 'a';
	}
	if(circuit->gates[y].in1==1 && circuit->gates[y].in2 == 0){ //Detected inverter
	tee(fptr,"%d: INV, in1: %c\n",y+NUM_INPUTS+2,print_in3);
	}else{ //normal muxig
	tee(fptr,"%d: %s, in1: %c, in2: %c, in3: %c\n",y+NUM_INPUTS+2,circuit->gates[y].gate->type,print_in1,print_in2,print_in3);
	}
	}

	tee(fptr,"Output ");
	for(int i='x';(i-'x')<NUM_OUTPUTS;i++){tee(fptr,"%c:%lu, ",i,NUM_INPUTS+circuit->gate_count-NUM_OUTPUTS+(i-'x')+2);}
	tee(fptr,"\n");
	tee(fptr,"----------------------------------\n");
	fclose(fptr);
	}

	void write_circuit_to_file(Circuit * circuit, int area, int worker_number, int file_number){
	FILE *fptr;

	char file_name[100];
	sprintf(file_name, "./output/output_%d_%d_%d_bruteforce.dot", area, worker_number, file_number);

	fptr = fopen(file_name, "w");

	//for(int y=0; y<circuit->gate_count; y++){
	// printf("%d: %s, in1: %d, in2: %d, in3: %d\n",y,circuit->gates[y].gate->type,circuit->gates[y].in1,circuit->gates[y].in2,circuit->gates[y].in3);
	//}
	fprintf(fptr, "digraph Circuit {\n rankdir=LR; // Makes the graph left-to-right\n node [shape=ellipse]; // Default shape for nodes\n ranksep=2; // Increases vertical separation\n");


	for(int i='a';(i-'a')<NUM_INPUTS;i++){fprintf(fptr," %c [ shape=octagon, label=\"%c\", color=\"black\", fontcolor=\"black\"]; \n",i,i);}


	for(int y=0; y<circuit->gate_count; y++){
	int print_in1 = circuit->gates[y].in1 + '0';
	int print_in2 = circuit->gates[y].in2 + '0';
	int print_in3 = circuit->gates[y].in3 + '0';
	if((print_in1-2-'0')<NUM_INPUTS && (print_in1-2-'0')>=0){
	print_in1 = circuit->gates[y].in1-2 + 'a';
	}
	if((print_in2-2-'0')<NUM_INPUTS && (print_in2-2-'0')>=0){
	print_in2 = circuit->gates[y].in2-2 + 'a';
	}
	if((print_in3-2-'0')<NUM_INPUTS && (print_in3-2-'0')>=0){
	print_in3 = circuit->gates[y].in3-2 + 'a';
	}
	int unit_number = y+NUM_INPUTS+2;

	if(circuit->gates[y].in1==1 && circuit->gates[y].in2 == 0){ //Detected inverter
	fprintf(fptr," %d [ shape=record, label=\"{{<p1> in }\|INV %d \|{<p4> out}}\", color=\"darkred\", fontcolor=\"darkred\" ];\n",unit_number,unit_number);
	fprintf(fptr," %c:e -> %d:p1;\n",print_in3,unit_number);
	} else { //normal muxig
	fprintf(fptr," %d [ shape=record, label=\"{{<p1> in 0\|<p2> in 1\|<p3> S}\| MUX %d \|{<p4> Y}}\", color=\"darkred\", fontcolor=\"darkred\" ];\n",unit_number,unit_number);
	fprintf(fptr," %c:e -> %d:p1;\n %c:e -> %d:p2;\n %c:e -> %d:p3;\n",print_in1,unit_number,print_in2,unit_number,print_in3,unit_number);
	}
	}

	for(int i='x';(i-'x')<NUM_OUTPUTS;i++){fprintf(fptr," %lu:e -> %c;\n",NUM_INPUTS+circuit->gate_count-NUM_OUTPUTS+(i-'x')+2,i);}


	fprintf(fptr,"}\n");
	fclose(fptr);
	}

	void evaluate_circuit(GateType* all_gates, Circuit* circuit, int8_t* inputs, int8_t* outputs) {
	int8_t intermediate_outputs[NUM_INPUTS + MAX_GATES+2];
	intermediate_outputs[0] = 0; //Make sure that intermediate_outputs[0] = 0 and [1] = 1 for constant signal attachments
	intermediate_outputs[1] = 1;
	memcpy(&intermediate_outputs[2], inputs, NUM_INPUTS * sizeof(int8_t)); //copy boolean value over this

	for (int i = 0; i < circuit->gate_count; i++) {
	int out1 = intermediate_outputs[circuit->gates[i].in1];
	int out2 = intermediate_outputs[circuit->gates[i].in2];
	int out3 = intermediate_outputs[circuit->gates[i].in3];
	int output = 0;

	if (circuit->gates[i].gate == &all_gates[0]) //INV
	- output = ~out1 & 1;
	+ output = ~out3 & 1;
	else if (circuit->gates[i].gate == &all_gates[1]) //MUX
	output = out3 ? out2 : out1;

	intermediate_outputs[NUM_INPUTS + i + 2] = output;
	}

	for(int z=0; z<NUM_OUTPUTS;z++){
	outputs[z] = intermediate_outputs[NUM_INPUTS + 2 + circuit->gate_count-NUM_OUTPUTS+z];
	}
	}

	int detect_tautology(Circuit current_circuit, int in1, int in2, int in3, int gate_selected, ThreadArgs data){
	if ((in1 == in2 && gate_selected != 0) \|\|
	(in1 == in3 \|\| in2 == in3) \|\|
	(in1 == 0 && in2 == 1 && gate_selected != 0) ){ //\|\| //Skip gate if it has the same input both ports NOTE THAT IF i == 0 THEN WE SELECT INV.
	return 1;
	}


	for(int i=0; i<(current_circuit->gate_count-1);i++){
	if(current_circuit->gates[i].gate == &data->gate_types[gate_selected]){
	if(current_circuit->gates[i].in1 == in1 && current_circuit->gates[i].in2 == in2 && current_circuit->gates[i].in3 == in3){
	return 1; //DETECTED A COMPLETE equivalent circuit
	}
	}
	}

	int input_used[current_circuit->gate_count + data->num_inputs+2];
	memset(input_used, 0, sizeof(input_used));

	input_used[0] = 1; //make sure that the constant don't trigger a faulty tautology result.
	input_used[1] = 1;

	for(int i=0; i<current_circuit->gate_count; i++){
	input_used[current_circuit->gates[i].in1] = 1;
	input_used[current_circuit->gates[i].in2] = 1;
	input_used[current_circuit->gates[i].in3] = 1;
	}

	input_used[in1] = 1;
	input_used[in2] = 1;
	input_used[in3] = 1;

	for(int i=0; i < (current_circuit->gate_count + data->num_inputs - NUM_OUTPUTS+2); i++){
	if(input_used[i]==0 && current_circuit->gate_count!=0){
	return 2; //missing an used output
	}
	}

	return 0;
	}

	void generate_circuits_recursive(Circuit current_circuit, int depth, ThreadArgs data) {
	if (depth == data->num_gates){
	// Reached end of amount of gates.
	return;
	}

	GateType* gate_types = data->gate_types;

	// Loop through gate types and inputs to build possible circuits
	//int num_gate_types = 1;
	//int division = (num_gate_types + NUM_THREADS-1)/NUM_THREADS;
	//int multi_core_division=NUM_THREADS/num_gate_types;
	//0 - 2, 3 - 5, 6 - 8
	//for (int i = 0; i < num_gate_types; i++) {
	- int i = 1; //Only select the multiplexer

	- if((current_circuit->area+data->gate_types[i].area)>data->best_area){
	+ if((current_circuit->area+data->gate_types[0].area)>data->best_area){
	//printf("worker %d: area %d on gate type %d and depth %d larger then best area %d continueing\n",data->worker_id,current_circuit->area,i,depth,data->best_area);
	return;
	}

	for (int in3 = 2; in3 < depth + data->num_inputs + 2; in3++){

	//Going for multithread approach
	if(in3 != data->worker_id+2 && depth == 0){
	continue;
	}

	for (int in2 = 0; in2 < depth + data->num_inputs + 2; in2++) {
	for (int in1 = 0; in1 < depth + data->num_inputs + 2; in1++){
	data->num_circuit[0] += 1;



	// Add the new gate to the circuit
	- current_circuit->gates[depth].gate = &gate_types[i]; //set pointer to the type of gate
	+ current_circuit->gates[depth].gate = &gate_types[1]; //set pointer to the type of gate
	+ if(in1 == 1 && in2 == 0){
	+ current_circuit->gates[depth].gate = &gate_types[0]; //set the pointer to inv
	+ }
	current_circuit->gates[depth].in1 = in1;
	current_circuit->gates[depth].in2 = in2;
	current_circuit->gates[depth].in3 = in3;
	current_circuit->gate_count = depth + 1;

	+
	+
	//if(current_circuit->gates[0].in1 == 0 && current_circuit->gates[0].in2 == 1 && current_circuit->gates[0].in3 == 3 && current_circuit->gates[1].in1 == 2 && current_circuit->gates[1].in2 == 3 && current_circuit->gates[1].in3 == 4 && current_circuit->gates[2].in1 == 4 && current_circuit->gates[2].in2 == 5 && current_circuit->gates[2].in3 == 6){// && current_circuit->gates[2].gate==&data->gate_types[6]){
	- //if(current_circuit->gates[0].in1 == 2 && current_circuit->gates[0].in2 == 3 && current_circuit->gates[0].in3 == 4){
	+ //if(current_circuit->gates[0].gate == &data->gate_types[0] && current_circuit->gates[0].in3 == 2 // a:2 b:3 c:4 I1:5 I2:6 MUX1:7 MUX2:8
	+ //&& current_circuit->gates[1].gate == &data->gate_types[0] && current_circuit->gates[1].in3 == 4
	+ //&& current_circuit->gates[2].gate == &data->gate_types[1] && current_circuit->gates[2].in1 == 5 && current_circuit->gates[2].in2 == 2 && current_circuit->gates[2].in3 == 3
	+ //&& current_circuit->gates[3].gate == &data->gate_types[1] && current_circuit->gates[3].in1 == 4 && current_circuit->gates[3].in2 == 6 && current_circuit->gates[3].in3 == 7
	+ //){
	// printf("test\n");
	//}

	- int tautology = detect_tautology(current_circuit,in1,in2,in3,i,data); //0: nothing found, 1: direct tautology, 2:unconnected device may still be connected.
	+ int tautology = detect_tautology(current_circuit,in1,in2,in3,1,data); //0: nothing found, 1: direct tautology, 2:unconnected device may still be connected.
	if(tautology==1){
	continue; //Found already unnecessary combo and should skip it
	}


	int valid = 0;

	if(tautology!=2){ //There is an unconnected gate if this holds true
	valid = 1;
	int8_t output[NUM_OUTPUTS];
	for (int y=0; y < (1 << data->num_inputs); y++){ //CHECK IF IT IS VALID
	evaluate_circuit(data->gate_types, current_circuit, &data->truth_table[y*data->num_inputs], output);
	for(int z=0; z<NUM_OUTPUTS;z++){
	if(output[z]!=data->target_outputs[y+NUM_COMBINATION*z]){
	valid = 0;
	}
	}
	}
	}
	//valid circuit add area
	- current_circuit->area += gate_types[i].area; // Example area increment (modify as needed)
	+ if(in1 == 1 && in2 == 0){
	+ current_circuit->area += gate_types[0].area;
	+ } else {
	+ current_circuit->area += gate_types[1].area; // Example area increment (modify as needed)
	+ }

	if(data->num_circuit[0]%1000000000 == 0){
	data->num_circuit[1] += 1;
	data->num_circuit[0] = 0;
	printf("%d:At circuit number %d M current best_area %d and tested area %d\n",data->worker_id,data->num_circuit[1],data->best_area,current_circuit->area);
	}

	pthread_mutex_lock(&data->mutex); //get mutex
	if(valid == 1 && current_circuit->area<data->best_area){
	//Found a valid solution!
	memcpy((void *)&data->best_circuit, current_circuit, sizeof(Circuit)); //write to best circuit
	printf("%d: Found proper solution\n",data->worker_id);
	print_circuit(current_circuit);
	write_circuit_to_file(current_circuit,current_circuit->area,data->worker_id,data->num_circuit[0]*100 + data->num_circuit[1]);
	data->best_area = current_circuit->area;
	}
	pthread_mutex_unlock(&data->mutex);
	// Recurse to add more gates

	generate_circuits_recursive(current_circuit, depth + 1, data);
	- current_circuit->area -= gate_types[i].area; // Example area increment (modify as needed)
	+
	+ if(in1 == 1 && in2 == 0){
	+ current_circuit->area -= gate_types[0].area;
	+ } else {
	+ current_circuit->area -= gate_types[1].area; // Example area increment (modify as needed)
	+ }
	//printf("worker %d: returning with depth %d and area %d\n",data->worker_id,depth,current_circuit->area);
	}
	}
	}
	}

	void* search_space_worker(void* args) {
	// Define and initialize worker-specific parameters and loop through circuits
	// You will need to pass parameters in `args` and cast them in this function
	ThreadArgs *data;
	data = (ThreadArgs *) args;

	Circuit current_circuit;
	current_circuit.area = 0;
	current_circuit.gate_count = 0;

	printf("%d: best Area %d, Going in recusive loop to check all circuits\n",data->worker_id, data->best_area);
	generate_circuits_recursive(&current_circuit, 0, data);

	//finished set worker_id to 1000 to indicate to the management thread that we finished
	pthread_mutex_lock(&data->mutex);
	data->worker_id = 1000;
	pthread_mutex_unlock(&data->mutex);

	return NULL; // Return the best found circuit and area as needed
	}


	void brute_force_boolean(Circuit* best_circuit, int8_t truth_table[], int8_t target_outputs[], int num_inputs, int max_gates, int max_area) {
	pthread_t threads[NUM_THREADS];
	ThreadArgs thread_args[NUM_THREADS]; // Define `ThreadArgs` to pass data to threads
	int best_area = max_area;
	int total_circuits = 0;



	for (int i = 0; i < NUM_THREADS; i++) {
	thread_args[i].gate_types = gate_types;
	thread_args[i].num_inputs = num_inputs;
	thread_args[i].num_gates = max_gates;
	thread_args[i].best_area = best_area;
	thread_args[i].truth_table = truth_table;
	thread_args[i].target_outputs = target_outputs;
	thread_args[i].worker_id = i;
	thread_args[i].num_circuit[0] = 0;
	thread_args[i].num_circuit[1] = 0;
	pthread_mutex_init(&thread_args[i].mutex, NULL);
	pthread_create(&threads[i], NULL, search_space_worker, (void *)&thread_args[i]);
	}

	clock_t begin = clock();
	int number_of_running_threads = NUM_THREADS;
	while(number_of_running_threads>0){
	number_of_running_threads = NUM_THREADS;
	for (int i = 0; i < NUM_THREADS; i++) {
	pthread_mutex_lock(&thread_args[i].mutex); //get lock on the data

	//Check if it found a better circuit then known before.
	if(thread_args[i].best_area<best_area){
	best_area = thread_args[i].best_area;
	printf("Found best circuit at size %d, on worker: %d\n",best_area,i);
	memcpy(best_circuit, (void *)&thread_args[i].best_circuit, sizeof(Circuit));
	}

	//found a better circuit by another thread. Update data variable so that it does not searche longer where not necessary
	if(thread_args[i].best_area>best_area){
	printf("setting the best_area size %d, on worker: %d\n",best_area,i);
	thread_args[i].best_area = best_area;
	}

	//lastly check if the thread_closed
	if(thread_args[i].worker_id==1000){
	number_of_running_threads -= 1;
	}
	pthread_mutex_unlock(&thread_args[i].mutex);
	// Collect best circuits and area from each thread
	}

	clock_t toc = clock();
	printf("%f: running number of threads: %d\n",(double)(toc - begin) / (CLOCKS_PER_SEC*number_of_running_threads),number_of_running_threads);
	sleep(5);
	}
	printf("no threads running anymore\n");
	// Output the best circuit

	//count total amount of circuits
	for(int i=0;i<NUM_THREADS;i++){
	total_circuits += thread_args[i].num_circuit[1];
	}

	printf("Total amount of circuits searched is %d M\n",total_circuits);
	}

	void fill_target_outputs(int8_t truth_table[], int8_t target_outputs[], int num_inputs) {
	int num_combinations = NUM_COMBINATION;
	for (int i = 0; i < num_combinations; i++) {
	int inputs[num_inputs];
	for (int j = 0; j < num_inputs; j++) {
	inputs[j] = (i >> j) & 1; // Extract each bit of i as an input
	truth_table[i*num_inputs+j] = (i >> j) & 1;;
	}
	target_outputs[i] = target_function(inputs);
	}
	}



	int main() {
	// Define target function output
	int8_t target_outputs[NUM_COMBINATION*NUM_OUTPUTS]; // 1<<NUM_INPUTS is equivalent to 2^NUM_INPUTS
	int8_t truth_table[NUM_COMBINATION*NUM_INPUTS]; // create a truth_table the size of target_output with an entry for every input.
	fill_target_outputs(truth_table, target_outputs, NUM_INPUTS);

	if(use_truth_table){
	for(int i=0; i<(NUM_COMBINATION*NUM_OUTPUTS); i++){
	target_outputs[i] = target_truth_table[(NUM_COMBINATION*NUM_OUTPUTS-1)-i]-'0'; //load in the truth table but then flipped
	}
	}

	Circuit best_circuit;
	brute_force_boolean(&best_circuit, truth_table, target_outputs, NUM_INPUTS, MAX_GATES, MAX_AREA);

	printf("Found best solution\n");
	print_circuit(&best_circuit);
	write_circuit_to_file(&best_circuit,best_circuit.area,0,0);
	// Print best circuit details
	return 0;
	}

	diff --git a/mockturtle_binaries/sim_resubstitution b/mockturtle_binaries/sim_resubstitution
	new file mode 100755
	index 0000000..ca514dd
	Binary files /dev/null and b/mockturtle_binaries/sim_resubstitution differ
	diff --git a/nem_liberty/nem_basic_yosys.lib b/nem_liberty/nem_basic_original.lib
	similarity index 95%
	copy from nem_liberty/nem_basic_yosys.lib
	copy to nem_liberty/nem_basic_original.lib
	index 7f733ac..9162afa 100644
	--- a/nem_liberty/nem_basic_yosys.lib
	+++ b/nem_liberty/nem_basic_original.lib
	@@ -1,1850 +1,1826 @@
	library (nem_basic) {
	comment : "Manually created liberty with more gates - ignore any timing information";
	date : "$April 26th 2024$";
	revision : "0.2";
	delay_model : table_lookup;
	capacitive_load_unit (1,pf);
	time_unit : "1ns";
	current_unit : "1uA";
	voltage_unit : "1V";
	voltage_map (VCC,15);
	voltage_map (GND,0);
	default_cell_leakage_power : 0;
	default_fanout_load : 1;
	default_max_transition : 500;
	default_output_pin_cap : 0;
	input_threshold_pct_rise : 50.0;
	input_threshold_pct_fall : 50.0;
	output_threshold_pct_rise : 50.0;
	output_threshold_pct_fall : 50.0;
	slew_lower_threshold_pct_rise : 20.0;
	slew_lower_threshold_pct_fall : 20.0;
	slew_upper_threshold_pct_rise : 80.0;
	slew_upper_threshold_pct_fall : 80.0;
	slew_derate_from_library : 1.0;
	nom_process : 1;
	nom_temperature : 125;
	nom_voltage : 15;

	operating_conditions (NEM_BASIC_COND) {
	process : 1;
	temperature : 125;
	voltage : 29;
	}
	default_operating_conditions : NEM_BASIC_COND;

	lu_table_template (delay_template_2x2) {
	variable_1 : input_net_transition;
	variable_2 : total_output_net_capacitance;
	index_1("0.01,0.1");
	index_2("0.02,0.2");
	}

	lu_table_template (constraint_template_2x2) {
	variable_1 : constrained_pin_transition;
	variable_2 : related_pin_transition;
	index_1("0.01,0.1");
	index_2("0.02,0.2");
	}

	cell(inv_3T) {
	area : 1160;
	cell_footprint : inv_3T;
	/* cell_description : "NEM 3T Inverter"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (in) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "!(in)";
	max_capacitance : 10;
	max_fanout : 10;
	max_transition : 500;
	timing () {
	related_pin : "in";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(buf_3T) {
	area : 2240;
	cell_footprint : buf_3T;
	/* cell_description : "NEM 3T Buffer"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (in) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "in";
	max_capacitance : 10;
	max_fanout : 10;
	max_transition : 500;
	timing () {
	related_pin : "in";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(nand_3T) {
	area : 2832;
	cell_footprint : nand_3T;
	/* cell_description : "NEM 3T 2-Input NAND"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "!(a&b)";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}


	cell(and_3T) {
	area : 3912;
	cell_footprint : and_3T;
	/* cell_description : "NEM 3T 2-Input AND"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "a&b";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(nor_3T) {
	area : 2832;
	cell_footprint : nor_3T;
	/* cell_description : "NEM 3T 2-Input NOR"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "!(a\|b)";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(or_3T) {
	area : 3952;
	cell_footprint : or_3T;
	/* cell_description : "NEM 3T 2-Input OR"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "a\|b";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(xnor_3T) {
	area : 7824;
	cell_footprint : xnor_3T;
	/* cell_description : "NEM 3T 2-Input XNOR"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "!(a^b)";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(xor_3T) {
	area : 7824;
	cell_footprint : xor_3T;
	/* cell_description : "NEM 3T 2-Input XOR"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "a^b";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}


	cell(mux_3T) {
	area : 8000;
	cell_footprint : mux_3T;
	/* cell_description : "NEM 3T 2-Input MUX"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	- /*bundle(in) {
	+ bundle(in) {
	members(in_0,in_1);
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	- }*/
	- pin(in_0){
	- direction : "input";
	- related_ground_pin : GND;
	- related_power_pin : VCC;
	- capacitance : 1;
	- }
	- pin(in_1){
	- direction : "input";
	- related_ground_pin : GND;
	- related_power_pin : VCC;
	- capacitance : 1;
	}
	pin (sel) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "(!sel & in_0) \| (sel & in_1)";
	max_fanout : 10;
	timing () {
	related_pin : "in_0";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "in_1";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "sel";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}


	cell(mux_4T) {
	area : 3472;
	cell_footprint : mux_4T;
	/* cell_description : "NEM 4T 2-Input MUX"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	- /*bundle(in) {
	+ bundle(in){
	members(in_0,in_1);
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	- }*/
	- pin(in_0){
	- direction : "input";
	- related_ground_pin : GND;
	- related_power_pin : VCC;
	- capacitance : 1;
	- }
	- pin(in_1){
	- direction : "input";
	- related_ground_pin : GND;
	- related_power_pin : VCC;
	- capacitance : 1;
	}
	pin (sel) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "(!sel & in_0) \| (sel & in_1)";
	max_fanout : 10;
	timing () {
	related_pin : "in_0";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "in_1";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "sel";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	/*
	cell(SR_latch) {
	area : 2704;
	cell_footprint : SR_latch;
	cell_description : "NEM based S-R type Latch";
	pin (S) {
	direction : "input";
	}
	pin (R) {
	direction : "input";
	}
	pin (Q) {
	direction : "output";
	function : "IQ";
	}
	pin (Q_bar) {
	direction : "output";
	function : "IQB";
	}
	latch (IQ,IQB) {
	preset : "S"
	clear : "R"
	clear_preset_var1 : L;
	clear_preset_var2 : L;
	}
	statetable (" R S ", " IQ IQB "){
	table : "H L : - - : L H ,\
	L H : - - : H L ,\
	H H : - - : L L ,\
	L L : - - : N N";
	}
	}
	*/

	cell(D_latch) {
	area : 9448;
	cell_footprint : D_latch;
	/* cell_description : "NEM based D type Latch"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	/* data_in_type : data;*/
	/*
	timing() {
	related_pin : "EN";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing() {
	related_pin : "EN";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	*/
	}
	pin (EN) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	/*
	timing () {
	related_pin : "D";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "EN";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	*/
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	/*
	timing () {
	related_pin : "D";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "EN";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	*/
	}
	latch (QOUT,QBOUT) {
	enable : "EN";
	data_in : "D";
	}
	}


	cell(D_latch_rst) {
	area : 13432;
	cell_footprint : D_latch_rst;
	/* cell_description : "NEM based D type Latch with reset"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	/* data_in_type : data;*/
	}
	pin (EN) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (rst) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "D";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "EN";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	- values ("0.2,4darkblue.0","0.21,4.1");
	+ values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "D";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "EN";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	latch (QOUT,QBOUT) {
	enable : "EN";
	data_in : "D";
	clear : "rst";
	}
	}

	cell(D_FF) {
	area : 20056;
	cell_footprint : D_FF;
	/* cell_description : "NEM based M-S D type Flip Flop"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	nextstate_type : data;
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	max_transition : 0.2;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	}
	pin (CLK) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	ff (QOUT,QBOUT) {
	clocked_on : "CLK";
	next_state : "D";
	}
	}

	cell(D_FF_rst) {
	area : 28184;
	cell_footprint : D_FF_rst;
	/* cell_description : "NEM based M-S D type Flip Flop with reset"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	nextstate_type : data;
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	max_transition : 0.2;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,-4.0","0.21,4.1");
	}
	}
	}
	pin (rst) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : recovery_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : removal_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	}
	}
	pin (CLK) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	ff (QOUT,QBOUT) {
	clear : "rst";
	clocked_on : "CLK";
	next_state : "D";
	}
	}

	/* SCAN FUNCTIONALITY HASN'T BEEN ADDED YET */
	cell(S_FF) {
	area : 20056;
	cell_footprint : D_FF;
	/* cell_description : "NEM based M-S D type Flip Flop with scan functionality";*/
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	nextstate_type : data;
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	max_transition : 0.2;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	}
	pin (SI) {
	nextstate_type : data;
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	max_transition : 0.2;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	}
	pin (CLK) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	ff (QOUT,QBOUT) {
	clocked_on : "CLK";
	next_state : "D";
	}
	}

	/* SCAN FUNCTIONALITY HASN'T BEEN ADDED YET */
	cell(S_FF_rst) {
	area : 28184;
	cell_footprint : S_FF_rst;
	/* cell_description : "NEM based M-S D type Flip Flop with reset and scan functionality"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	nextstate_type : data;
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	max_transition : 0.2;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,-4.0","0.21,4.1");
	}
	}
	}
	pin (rst) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : recovery_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : removal_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	}
	}
	pin (CLK) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	ff (QOUT,QBOUT) {
	clear : "rst";
	clocked_on : "CLK";
	next_state : "D";
	}
	}
	}
	diff --git a/nem_liberty/nem_basic_yosys.lib b/nem_liberty/nem_basic_yosys.lib
	index 7f733ac..537931a 100644
	--- a/nem_liberty/nem_basic_yosys.lib
	+++ b/nem_liberty/nem_basic_yosys.lib
	@@ -1,1850 +1,1728 @@
	library (nem_basic) {
	comment : "Manually created liberty with more gates - ignore any timing information";
	date : "$April 26th 2024$";
	revision : "0.2";
	delay_model : table_lookup;
	capacitive_load_unit (1,pf);
	time_unit : "1ns";
	current_unit : "1uA";
	voltage_unit : "1V";
	voltage_map (VCC,15);
	voltage_map (GND,0);
	default_cell_leakage_power : 0;
	default_fanout_load : 1;
	default_max_transition : 500;
	default_output_pin_cap : 0;
	input_threshold_pct_rise : 50.0;
	input_threshold_pct_fall : 50.0;
	output_threshold_pct_rise : 50.0;
	output_threshold_pct_fall : 50.0;
	slew_lower_threshold_pct_rise : 20.0;
	slew_lower_threshold_pct_fall : 20.0;
	slew_upper_threshold_pct_rise : 80.0;
	slew_upper_threshold_pct_fall : 80.0;
	slew_derate_from_library : 1.0;
	nom_process : 1;
	nom_temperature : 125;
	nom_voltage : 15;

	operating_conditions (NEM_BASIC_COND) {
	process : 1;
	temperature : 125;
	voltage : 29;
	}
	default_operating_conditions : NEM_BASIC_COND;

	lu_table_template (delay_template_2x2) {
	variable_1 : input_net_transition;
	variable_2 : total_output_net_capacitance;
	index_1("0.01,0.1");
	index_2("0.02,0.2");
	}

	lu_table_template (constraint_template_2x2) {
	variable_1 : constrained_pin_transition;
	variable_2 : related_pin_transition;
	index_1("0.01,0.1");
	index_2("0.02,0.2");
	}

	cell(inv_3T) {
	area : 1160;
	cell_footprint : inv_3T;
	/* cell_description : "NEM 3T Inverter"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (in) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "!(in)";
	max_capacitance : 10;
	max_fanout : 10;
	max_transition : 500;
	timing () {
	related_pin : "in";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(buf_3T) {
	area : 2240;
	cell_footprint : buf_3T;
	/* cell_description : "NEM 3T Buffer"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (in) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "in";
	max_capacitance : 10;
	max_fanout : 10;
	max_transition : 500;
	timing () {
	related_pin : "in";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(nand_3T) {
	area : 2832;
	cell_footprint : nand_3T;
	/* cell_description : "NEM 3T 2-Input NAND"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "!(a&b)";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}


	cell(and_3T) {
	area : 3912;
	cell_footprint : and_3T;
	/* cell_description : "NEM 3T 2-Input AND"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "a&b";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(nor_3T) {
	area : 2832;
	cell_footprint : nor_3T;
	/* cell_description : "NEM 3T 2-Input NOR"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "!(a\|b)";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(or_3T) {
	area : 3952;
	cell_footprint : or_3T;
	/* cell_description : "NEM 3T 2-Input OR"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "a\|b";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(xnor_3T) {
	area : 7824;
	cell_footprint : xnor_3T;
	/* cell_description : "NEM 3T 2-Input XNOR"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "!(a^b)";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(xor_3T) {
	area : 7824;
	cell_footprint : xor_3T;
	/* cell_description : "NEM 3T 2-Input XOR"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "a^b";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}


	cell(mux_3T) {
	area : 8000;
	cell_footprint : mux_3T;
	/* cell_description : "NEM 3T 2-Input MUX"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	/*bundle(in) {
	members(in_0,in_1);
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}*/
	pin(in_0){
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin(in_1){
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (sel) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "(!sel & in_0) \| (sel & in_1)";
	max_fanout : 10;
	timing () {
	related_pin : "in_0";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "in_1";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "sel";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	-
	-cell(mux_4T) {
	- area : 3472;
	- cell_footprint : mux_4T;
	-/* cell_description : "NEM 4T 2-Input MUX"; */
	- pg_pin (VCC) {
	- pg_type : primary_power;
	- voltage_name : "VCC";
	- }
	- pg_pin (GND) {
	- pg_type : primary_ground;
	- voltage_name : "GND";
	- }
	- /*bundle(in) {
	- members(in_0,in_1);
	- direction : "input";
	- related_ground_pin : GND;
	- related_power_pin : VCC;
	- capacitance : 1;
	- }*/
	- pin(in_0){
	- direction : "input";
	- related_ground_pin : GND;
	- related_power_pin : VCC;
	- capacitance : 1;
	- }
	- pin(in_1){
	- direction : "input";
	- related_ground_pin : GND;
	- related_power_pin : VCC;
	- capacitance : 1;
	- }
	- pin (sel) {
	- direction : "input";
	- related_ground_pin : GND;
	- related_power_pin : VCC;
	- capacitance : 1;
	- }
	- pin (out) {
	- direction : "output";
	- related_ground_pin : GND;
	- related_power_pin : VCC;
	- function : "(!sel & in_0) \| (sel & in_1)";
	- max_fanout : 10;
	- timing () {
	- related_pin : "in_0";
	- timing_sense : positive_unate;
	- timing_type : combinational;
	- cell_rise (delay_template_2x2) {
	- index_1 ("0.01,0.1");
	- index_2 ("0.02,0.2");
	- values ("0.2,2.0","0.21,2.1");
	- }
	- rise_transition (delay_template_2x2) {
	- index_1 ("0.01,0.1");
	- index_2 ("0.02,0.2");
	- values ("0.2,4.0","0.21,4.1");
	- }
	- cell_fall (delay_template_2x2) {
	- index_1 ("0.01,0.1");
	- index_2 ("0.02,0.2");
	- values ("0.2,2.0","0.21,2.1");
	- }
	- fall_transition (delay_template_2x2) {
	- index_1 ("0.01,0.1");
	- index_2 ("0.02,0.2");
	- values ("0.2,4.0","0.21,4.1");
	- }
	- }
	- timing () {
	- related_pin : "in_1";
	- timing_sense : positive_unate;
	- timing_type : combinational;
	- cell_rise (delay_template_2x2) {
	- index_1 ("0.01,0.1");
	- index_2 ("0.02,0.2");
	- values ("0.2,2.0","0.21,2.1");
	- }
	- rise_transition (delay_template_2x2) {
	- index_1 ("0.01,0.1");
	- index_2 ("0.02,0.2");
	- values ("0.2,4.0","0.21,4.1");
	- }
	- cell_fall (delay_template_2x2) {
	- index_1 ("0.01,0.1");
	- index_2 ("0.02,0.2");
	- values ("0.2,2.0","0.21,2.1");
	- }
	- fall_transition (delay_template_2x2) {
	- index_1 ("0.01,0.1");
	- index_2 ("0.02,0.2");
	- values ("0.2,4.0","0.21,4.1");
	- }
	- }
	- timing () {
	- related_pin : "sel";
	- timing_sense : non_unate;
	- timing_type : combinational;
	- cell_rise (delay_template_2x2) {
	- index_1 ("0.01,0.1");
	- index_2 ("0.02,0.2");
	- values ("0.2,2.0","0.21,2.1");
	- }
	- rise_transition (delay_template_2x2) {
	- index_1 ("0.01,0.1");
	- index_2 ("0.02,0.2");
	- values ("0.2,4.0","0.21,4.1");
	- }
	- cell_fall (delay_template_2x2) {
	- index_1 ("0.01,0.1");
	- index_2 ("0.02,0.2");
	- values ("0.2,2.0","0.21,2.1");
	- }
	- fall_transition (delay_template_2x2) {
	- index_1 ("0.01,0.1");
	- index_2 ("0.02,0.2");
	- values ("0.2,4.0","0.21,4.1");
	- }
	- }
	- }
	-}
	-
	/*
	cell(SR_latch) {
	area : 2704;
	cell_footprint : SR_latch;
	cell_description : "NEM based S-R type Latch";
	pin (S) {
	direction : "input";
	}
	pin (R) {
	direction : "input";
	}
	pin (Q) {
	direction : "output";
	function : "IQ";
	}
	pin (Q_bar) {
	direction : "output";
	function : "IQB";
	}
	latch (IQ,IQB) {
	preset : "S"
	clear : "R"
	clear_preset_var1 : L;
	clear_preset_var2 : L;
	}
	statetable (" R S ", " IQ IQB "){
	table : "H L : - - : L H ,\
	L H : - - : H L ,\
	H H : - - : L L ,\
	L L : - - : N N";
	}
	}
	*/

	cell(D_latch) {
	area : 9448;
	cell_footprint : D_latch;
	/* cell_description : "NEM based D type Latch"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	/* data_in_type : data;*/
	/*
	timing() {
	related_pin : "EN";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing() {
	related_pin : "EN";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	*/
	}
	pin (EN) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	/*
	timing () {
	related_pin : "D";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "EN";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	*/
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	/*
	timing () {
	related_pin : "D";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "EN";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	*/
	}
	latch (QOUT,QBOUT) {
	enable : "EN";
	data_in : "D";
	}
	}


	cell(D_latch_rst) {
	area : 13432;
	cell_footprint : D_latch_rst;
	/* cell_description : "NEM based D type Latch with reset"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	/* data_in_type : data;*/
	}
	pin (EN) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (rst) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "D";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "EN";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4darkblue.0","0.21,4.1");
	}
	}
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "D";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "EN";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	latch (QOUT,QBOUT) {
	enable : "EN";
	data_in : "D";
	clear : "rst";
	}
	}

	cell(D_FF) {
	area : 20056;
	cell_footprint : D_FF;
	/* cell_description : "NEM based M-S D type Flip Flop"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	nextstate_type : data;
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	max_transition : 0.2;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	}
	pin (CLK) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	ff (QOUT,QBOUT) {
	clocked_on : "CLK";
	next_state : "D";
	}
	}

	cell(D_FF_rst) {
	area : 28184;
	cell_footprint : D_FF_rst;
	/* cell_description : "NEM based M-S D type Flip Flop with reset"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	nextstate_type : data;
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	max_transition : 0.2;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,-4.0","0.21,4.1");
	}
	}
	}
	pin (rst) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : recovery_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : removal_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	}
	}
	pin (CLK) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	ff (QOUT,QBOUT) {
	clear : "rst";
	clocked_on : "CLK";
	next_state : "D";
	}
	}

	/* SCAN FUNCTIONALITY HASN'T BEEN ADDED YET */
	cell(S_FF) {
	area : 20056;
	cell_footprint : D_FF;
	/* cell_description : "NEM based M-S D type Flip Flop with scan functionality";*/
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	nextstate_type : data;
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	max_transition : 0.2;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	}
	pin (SI) {
	nextstate_type : data;
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	max_transition : 0.2;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	}
	pin (CLK) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	ff (QOUT,QBOUT) {
	clocked_on : "CLK";
	next_state : "D";
	}
	}

	/* SCAN FUNCTIONALITY HASN'T BEEN ADDED YET */
	cell(S_FF_rst) {
	area : 28184;
	cell_footprint : S_FF_rst;
	/* cell_description : "NEM based M-S D type Flip Flop with reset and scan functionality"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	nextstate_type : data;
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	max_transition : 0.2;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,-4.0","0.21,4.1");
	}
	}
	}
	pin (rst) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : recovery_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : removal_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	}
	}
	pin (CLK) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	ff (QOUT,QBOUT) {
	clear : "rst";
	clocked_on : "CLK";
	next_state : "D";
	}
	}
	}
	diff --git a/nem_liberty/nem_basic_yosys_extended.lib b/nem_liberty/nem_basic_yosys_extended.lib
	index 9b9d471..27194e3 100644
	--- a/nem_liberty/nem_basic_yosys_extended.lib
	+++ b/nem_liberty/nem_basic_yosys_extended.lib
	@@ -1,2514 +1,2514 @@
	library (nem_basic) {
	comment : "Manually created liberty with more gates - ignore any timing information";
	date : "$April 26th 2024$";
	revision : "0.2";
	delay_model : table_lookup;
	capacitive_load_unit (1,pf);
	time_unit : "1ns";
	current_unit : "1uA";
	voltage_unit : "1V";
	voltage_map (VCC,15);
	voltage_map (GND,0);
	default_cell_leakage_power : 0;
	default_fanout_load : 1;
	default_max_transition : 500;
	default_output_pin_cap : 0;
	input_threshold_pct_rise : 50.0;
	input_threshold_pct_fall : 50.0;
	output_threshold_pct_rise : 50.0;
	output_threshold_pct_fall : 50.0;
	slew_lower_threshold_pct_rise : 20.0;
	slew_lower_threshold_pct_fall : 20.0;
	slew_upper_threshold_pct_rise : 80.0;
	slew_upper_threshold_pct_fall : 80.0;
	slew_derate_from_library : 1.0;
	nom_process : 1;
	nom_temperature : 125;
	nom_voltage : 15;

	operating_conditions (NEM_BASIC_COND) {
	process : 1;
	temperature : 125;
	voltage : 29;
	}
	default_operating_conditions : NEM_BASIC_COND;

	lu_table_template (delay_template_2x2) {
	variable_1 : input_net_transition;
	variable_2 : total_output_net_capacitance;
	index_1("0.01,0.1");
	index_2("0.02,0.2");
	}

	lu_table_template (constraint_template_2x2) {
	variable_1 : constrained_pin_transition;
	variable_2 : related_pin_transition;
	index_1("0.01,0.1");
	index_2("0.02,0.2");
	}

	cell(inv_3T) {
	area : 1160;
	cell_footprint : inv_3T;
	/* cell_description : "NEM 3T Inverter"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (in) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "!(in)";
	max_capacitance : 10;
	max_fanout : 10;
	max_transition : 500;
	timing () {
	related_pin : "in";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(buf_3T) {
	area : 2240;
	cell_footprint : buf_3T;
	/* cell_description : "NEM 3T Buffer"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (in) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "in";
	max_capacitance : 10;
	max_fanout : 10;
	max_transition : 500;
	timing () {
	related_pin : "in";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(nand_3T) {
	area : 2832;
	cell_footprint : nand_3T;
	/* cell_description : "NEM 3T 2-Input NAND"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "!(a&b)";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}


	cell(and_3T) {
	area : 3912;
	cell_footprint : and_3T;
	/* cell_description : "NEM 3T 2-Input AND"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "a&b";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(nor_3T) {
	area : 2832;
	cell_footprint : nor_3T;
	/* cell_description : "NEM 3T 2-Input NOR"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "!(a\|b)";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(or_3T) {
	area : 3952;
	cell_footprint : or_3T;
	/* cell_description : "NEM 3T 2-Input OR"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "a\|b";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(xnor_3T) {
	area : 7824;
	cell_footprint : xnor_3T;
	/* cell_description : "NEM 3T 2-Input XNOR"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "!(a^b)";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(xor_3T) {
	area : 7824;
	cell_footprint : xor_3T;
	/* cell_description : "NEM 3T 2-Input XOR"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "a^b";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}


	cell(mux_3T) {
	area : 8000;
	cell_footprint : mux_3T;
	/* cell_description : "NEM 3T 2-Input MUX"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	/*bundle(in) {
	members(in_0,in_1);
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}*/
	pin(in_0){
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin(in_1){
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (sel) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "(!sel & in_0) \| (sel & in_1)";
	max_fanout : 10;
	timing () {
	related_pin : "in_0";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "in_1";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "sel";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}


	cell(mux_4T) {
	- area : 1288;
	+ area : 3472;
	cell_footprint : mux_4T;
	/* cell_description : "NEM 4T 2-Input MUX"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	/*bundle(in) {
	members(in_0,in_1);
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}*/
	pin(in_0){
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin(in_1){
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (sel) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "(!sel & in_0) \| (sel & in_1)";
	max_fanout : 10;
	timing () {
	related_pin : "in_0";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "in_1";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "sel";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}
	cell(and_4T) {
	area : 1288;
	cell_footprint : and_4T;
	/* cell_description : "NEM 4T 2-Input AND based on muxiplayers pass logic"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "a&b";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(nand_4T) {
	area : 2448;
	cell_footprint : and_4T;
	/* cell_description : "NEM 4T 2-Input AND based on muxiplayers pass logic"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "!(a&b)";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(and_not_4T) {
	area : 1288;
	cell_footprint : and_4T;
	/* cell_description : "NEM 4T 2-Input AND based on muxiplayers pass logic having inverted input"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "a&!(b)";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(or_4T) {
	area : 1288;
	cell_footprint : or_4T;
	/* cell_description : "NEM 4T 2-Input OR based on muxiplayers pass logic"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "a\|b";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(nor_4T) {
	area : 2448;
	cell_footprint : or_4T;
	/* cell_description : "NEM 4T 2-Input NOR based on muxiplayers pass logic"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "a\|b";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}


	cell(or_not_4T) {
	area : 1288;
	cell_footprint : or_4T;
	/* cell_description : "NEM 4T 2-Input OR based on muxiplayers pass logic having inverted input"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "a\|!(b)";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(xor_4T) {
	area : 2448;
	cell_footprint : xor_3T;
	/* cell_description : "NEM 4T 2-Input XOR based on 2 4T and 3T inverter"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "a^b";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	cell(xnor_4T) {
	area : 2448;
	cell_footprint : xor_3T;
	/* cell_description : "NEM 4T 2-Input XNOR based on 2 4T and 3T inverter"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (a) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (b) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (out) {
	direction : "output";
	related_ground_pin : GND;
	related_power_pin : VCC;
	function : "!(a^b)";
	max_fanout : 10;
	timing () {
	related_pin : "a";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "b";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	}

	/*
	cell(SR_latch) {
	area : 2704;
	cell_footprint : SR_latch;
	cell_description : "NEM based S-R type Latch";
	pin (S) {
	direction : "input";
	}
	pin (R) {
	direction : "input";
	}
	pin (Q) {
	direction : "output";
	function : "IQ";
	}
	pin (Q_bar) {
	direction : "output";
	function : "IQB";
	}
	latch (IQ,IQB) {
	preset : "S"
	clear : "R"
	clear_preset_var1 : L;
	clear_preset_var2 : L;
	}
	statetable (" R S ", " IQ IQB "){
	table : "H L : - - : L H ,\
	L H : - - : H L ,\
	H H : - - : L L ,\
	L L : - - : N N";
	}
	}
	*/

	cell(D_latch) {
	area : 9448;
	cell_footprint : D_latch;
	/* cell_description : "NEM based D type Latch"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	/* data_in_type : data;*/
	/*
	timing() {
	related_pin : "EN";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing() {
	related_pin : "EN";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	*/
	}
	pin (EN) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	/*
	timing () {
	related_pin : "D";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "EN";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	*/
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	/*
	timing () {
	related_pin : "D";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "EN";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	*/
	}
	latch (QOUT,QBOUT) {
	enable : "EN";
	data_in : "D";
	}
	}


	cell(D_latch_rst) {
	area : 13432;
	cell_footprint : D_latch_rst;
	/* cell_description : "NEM based D type Latch with reset"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	/* data_in_type : data;*/
	}
	pin (EN) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (rst) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "D";
	timing_sense : positive_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "EN";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4darkblue.0","0.21,4.1");
	}
	}
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "D";
	timing_sense : negative_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	timing () {
	related_pin : "EN";
	timing_sense : non_unate;
	timing_type : combinational;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	latch (QOUT,QBOUT) {
	enable : "EN";
	data_in : "D";
	clear : "rst";
	}
	}

	cell(D_FF) {
	area : 20056;
	cell_footprint : D_FF;
	/* cell_description : "NEM based M-S D type Flip Flop"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	nextstate_type : data;
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	max_transition : 0.2;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	}
	pin (CLK) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	ff (QOUT,QBOUT) {
	clocked_on : "CLK";
	next_state : "D";
	}
	}

	cell(D_FF_rst) {
	area : 28184;
	cell_footprint : D_FF_rst;
	/* cell_description : "NEM based M-S D type Flip Flop with reset"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	nextstate_type : data;
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	max_transition : 0.2;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,-4.0","0.21,4.1");
	}
	}
	}
	pin (rst) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : recovery_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : removal_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	}
	}
	pin (CLK) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	ff (QOUT,QBOUT) {
	clear : "rst";
	clocked_on : "CLK";
	next_state : "D";
	}
	}

	/* SCAN FUNCTIONALITY HASN'T BEEN ADDED YET */
	cell(S_FF) {
	area : 20056;
	cell_footprint : D_FF;
	/* cell_description : "NEM based M-S D type Flip Flop with scan functionality";*/
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	nextstate_type : data;
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	max_transition : 0.2;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	}
	pin (SI) {
	nextstate_type : data;
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	max_transition : 0.2;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	}
	pin (CLK) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	ff (QOUT,QBOUT) {
	clocked_on : "CLK";
	next_state : "D";
	}
	}

	/* SCAN FUNCTIONALITY HASN'T BEEN ADDED YET */
	cell(S_FF_rst) {
	area : 28184;
	cell_footprint : S_FF_rst;
	/* cell_description : "NEM based M-S D type Flip Flop with reset and scan functionality"; */
	pg_pin (VCC) {
	pg_type : primary_power;
	voltage_name : "VCC";
	}
	pg_pin (GND) {
	pg_type : primary_ground;
	voltage_name : "GND";
	}
	pin (D) {
	nextstate_type : data;
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	max_transition : 0.2;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : hold_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","-0.21,4.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : setup_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,-4.0","0.21,4.1");
	}
	}
	}
	pin (rst) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_type : recovery_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("-0.2,-2.0","-0.21,-2.1");
	}
	}
	timing () {
	related_pin : "CLK";
	timing_type : removal_rising;
	rise_constraint (constraint_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	}
	}
	pin (CLK) {
	direction : "input";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	}
	pin (Q) {
	direction : "output";
	function : "QOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	pin (Q_bar) {
	direction : "output";
	function : "QBOUT";
	related_ground_pin : GND;
	related_power_pin : VCC;
	capacitance : 1;
	timing () {
	related_pin : "CLK";
	timing_sense : non_unate;
	timing_type : rising_edge;
	cell_rise (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	rise_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	cell_fall (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,2.0","0.21,2.1");
	}
	fall_transition (delay_template_2x2) {
	index_1 ("0.01,0.1");
	index_2 ("0.02,0.2");
	values ("0.2,4.0","0.21,4.1");
	}
	}
	}
	ff (QOUT,QBOUT) {
	clear : "rst";
	clocked_on : "CLK";
	next_state : "D";
	}
	}
	}
	diff --git a/run.sh b/run.sh
	index a2f090f..44ff4cd 100755
	--- a/run.sh
	+++ b/run.sh
	@@ -1,381 +1,406 @@
	#!/bin/bash

	FILE=""
	FILE_BASENAME=""
	MODULE=""
	LIBERTY_FILE="nem_basic_yosys.lib"
	LIBERTY_USED="3T"
	visualize=0

	# Function to display the menu and get user input
	show_menu() {


	# Define color codes
	GREEN='\033[0;32m'
	YELLOW='\033[1;33m'
	CYAN='\033[0;36m'
	RESET='\033[0m'

	echo "--------------------------------------------------------------"
	echo -e "${CYAN}Current file: $FILE with module: $MODULE${RESET}"
	echo -e "${YELLOW}Please select your options (you can choose multiple options):${RESET}"
	echo
	- echo -e "${GREEN}1)${RESET} Synthesize to NEM technology"
	- echo -e "${GREEN}2)${RESET} Print initial design"
	- echo -e "${GREEN}3)${RESET} Print out NEM optimized design"
	- echo -e "${GREEN}4)${RESET} Perform SAT comparison"
	- echo -e "${GREEN}5)${RESET} Export FSM as KISS2 format"
	- echo -e "${GREEN}6)${RESET} Start shell with modules"
	- echo -e "${GREEN}7)${RESET} Switch from normal 3T gate library to new 4T"
	- echo -e "${GREEN}8)${RESET} Run series of test and create comparison report"
	- echo -e "${GREEN}9)${RESET} Perform MUXIG synthesis run"
	- echo -e "${GREEN}10)${RESET} export truth table and MIG run"
	+ echo -e "${GREEN}1)${RESET} Synthesize to NEM technology with normal Yosys AIG flow"
	+ echo -e "${GREEN}2)${RESET} Synthesize to NEM and perform MUXIG optimisaiton run"
	+ echo -e "${GREEN}3)${RESET} Synthesize to NEM and perform MIG optimisation run"
	+ echo -e "${GREEN}4)${RESET} Print initial design"
	+ echo -e "${GREEN}5)${RESET} Print out NEM optimized design"
	+ echo -e "${GREEN}6)${RESET} Perform SAT comparison"
	+ echo -e "${GREEN}7)${RESET} Export FSM as KISS2 format"
	+ echo -e "${GREEN}8)${RESET} Start shell with modules"
	+ echo -e "${GREEN}9)${RESET} Switch from normal 3T gate library to new 4T"
	+ echo -e "${GREEN}10)${RESET} Run series of test and create comparison report"
	echo -e "${GREEN}11)${RESET} Select a new Verilog file"
	echo -e "${GREEN}0)${RESET} Exit the program"
	echo "--------------------------------------------------------------"
	}

	# Request the file to process
	request_data(){
	echo "-:- Enter the file to map to NEM"
	read -e -p "What is the file name?: " FILE
	read -p "What is the name of the top module? (press ENTER for the same as the file name): " MODULE

	if [ ! -f "$FILE" ]; then
	echo "File not found"
	request_data
	fi

	FILE_BASENAME=$(basename "$FILE" \| cut -d. -f1)
	#echo $FILE_BASENAME

	if [ -z "$MODULE" ]; then
	#echo "setting name equal to that of the file"
	MODULE=$FILE_BASENAME
	fi
	}

	#run a yosys file specified to the function
	run_yosys_file() {
	local yosys_file="$1"
	local depth="$2"
	local additional_yosys_args="$3"

	# Start with basic sed commands
	sed_command=$(sed -e "s\|{{FILE}}\|$FILE\|g" \
	-e "s\|{{FILE_BASENAME}}\|$FILE_BASENAME\|g" \
	-e "s\|{{MODULE}}\|$MODULE\|g" \
	-e "s\|{{LIBERTY_FILE}}\|$LIBERTY_FILE\|g" \
	-e "s\|{{LIBERTY_USED}}\|$LIBERTY_USED\|g"\
	"./yosys/${yosys_file}.ys")

	# Apply additional sed expressions based on DEPTH value
	if [[ $depth -eq 0 ]]; then
	sed_command=$(echo "$sed_command" \| sed -e "/#IF {{DEPTH}}==0/d" \
	-e "/#ELSE/,/#END/d")
	elif [[ $depth -eq 1 ]]; then
	sed_command=$(echo "$sed_command" \| sed -e "/#IF {{DEPTH}}==0/,/#ELSE/d" \
	-e "/#END/d")
	fi

	# Write the result to a temp file and run yosys
	echo "$sed_command" > "./temp/${yosys_file}_temp.ys"
	yosys $additional_yosys_args "./temp/${yosys_file}_temp.ys"
	}

	#Switch between 3T and 4T pass through gates
	switch_liberty() {
	local override="$1"
	if [[ ("$LIBERTY_FILE" == "nem_basic_yosys.lib" && "$override" != "3T") \|\| "$override" == "4T" ]]; then
	LIBERTY_FILE="nem_basic_yosys_extended.lib"
	LIBERTY_USED="4T"
	echo "Now using extended (4T devices) library"
	elif [[ "$LIBERTY_FILE" == "nem_basic_yosys_extended.lib" \|\| "$override" == "3T" ]]; then
	LIBERTY_FILE="nem_basic_yosys.lib"
	LIBERTY_USED="3T"
	echo "Now using normal library"
	else
	echo "Unknown LIBERTY_FILE value: $LIBERTY_FILE"
	fi
	}

	compare_area() {
	# Extract area values from .stat files
	local area_3T=$(grep "Chip area for module" "./temp/${FILE_BASENAME}_3T.stat" \| awk '{print $6}')
	local area_4T=$(grep "Chip area for module" "./temp/${FILE_BASENAME}_4T.stat" \| awk '{print $6}')
	local area_MUX=$(grep "Chip area for module" "./temp/${FILE_BASENAME}_MUX.stat" \| awk '{print $6}')

	# Calculate ratio as (area_3T / area_4T) * 100
	local ratio_4T=$(echo "($area_4T / $area_3T)" \| bc -l)
	local ratio_MUX=$(echo "($area_MUX / $area_3T)" \| bc -l)

	{
	echo "------------- normal 3T ---------------"
	cat "./temp/${FILE_BASENAME}_3T.stat"
	echo "------------- 4T ---------------"
	cat "./temp/${FILE_BASENAME}_4T.stat"
	echo "------------- Muxig ---------------"
	cat "./temp/${FILE_BASENAME}_MUX.stat"
	echo "------------- Stats ---------------"
	echo "Area 3T: $area_3T"
	echo "Area 4T: $area_4T"
	echo "Ratio 4T->3T: $ratio_4T%"
	echo "Area MUX: $area_MUX"
	echo "Ratio MUX->3T: $ratio_MUX%"
	} > "./output/${FILE_BASENAME}.ratio"

	# Output the areas and the ratio
	echo "Area 3T: $area_3T, Area 4T: $area_4T, Ratio 4T->3T: $ratio_4T, Area MUX: $area_MUX, Ratio MUX->3T: $ratio_MUX%"
	}

	create_report() {

	-# Output CSV file name
	-csv_output="./output/output_report.csv"
	-
	-# Clear the CSV file by redirecting an empty string to it
	-> "$csv_output"
	-
	-# Write the CSV header
	-echo "Module,3T,4T,Ratio 4T,Mux,Ratio Mux" > "$csv_output"
	-# Print the header of the table
	-printf "%-20s %-20s %-20s %-20s %-20s %-20s\n" "Module" "3T" "4T" "Ratio 4T" "MUX" "Ratio MUx"
	-printf "%-20s %-20s %-20s %-20s %-20s %-20s\n" "-------" "------" "------" "-----" "-----" "-----"
	-
	-# Loop through each .ratio file in the directory
	-for file in ./output/*.ratio; do
	- # Check if the file exists
	- if [[ -f "$file" ]]; then
	- # Extract the module name
	- module_name=$(grep -m 1 -oP '(?<==== ).*(?= ===)' "$file") # Extract the module name
	-
	- # Extract areas using grep and sed
	- area1=$(grep "Chip area for module" "$file" \| sed -n '1s/.*: //p') # Area 3T
	- area2=$(grep "Chip area for module" "$file" \| sed -n '2s/.*: //p') # Area 4T
	- area3=$(grep "Chip area for module" "$file" \| sed -n '3s/.*: //p') # Area MUX
	-
	- # Extract the ratio
	- ratio_4T=$(grep -oP '(?<=Ratio 4T->3T: )[\d.]+' "$file") # Extract the ratio
	- ratio_MUX=$(grep -oP '(?<=Ratio MUX->3T: )[\d.]+' "$file") # Extract the ratio
	- ratio_4T=$(printf "%.5f" "$ratio_4T")
	- ratio_MUX=$(printf "%.5f" "$ratio_MUX")
	-
	- # Append the data to the CSV file
	- echo "$module_name,$area1,$area2,$ratio_4T,$area3,$ratio_MUX" >> "$csv_output"
	-
	- # Print the results in the table format
	- printf "%-20s %-20s %-20s %-20s %-20s %-20s\n" "$module_name" "$area1" "$area2" "$ratio_4T" "$area3" "$ratio_MUX"
	- fi
	-done
	+ # Output CSV file name
	+ csv_output="./output/output_report.csv"
	+
	+ # Clear the CSV file by redirecting an empty string to it
	+ > "$csv_output"
	+
	+ # Write the CSV header
	+ echo "Module,3T,Mux,Ratio Mux,and_3T,nand_3T,or_3T,nor_3T,xor_3T,xnor_3T,inv_3T,mux_3T,muxig_inv_3T,mux_4T,device_count_3T,device_count_muxig,ratio" > "$csv_output"
	+
	+ # Print the header of the table
	+ printf "%-20s %-20s %-20s %-20s %-20s %-20s\n" "Module" "3T" "4T" "Ratio 4T" "MUX" "Ratio MUX"
	+ printf "%-20s %-20s %-20s %-20s %-20s %-20s\n" "-------" "------" "------" "-------" "-----" "----------"
	+
	+ # Loop through each .ratio file in the directory
	+ for file in ./output/*.ratio; do
	+ # Check if the file exists
	+ if [[ -f "$file" ]]; then
	+ # Extract the module name
	+ module_name=$(grep -m 1 -oP '(?<==== ).*(?= ===)' "$file") # Extract the module name
	+
	+ # Extract areas using grep and sed
	+ area1=$(grep "Chip area for module" "$file" \| sed -n '1s/.*: //p') # Area 3T
	+ area3=$(grep "Chip area for module" "$file" \| sed -n '3s/.*: //p') # Area MUX
	+
	+ # Extract sections
	+ normal_3T_section=$(awk '/------------- normal 3T ---------------/,/------------- 4T ---------------/' "$file")
	+ muxig_section=$(awk '/------------- Muxig ---------------/,/------------- Stats ---------------/' "$file")
	+
	+ # Extract gate counts for "normal 3T"
	+ and_3T=$(echo "$normal_3T_section" \| awk '/ and_3T/ {print $2}' \|\| echo 0)
	+ nand_3T=$(echo "$normal_3T_section" \| awk '/ nand_3T/ {print $2}' \|\| echo 0)
	+ or_3T=$(echo "$normal_3T_section" \| awk '/ or_3T/ {print $2}' \|\| echo 0)
	+ nor_3T=$(echo "$normal_3T_section" \| awk '/ nor_3T/ {print $2}' \|\| echo 0)
	+ xor_3T=$(echo "$normal_3T_section" \| awk '/ xor_3T/ {print $2}' \|\| echo 0)
	+ xnor_3T=$(echo "$normal_3T_section" \| awk '/ xnor_3T/ {print $2}' \|\| echo 0)
	+ inv_3T=$(echo "$normal_3T_section" \| awk '/ inv_3T/ {print $2}' \|\| echo 0)
	+ mux_3T=$(echo "$normal_3T_section" \| awk '/ mux_3T/ {print $2}' \|\| echo 0)
	+
	+ # Extract gate counts for "Muxig"
	+ muxig_inv_3T=$(echo "$muxig_section" \| awk '/ inv_3T/ {print $2}' \|\| echo 0)
	+ mux_4T=$(echo "$muxig_section" \| awk '/ mux_4T/ {print $2}' \|\| echo 0)
	+
	+ # Calculate device counts
	+ device_count_3T=$((and_3T * 6 + nand_3T * 4 + or_3T * 6 + nor_3T * 4 + xor_3T * 12 + xnor_3T * 12 + mux_3T * 12 + inv_3T * 2))
	+ device_count_muxig=$((muxig_inv_3T * 2 + mux_4T * 2))
	+
	+ # Extract the ratio
	+ ratio_4T=$(grep -oP '(?<=Ratio 4T->3T: )[\d.]+' "$file" \|\| echo 0) # Extract the ratio
	+ ratio_MUX=$(grep -oP '(?<=Ratio MUX->3T: )[\d.]+' "$file" \|\| echo 0) # Extract the ratio
	+ ratio_4T=$(printf "%.5f" "$ratio_4T")
	+ ratio_MUX=$(printf "%.5f" "$ratio_MUX")
	+
	+ ratio_device_count=$(echo "($device_count_muxig / $device_count_3T)" \| bc -l)
	+
	+ # Append the data to the CSV file
	+ echo "$module_name,$area1,$area3,$ratio_MUX,$and_3T,$nand_3T,$or_3T,$nor_3T,$xor_3T,$xnor_3T,$inv_3T,$mux_3T,$muxig_inv_3T,$mux_4T,$device_count_3T,$device_count_muxig,$ratio_device_count" >> "$csv_output"
	+
	+ # Print the results in the table format
	+ printf "%-20s %-20s %-20s %-20s %-20s %-20s\n" "$module_name" "$area1" "$area3" "$ratio_4T" "$area3" "$ratio_MUX"
	+ fi
	+ done
	}


	+
	#START ACTUAL EXECUTION

	#Check if in menu mode or in CLI mode
	if [ -z "$1" ]; then
	# in menu mode
	request_data
	else

	#in cli mode. Filter through all the parameters
	while getopts ":d:f:m:v:x:r:" opt; do
	case $opt in
	d) # -d option for directory
	file_directory="$OPTARG"
	;;
	f) # -f option for file
	FILE="$OPTARG"
	;;
	m) # -m option for module (requires -f to be set)
	MODULE="$OPTARG"
	;;
	v) # -v visualize before and after synthesis
	echo "found visualize"
	visualize=1
	;;
	x) # -x switch to extended nem liberty file
	echo "switching to 4T libert file"
	switch_liberty
	;;
	r) # -r generate report of output
	echo "generating report"
	create_report
	;;
	\?) # Invalid option
	echo "Invalid option: -$OPTARG" >&2
	usage
	;;
	:) # Missing argument for an option
	echo "Option -$OPTARG requires an argument." >&2
	usage
	;;
	esac
	done

	#running synthesis on al lthe files in the directory
	if [ -n "$file_directory" ]; then
	if [ -d "$file_directory" ]; then
	echo "Directory exists: $file_directory"

	for file in "$file_directory"/*.v; do
	# Check if it's a regular file
	if [ -f "$file" ]; then
	# Use grep to find the line that starts with 'module' and extract the module name
	module_name=$(grep -m 1 -oP '^module\s+\K\w+' "$file")

	# If the module name is found, print the file path and the module name
	if [ -n "$module_name" ]; then
	echo "File: $file"
	echo "Module: $module_name"
	echo

	FILE=$file
	FILE_BASENAME=$(basename "$FILE" \| cut -d. -f1)
	MODULE=$module_name
	-
	+ MODULE=$FILE_BASENAME
	#synthesise the file
	echo "running sequence of test commands"
	switch_liberty "3T"
	run_yosys_file "synth_nem" 0
	- run_yosys_file "sat_test" 0
	+ #run_yosys_file "sat_test" 0
	switch_liberty "4T"
	run_yosys_file "synth_nem" 0
	- run_yosys_file "sat_test" 0
	+ #run_yosys_file "sat_test" 0
	switch_liberty "4T"
	run_yosys_file "bruteforce" 0
	switch_liberty "3T"
	compare_area

	else
	echo "No module found in file: $file"
	echo
	fi
	fi
	done

	#done with synthesis
	create_report
	exit 0

	else
	echo "Directory does not exist: $file_directory"
	exit 1
	fi
	fi

	#running synthesis on the file requested
	if [ -n "$FILE" ]; then
	if [ -n "$MODULE" ]; then
	if [ -f "$FILE" ]; then
	echo "File exists: $file"
	echo "Module: $module"
	FILE_BASENAME=$(basename "$FILE" \| cut -d. -f1)
	run_yosys_file "synth_nem" 0
	if [ "$visualize" -eq 1 ]; then
	run_yosys_file "visual" 0
	run_yosys_file "visual" 1
	else
	echo "no visualize set"
	fi
	+ compare_area
	+ create_report
	exit 0
	else
	echo "File does not exist: $file"
	exit 1
	fi
	else
	echo "Missing module (-m) for the file (-f)."
	- usage
	fi
	fi
	exit 1

	fi


	# Loop to allow multiple selections
	while true; do
	show_menu
	read -p "Enter your choices (e.g., 1 2 3, or 0 to finish): " -a choices

	for choice in "${choices[@]}"; do
	case $choice in
	1)
	- echo "performing synthesis"
	+ echo "performing synthesis with normal Yosys flow"
	run_yosys_file "synth_nem" 0
	;;
	2)
	+ echo "exporting BLIf and running in mockturtle for muxig"
	+ run_yosys_file "bruteforce" 0
	+ ;;
	+ 3)
	+ echo "exporting BLIF and running in mockturtle for MIG"
	+ run_yosys_file "bruteforce" 1
	+ ;;
	+ 4)
	echo "Plotting the initial design with $FILE and $MODULE"
	run_yosys_file "visual" 0
	;;
	- 3)
	+ 5)
	echo "Plotting the NEM design with $FILE and $MODULE"
	run_yosys_file "visual" 1
	;;
	- 4)
	+ 6)
	echo "Performing SAT test on $FILE and $MODULE"
	run_yosys_file "sat_test" 0
	;;
	- 5)
	+ 7)
	echo "Exporting FSM overview of the design"
	make clean #to make sure no previous .kiss2 file remains
	run_yosys_file "fsm_export" 0

	if [ -f "./temp/${FILE_BASENAME}.kiss2" ]; then
	# If the file exists, run the python script and xdot
	python3 ./yosys/kiss2dot.py ./temp/${FILE_BASENAME}.kiss2 > ./temp/${FILE_BASENAME}.dot
	xdot ./temp/${FILE_BASENAME}.dot
	else
	# If the file doesn't exist, print a message
	echo "Could not detect an FSM in ${MODULE}"
	fi
	;;
	- 6)
	+ 8)
	echo "Plotting the initial design with $FILE and $MODULE"
	make clean #Clean directories
	run_yosys_file "synth_nem" 0
	make all #build plugins
	ls ./plugins/*.so
	run_yosys_file "start_shell" 0 "$(for so_file in ./plugins/*.so; do echo -m "$so_file"; done)" #create a list of all plugins to load
	;;
	- 7)
	+ 9)
	echo "Switching libary"
	switch_liberty
	;;
	- 8)
	+ 10)
	echo "running sequence of test commands"
	switch_liberty "3T"
	run_yosys_file "synth_nem" 0
	#run_yosys_file "visual" 1
	switch_liberty "4T"
	run_yosys_file "synth_nem" 0
	#run_yosys_file "visual" 1
	run_yosys_file "bruteforce" 0
	compare_area
	-
	- ;;
	- 9)
	- echo "exporting truth table and running in mockturtle for muxig"
	- run_yosys_file "bruteforce" 0
	- ;;
	- 10)
	- echo "exporting truth table and running in mockturtle for MIG"
	- run_yosys_file "bruteforce" 1
	;;
	11)
	echo "requesting new module"
	request_data
	;;
	0)
	echo "exiting"
	break 2
	;;
	*)
	echo "Invalid choice. Please select a number between 1 and 6."
	;;
	esac
	done

	echo
	done
	diff --git a/sim_resubstitution.cpp b/sim_resubstitution.cpp
	deleted file mode 100644
	index 5a72ad7..0000000
	--- a/sim_resubstitution.cpp
	+++ /dev/null
	@@ -1,199 +0,0 @@
	-/* mockturtle: C++ logic network library
	- * Copyright (C) 2018-2022 EPFL
	- *
	- * Permission is hereby granted, free of charge, to any person
	- * obtaining a copy of this software and associated documentation
	- * files (the "Software"), to deal in the Software without
	- * restriction, including without limitation the rights to use,
	- * copy, modify, merge, publish, distribute, sublicense, and/or sell
	- * copies of the Software, and to permit persons to whom the
	- * Software is furnished to do so, subject to the following
	- * conditions:
	- *
	- * The above copyright notice and this permission notice shall be
	- * included in all copies or substantial portions of the Software.
	- *
	- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	- * OTHER DEALINGS IN THE SOFTWARE.
	- */
	-
	-
	-#include <cstdint>
	-#include <iostream>
	-
	-#include <lorina/blif.hpp>
	-#include <mockturtle/algorithms/cover_to_graph.hpp>
	-#include <mockturtle/io/write_dot.hpp>
	-#include <mockturtle/networks/cover.hpp>
	-#include <mockturtle/networks/muxig.hpp>
	-#include <mockturtle/utils/debugging_utils.hpp>
	-#include <mockturtle/views/fanout_view.hpp>
	-#include <string>
	-//#include <vector>
	-
	-#include <fmt/format.h>
	-#include <lorina/aiger.hpp>
	-#include <mockturtle/algorithms/cleanup.hpp>
	-#include <mockturtle/algorithms/sim_resub.hpp>
	-#include <mockturtle/io/blif_reader.hpp>
	-#include <mockturtle/io/write_blif.hpp>
	-#include <mockturtle/networks/aig.hpp>
	-
	-#include <experiments.hpp>
	-#include <vector>
	-
	-int main( int argc, char* argv[] )
	-{
	- if ( argc != 2 )
	- {
	- std::cout << "Received " << argc << "\n";
	- std::cout << "[e] Please give exactly one argument, which is a AIG file to be processed\n";
	- std::cout << " For example: ./sim_resubstition test.aig\n";
	- return -1;
	- }
	-
	- using namespace experiments;
	- using namespace mockturtle;
	-
	- experiment<std::string, uint32_t, uint32_t, float> exp( "sim_resubstitution", "benchmark", "size", "gain", "runtime");
	-
	- std::string benchmark( argv[1] );
	- std::string filename_trimed;
	-
	- fmt::print( "[i] processing {}\n", benchmark );
	- muxig_network muxig;
	- cover_network temp;
	-
	-
	- if ( benchmark.size() > 5 && benchmark.substr( benchmark.size() - 5, 5 ) == ".blif" )
	- {
	- filename_trimed = benchmark.substr( 0, benchmark.size() - 5 );
	-
	- std::cout << "received: " << benchmark << "\n";
	-
	- if ( lorina::read_blif( benchmark, blif_reader( temp ) ) != lorina::return_code::success )
	- {
	- std::cout << "Error in reading file\n";
	- return 1;
	- }
	- } else
	- {
	- std::cout << "received: " << benchmark << "\n";
	- std::cout << "[e] Argument does not end with .aig\n";
	- std::cout << "[i] Usage: ./muxig_rewriting_with_resynthesis [AIGER or Verilog filename]\n";
	- return -1;
	- }
	- muxig = convert_cover_to_graph<muxig_network>(temp);
	-
	- resubstitution_params ps;
	- resubstitution_stats st;
	- mockturtle::write_blif(muxig, filename_trimed + "_direct_conversion.blif");
	-
	- //mockturtle::print(muxig);
	-
	- //ps.pattern_filename = "1024sa1/" + benchmark + ".pat";
	- ps.max_inserts = 20;
	- ps.max_pis = 10;
	- ps.progress = true;
	- ps.verbose = true;
	-
	- ps.max_divisors = std::numeric_limits<uint32_t>::max();
	-
	- const uint32_t size_before = muxig.num_gates();
	- sim_resubstitution( muxig, ps, &st );
	- //mockturtle::print(muxig);
	- muxig = cleanup_dangling( muxig );
	-
	- fanout_view fnntk(muxig);
	-
	- muxig.foreach_node( [&]( auto node ) {
	- if(muxig.is_mux(node) && (muxig.fanin_size(node)==3)){
	- std::cout << "running normalization on node " << node << "\n";
	- muxig_network::normalization_result results = muxig.normalized_fanins(muxig._storage->nodes[node].children[0],muxig._storage->nodes[node].children[1],muxig._storage->nodes[node].children[2]);
	- }});
	-
	-
	- muxig.foreach_node( [&]( auto node ) {
	- if(muxig.is_mux(node) && (muxig.fanin_size(node)==3)){
	- uint32_t inv = muxig.fanout_size(node);
	- std::cout << "now in node " << node << " with fanout size " << inv << "\n";
	-
	- std::vector<std::pair<uint32_t, uint32_t>> fanout_stack;
	-
	- fnntk.foreach_fanout(node, [&]( auto fan_out ){
	- std::cout << "Currently in fanout " << fan_out << "\n";
	- int i = 0;
	- muxig.foreach_fanin(fan_out, [&]( auto signal ) {
	-
	- if(muxig.get_node(signal)==node){
	- if(signal.complement){
	- inv--;
	- }
	- fanout_stack.emplace_back(fan_out,i);
	- }
	-
	- i++;
	-
	- });
	- });
	-
	- muxig.foreach_po([&]( auto po ){
	- if(muxig.get_node(po)==node && muxig.is_complemented(po)){
	- inv--;
	- }
	- });
	-
	- if(inv == 0 && muxig.fanout_size(node) != 0){
	- std::cout << "Found complemented output, will normalize\n";
	- if(muxig._storage->nodes[node].children[1] == 0 && muxig.is_complemented(muxig._storage->nodes[node].children[1]) == 0 && muxig._storage->nodes[node].children[2] != 0){
	- std::cout << "switching ANDNOT to ORNOT internal\n";
	- std::swap(muxig._storage->nodes[node].children[0],muxig._storage->nodes[node].children[2]);
	- std::swap(muxig._storage->nodes[node].children[1],muxig._storage->nodes[node].children[2]);
	- muxig._storage->nodes[node].children[2] = muxig.get_constant(true);
	- for (const auto& [node, child] : fanout_stack) {
	- muxig._storage->nodes[node].children[child] = muxig.create_not(muxig._storage->nodes[node].children[child]);
	- }
	- } else if(muxig._storage->nodes[node].children[2] == 0 && muxig.is_complemented(muxig._storage->nodes[node].children[2]) == 1 && muxig._storage->nodes[node].children[1] != 0){
	- std::cout << "switching ORNOT to ANDNOT internal\n";
	- std::swap(muxig._storage->nodes[node].children[0],muxig._storage->nodes[node].children[1]);
	- std::swap(muxig._storage->nodes[node].children[1],muxig._storage->nodes[node].children[2]);
	- muxig._storage->nodes[node].children[1] = muxig.get_constant(false);
	- for (const auto& [node, child] : fanout_stack) {
	- muxig._storage->nodes[node].children[child] = muxig.create_not(muxig._storage->nodes[node].children[child]);
	- }
	- }/*else if(muxig._storage->nodes[node].children[2] == 0 && muxig.is_complemented(muxig._storage->nodes[node].children[2]) == 0 && muxig._storage->nodes[node].children[1] != 0){
	- std::cout << "switching test to ANDNOT internal\n";
	- std::swap(muxig._storage->nodes[node].children[0],muxig._storage->nodes[node].children[1]);
	- std::swap(muxig._storage->nodes[node].children[1],muxig._storage->nodes[node].children[2]);
	- muxig._storage->nodes[node].children[1] = muxig.get_constant(true);
	- for (const auto& [node, child] : fanout_stack) {
	- muxig._storage->nodes[node].children[child] = muxig.create_not(muxig._storage->nodes[node].children[child]);
	- }
	- for(uint i = 0; i<muxig.num_pos(); i++){
	- if(muxig.get_node(muxig._storage->outputs[i])==node && muxig.is_complemented(muxig._storage->outputs[i])){
	- muxig._storage->outputs[i] = muxig.create_not(muxig._storage->outputs[i]);
	- }
	- }
	- }*/
	-
	- //std::swap(,muxig._storage->nodes[node].children[1]);
	- //muxig.normalized_fanout(muxig._storage->nodes[node].children[0],muxig._storage->nodes[node].children[1],muxig._storage->nodes[node].children[2]);
	- }
	- }});
	-
	-
	- //mockturtle::print(muxig);
	- mockturtle::write_blif(muxig, filename_trimed + "_mockturtle.blif");
	- mockturtle::write_dot(muxig,filename_trimed + "_mockturtle.dot");
	- exp( benchmark, size_before, size_before - muxig.num_gates(), to_seconds( st.time_total ));
	- exp.save();
	- exp.table();
	-
	- return 0;
	-}
	\ No newline at end of file
	diff --git a/sources/test_set/alu.v b/sources/test_set/alu.v
	new file mode 100644
	index 0000000..681fb4d
	--- /dev/null
	+++ b/sources/test_set/alu.v
	@@ -0,0 +1,51 @@
	+module alu8(
	+ input clk,
	+ input rst,
	+ input a,
	+ input b,
	+ input [2:0] opcode, // 000: add, 001: sub, 010: and, 011: or, 100: xor
	+ output reg result
	+);
	+
	+ reg stage1_a, stage1_b;
	+ reg [2:0] stage1_opcode;
	+ reg stage2_result;
	+
	+ // Stage 1: Register Inputs
	+ always @(posedge clk) begin
	+ if (rst) begin
	+ stage1_a <= 0;
	+ stage1_b <= 0;
	+ stage1_opcode <= 0;
	+ end else begin
	+ stage1_a <= a;
	+ stage1_b <= b;
	+ stage1_opcode <= opcode;
	+ end
	+ end
	+
	+ // Stage 2: ALU Operations
	+ always @(posedge clk) begin
	+ if (rst) begin
	+ stage2_result <= 0;
	+ end else begin
	+ case (stage1_opcode)
	+ 3'b000: stage2_result <= stage1_a + stage1_b; // Add
	+ 3'b001: stage2_result <= stage1_a - stage1_b; // Subtract
	+ 3'b010: stage2_result <= stage1_a & stage1_b; // AND
	+ 3'b011: stage2_result <= stage1_a \| stage1_b; // OR
	+ 3'b100: stage2_result <= stage1_a ^ stage1_b; // XOR
	+ default: stage2_result <= 0;
	+ endcase
	+ end
	+ end
	+
	+ // Stage 3: Output
	+ always @(posedge clk) begin
	+ if (rst) begin
	+ result <= 0;
	+ end else begin
	+ result <= stage2_result;
	+ end
	+ end
	+endmodule
	diff --git a/sources/test_set/mux_test.v b/sources/test_set/mux_test.v
	new file mode 100644
	index 0000000..5bf9810
	--- /dev/null
	+++ b/sources/test_set/mux_test.v
	@@ -0,0 +1,10 @@
	+module mux_test (A, B, S, Y);
	+
	+input A;
	+input B;
	+input S;
	+
	+output Y;
	+
	+assign Y = S ? B : A;
	+endmodule
	diff --git a/sources/test_set/xor_and.v b/sources/test_set/xor_and.v
	index 0a09ab0..de31bbe 100644
	--- a/sources/test_set/xor_and.v
	+++ b/sources/test_set/xor_and.v
	@@ -1,8 +1,11 @@
	module xor_and (
	input A, B, C,
	output Y
	);
	wire X;
	+ wire N;
	assign X = (A & ~B) \| (~A & B);
	- assign Y = X & C;
	+ assign N = (C & ~X) \| (~C & X);
	+ assign Y = ~N;
	+
	endmodule
	diff --git a/yosys/bruteforce.ys b/yosys/bruteforce.ys
	index 9e50cb9..50bf192 100644
	--- a/yosys/bruteforce.ys
	+++ b/yosys/bruteforce.ys
	@@ -1,38 +1,52 @@
	read_verilog {{FILE}}

	#map to basic cells
	proc;;
	techmap;;
	opt;;
	-aigmap;;
	-
	splitnets;;
	+
	+#If required export some images
	#show -prefix ./temp/{{MODULE}}_bruteforce_aig_{{LIBERTY_USED}} -color orange t:$_NOT_ -color darkred t:$_AND_ -color purple t:$ge -color darkblue t:$ne -color blue t:$le -color maroon t:$add -enum


	write_blif ./temp/{{FILE_BASENAME}}.blif

	+abc -exe ./abc/abc -script "+source ./abc.rc;compress2rs"
	+
	+#if you want to do whole design at once.
	#exec -- ./abc/abc -c "read_blif ./temp/{{FILE_BASENAME}}.blif; compress2rs; write_blif ./temp/{{FILE_BASENAME}}_abc.blif"
	+
	+#if required export equation and truth table"
	#abc -liberty ./nem_liberty/{{LIBERTY_FILE}} -script "+strash; &get -n; collapse; write_eqn ./temp/{{FILE_BASENAME}}.eqn; &write_truths -x ./temp/{{FILE_BASENAME}}.truth"
	delete

	-exec -- ./mockturtle/debug/experiments/sim_resubstitution ./temp/{{FILE_BASENAME}}.blif
	-exec -- python3 ./yosys/map_ports.py ./temp/{{FILE_BASENAME}}.blif ./temp/{{FILE_BASENAME}}_mockturtle.blif
	+#Perform mockturtle muxig conversion
	+exec -- ./mockturtle_binaries/sim_resubstitution ./temp/{{FILE_BASENAME}}.blif

	+#Map the exported design back to yosys format to help with SAT mitters test.
	+exec -- python3 ./yosys/map_ports.py ./temp/{{FILE_BASENAME}}.blif ./temp/{{FILE_BASENAME}}_mockturtle.blif

	+#read back into Yosys
	read_blif ./temp/mapped_{{FILE_BASENAME}}_mockturtle.blif
	+
	+
	rename top {{MODULE}}_nem

	+#map the exported blif format back to Yosys basic cells
	techmap -map ./yosys/mockturtle_map.v
	techmap
	+
	+#Mockturtle creates constant 1 by taking a constant 0 and inverting it. opt_expr changes these to a constant 1 to avoid this inverter.
	opt_expr

	+
	clean -purge

	abc -liberty ./nem_liberty/{{LIBERTY_FILE}} -script "+attach"

	clean -purge

	write_verilog -selected ./temp/{{FILE_BASENAME}}_nem.v
	#Output stats
	tee -o ./temp/{{FILE_BASENAME}}_MUX.stat stat -liberty ./nem_liberty/{{LIBERTY_FILE}}

File Metadata

Mime Type: text/x-diff
Expires: Mon, Nov 10, 7:56 AM (16 h, 32 m)
Storage Engine: blob
Storage Format: Raw Data
Storage Handle: 235609
Default Alt Text: (388 KB)

No OneTemporaryActions

View Options

File Metadata

Event Timeline

No OneTemporary
Actions