flipflop.v
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flipflop.v
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	module sum ( clk, A, B, sel, out);

	input wire clk;
	input wire A;
	input wire B;
	input wire sel;
	output reg signed out;

	always @(posedge clk) begin
	if (sel)
	out <= A;
	else begin
	out <= B;
	end
	end
	endmodule

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