alu8.v
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alu8.v
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	module alu8(
	input clk,
	input rst,
	input [7:0] a,
	input [7:0] b,
	input [2:0] opcode, // 000: add, 001: sub, 010: and, 011: or, 100: xor
	output reg [7:0] result
	);

	reg [7:0] stage1_a, stage1_b;
	reg [2:0] stage1_opcode;
	reg [7:0] stage2_result;

	// Stage 1: Register Inputs
	always @(posedge clk) begin
	if (rst) begin
	stage1_a <= 0;
	stage1_b <= 0;
	stage1_opcode <= 0;
	end else begin
	stage1_a <= a;
	stage1_b <= b;
	stage1_opcode <= opcode;
	end
	end

	// Stage 2: ALU Operations
	always @(posedge clk) begin
	if (rst) begin
	stage2_result <= 0;
	end else begin
	case (stage1_opcode)
	3'b000: stage2_result <= stage1_a + stage1_b; // Add
	3'b001: stage2_result <= stage1_a - stage1_b; // Subtract
	3'b010: stage2_result <= stage1_a & stage1_b; // AND
	3'b011: stage2_result <= stage1_a \| stage1_b; // OR
	3'b100: stage2_result <= stage1_a ^ stage1_b; // XOR
	default: stage2_result <= 0;
	endcase
	end
	end

	// Stage 3: Output
	always @(posedge clk) begin
	if (rst) begin
	result <= 0;
	end else begin
	result <= stage2_result;
	end
	end
	endmodule