counter10.v
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counter10.v
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	module counter ( clk, rst, cnt);

	input wire clk;
	input wire rst;
	output reg signed[9:0] cnt;

	always @(posedge clk) begin
	if (rst)
	cnt <= 10'sd0;
	else begin
	cnt <= cnt + 10'sd1;
	end
	end
	endmodule

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