This utility was written to use yosys to synthesize from verilog to a netlist existing out of all standard cells available in the current library of NEM cells. It only uses the freely available yosys oss suite. No license required
# 2. data structure
The application is ordered as follows:
```
\bruteforce_approach\: contains all the c script's and a python script to run bruteforce approach on very small functions
\sources\ : All the verilog files for synthesis have to be stored here
\temp\ : Contains all the output files after synthesis or intermediate yosys / graphviz dots files.
\output\ :Contains all the reports and summary outputs of test either performed with the interactive or bulk tool.
\mockturtle_binaries\ : this contains both the source and binary code that performs the MuxIG or MIG mapping.
\nem_liberty\ : Contains the liberty files used for mapping purposes.
\yosys\ : Script that are executed for synthesis, visual, and sat testing.
```
As a user put the desired source files in .\sources\ and follow the instructions to synthesize them to designs.
# 3. How to run
Download the current oss-suite at [this link](https://github.com/YosysHQ/oss-cad-suite-build) and extract it to a working directory.
Pull the repository to your local working directory. Keep oss-suite and this tool seperate.
run:
```bash
source <oss-suite-location>/enviroment
./run.sh
```
and enter the file you want to use. Auto-complete is available. An example would be `sources/test_set/adder2.v`, or `sources/ISCA85/c17.v` . Then enter the main module name. Just press enter if it is the same as the file name, (in the example `adder2`, or `c17`).
-1: As the text explains option 1 will run the synthesis script under `\yosys\` and will output the file as `_nem.v` extension in the `\temp\` folder. Next to that it will output statistics in the `.stat` file under `\temp\`.
-2: pass the circuit to mockturtle to process it into MuxIG graph
-3: pass the circuit to mockturtle to process it into MIG graph
-4: Shows the abstract design before any syntehsis is done
-5: Shows the final synthesized solution
-6: Checks if the original verilog file matches the output of the final synthesised solution.
-7: search for fsm model and view it
-8: Compile plugins in the `\plugins\` directory and start a shell to run them on the current design
-9: Switch to extended liberty file with pass through muxiplexers as internal cells which abc can map too.
-10: Runs the normal test and the MuxIG synthesise. Next to that it tries the normal ABC synthesis on a liberty file which contains an optimal view of the PTL MuxIG implementaitons as normal primitive cells
-11: switch to different verilog file
+
+1. As the text explains option 1 will run the synthesis script under `\yosys\` and will output the file as `_nem.v` extension in the `\temp\` folder. Next to that it will output statistics in the `.stat` file under `\temp\`.
+2. pass the circuit to mockturtle to process it into MuxIG graph
+3. pass the circuit to mockturtle to process it into MIG graph
+4. Shows the abstract design before any syntehsis is done
+5. Shows the final synthesized solution
+6. Checks if the original verilog file matches the output of the final synthesised solution.
+7. search for fsm model and view it
+8. Compile plugins in the `\plugins\` directory and start a shell to run them on the current design
+9. Switch to extended liberty file with pass through muxiplexers as internal cells which abc can map too.
+10. Runs the normal test and the MuxIG synthesise. Next to that it tries the normal ABC synthesis on a liberty file which contains an optimal view of the PTL MuxIG implementaitons as normal primitive cells
+11. switch to different verilog file
# 4. CLI
You can also call the `./run.sh` with some arguments to work as a in-line tool if you want to automate stuff. The options are:
-d [DIRECTORY] synthesise all the files in the directory
-f [FILE_PATH] synthesise specific path
-m [MODULE_NAME] When -f argument used pass the module name
-v when present will also visualize the file.
-x Switch liberty file used or pass specific version
# 5. Optimisation adjusments
The tool will optimise the design already in primitive logic netlis tand perform MuxIG resynthesis with cut rewrittin to try to minimize the device count. All results can be viewed in the exported .csv generated after performing a test. This file contains the total count of all primitive cells used and provides a direct device count translation.
# 6. Bruteforce approach
In \bruteforce_approach\ are a couple c files to help with bruteforce approaches to check a minimal circuit for different type of building blocks. Each is has some tautology recognition to allow it to peform faster. Next to that they all use pthread to allow for parralel processing to speed up execution.
# 7. Troubleshooting
## 7.1. SAT comparison
If the SAT comparison gives a comment that it is not aware of a certain `_DFF_` cell such as `_DFF_PP0` then this specific memory cell does not exist in the standard cell library therefore it does not have the function to simulate it. These register often have asynchronous reset therefore make sure that your design does not use
```
always@(posedge clk or posedge rst)
if (rst) begin
result <= 0;
......
```
but instead
```
always@(posedge clk)
if (rst) begin
result <= 0;
......
```
So that reset happens on the same clk as a normal `_DFF_` register.