c17.ratio
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	------------- normal 3T ---------------

	yosys> stat -liberty ./nem_liberty/nem_basic_yosys.lib

	14. Printing statistics.

	=== c17_nem ===

	Number of wires: 11
	Number of wire bits: 11
	Number of public wires: 7
	Number of public wire bits: 7
	Number of ports: 7
	Number of port bits: 7
	Number of memories: 0
	Number of memory bits: 0
	Number of processes: 0
	Number of cells: 6
	nand_3T 6

	Chip area for module '\c17_nem': 16992.000000
	of which used for sequential elements: 0.000000 (0.00%)

	------------- 4T ---------------

	yosys> stat -liberty ./nem_liberty/nem_basic_yosys_extended.lib

	14. Printing statistics.

	=== c17_nem ===

	Number of wires: 11
	Number of wire bits: 11
	Number of public wires: 7
	Number of public wire bits: 7
	Number of ports: 7
	Number of port bits: 7
	Number of memories: 0
	Number of memory bits: 0
	Number of processes: 0
	Number of cells: 6
	and_4T 2
	and_not_4T 2
	or_4T 2

	Chip area for module '\c17_nem': 7728.000000
	of which used for sequential elements: 0.000000 (0.00%)

	------------- Muxig ---------------
	------------- Stats ---------------
	Area 3T: 16992.000000
	Area 4T: 7728.000000
	Ratio 4T->3T: .45480225988700564971%
	Area MUX:
	Ratio MUX->3T: %