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techmap_nems.v
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techmap_nems.v
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//Mux
(* techmap_celltype = "$lut" *)
module \$lut_1 (A, Y);
parameter LUT = 0;
parameter WIDTH = 3;
wire _TECHMAP_FAIL_ = (WIDTH != 3) || LUT != 8'b11011000;
input [WIDTH-1:0] A;
output Y;
//$mux #(.WIDTH(1)) switch_mux_2 (.A(A[2]),.B(A[1]),.S(A[0]),.Y(Y));
assign Y = A[0] ? A[2] : A[1];
endmodule
//Xnor
(* techmap_celltype = "$lut" *)
module \$lut_2 (A, Y);
parameter LUT = 0;
parameter WIDTH = 2;
wire _TECHMAP_FAIL_ = (WIDTH != 2) || LUT != 4'b1001;
input [WIDTH-1:0] A;
output Y;
assign Y = A[0] ^ A[1];
endmodule
//Inverter
(* techmap_celltype = "$lut" *)
module \$lut_3 (A, Y);
parameter LUT = 0;
parameter WIDTH = 3;
wire _TECHMAP_FAIL_ = (WIDTH != 1) || LUT != 2'b01;
input [WIDTH-1:0] A;
output Y;
assign Y = ~A;
endmodule
//Inverted Select
(* techmap_celltype = "$lut" *)
module \$lut_4 (A, Y);
parameter LUT = 0;
parameter WIDTH = 3;
wire _TECHMAP_FAIL_ = (WIDTH != 3) || LUT != 8'b11100100;
input [WIDTH-1:0] A;
output Y;
$mux #(.WIDTH(1)) switch_mux_1 (.A(A[2]),.B(A[1]),.S(~A[0]),.Y(Y));
endmodule
//Inverted Select and inverted A input.
(* techmap_celltype = "$lut" *)
module \$lut_5 (A, Y);
parameter LUT = 0;
parameter WIDTH = 3;
wire _TECHMAP_FAIL_ = (WIDTH != 3) || LUT != 8'b01001110;
input [WIDTH-1:0] A;
output Y;
$mux #(.WIDTH(1)) switch_mux_2 (.A(~A[2]),.B(A[1]),.S(~A[0]),.Y(Y));
endmodule
//Only Inverted A input
(* techmap_celltype = "$lut" *)
module \$lut_6 (A, Y);
parameter LUT = 0;
parameter WIDTH = 3;
wire _TECHMAP_FAIL_ = (WIDTH != 3) || LUT != 8'b10001101;
input [WIDTH-1:0] A;
output Y;
$mux #(.WIDTH(1)) switch_mux_3 (.A(~A[2]),.B(A[1]),.S(A[0]),.Y(Y));
endmodule

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