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muxig_synth.ys
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######################### preprocessing ###########################################################################
read_verilog {{VERILOG_FILE}}
hierarchy -top {{TOP_MODULE}}
proc;;
opt;;;
flatten -noscopeinfo;;
opt;;;
techmap;;
opt;;;
splitnets -ports;;
opt;;;
########################## write design to a blif file and delete empty line because mockturtle cannot handle that #
write_blif {{TEMP_DIR}}/{{BASE_NAME}}.blif
exec -- sed -i '/^$/d' {{TEMP_DIR}}/{{BASE_NAME}}.blif
rename {{TOP_MODULE}} {{TOP_MODULE}}_golden
########################## execute muxig pass map the result back to yosys names and rename the module #############
exec -- time -f "\nTime: %E\nCPU: %P\nMemory: %M KB" -o {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_muxig_time.txt ./build/src/convert_muxig_opt -o {{OUT_DIR}}/{{BASE_NAME}} {{TEMP_DIR}}/{{BASE_NAME}}.blif
exec -- python ./yosys/map_ports.py {{TEMP_DIR}}/{{BASE_NAME}}.blif {{TEMP_DIR}}/{{BASE_NAME}}_muxig_temp.blif
read_blif {{TEMP_DIR}}/{{BASE_NAME}}_muxig.blif
rename top {{TOP_MODULE}}_muxig
copy {{TOP_MODULE}}_muxig {{TOP_MODULE}}_muxig_sat
########################## read back the optimization and map it back to yosys internal gates #######################
techmap -map yosys/mockturtle_map.v {{TOP_MODULE}}_muxig
techmap {{TOP_MODULE}}_muxig
opt {{TOP_MODULE}}_muxig
########################### check equality of the optimization ######################################################
{{SAT}}techmap -map yosys/mockturtle_map.v {{BASE_NAME}}_muxig_sat
{{SAT}}techmap {{BASE_NAME}}_muxig_sat
{{SAT}}miter -equiv -make_assert {{TOP_MODULE}}_golden {{TOP_MODULE}}_muxig_sat equal
{{SAT}}flatten equal
{{SAT}}clean equal
{{SAT}}opt -full equal
{{SAT}}techmap equal
{{SAT}}sat -prove-asserts -set-init-zero -tempinduct -verify -show-regs -show-inputs -show-outputs -dump_vcd trace.vcd equal
########################### write data without abc pass #############################################################
tee -o {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_muxig.json stat -json {{TOP_MODULE}}_muxig
tee -o {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_golden.json stat -json {{TOP_MODULE}}_golden
tee -o {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_muxig_ltp.txt ltp {{TOP_MODULE}}_muxig
tee -o {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_golden_ltp.txt ltp {{TOP_MODULE}}_golden
########################### abc pass for the golden solution ########################################################
copy {{TOP_MODULE}}_golden {{TOP_MODULE}}_golden_abc
abc -liberty {{LIBERTY_FILE}} {{TOP_MODULE}}_golden_abc
tee -o {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_golden_abc.json stat -json {{TOP_MODULE}}_golden_abc
########################### abc pass for the optimization solution #################################################
copy {{TOP_MODULE}}_muxig {{TOP_MODULE}}_muxig_abc
abc -liberty {{LIBERTY_FILE}} -script "+attach"
tee -o {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_muxig_abc.json stat -json {{TOP_MODULE}}_muxig_abc
########################### write abc blif and verilog #############################################################
write_blif -top {{TOP_MODULE}}_muxig_abc {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_muxig_abc.blif
write_blif -top {{TOP_MODULE}}_golden_abc {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_golden_abc.blif
select {{TOP_MODULE}}_muxig_abc
write_verilog -selected {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_muxig_abc.v
select {{TOP_MODULE}}_golden_abc
write_verilog -selected {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_golden_abc.v
### this does not work for now so it is not considered
#tee -o {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_muxig_abc_ltp.txt ltp {{TOP_MODULE}}_muxig_abc

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