module fsm (
    input wire clk,
    input wire reset,
    input wire [1:0] in,
    output wire out
);
    reg [2:0] main_state;  // 3 bits for 8 states
    reg [2:0] sub_state;   // 3 bits for 5 states (2 bits will suffice for 4 states, but using 3 for simplicity)

    // Main FSM controlling a sub FSM
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            main_state <= 3'b000;  // Reset to state 0
        end else begin
            case (main_state)
                3'b000: main_state <= in[0] ? 3'b001 : 3'b000;
                3'b001: main_state <= in[0] ? 3'b010 : 3'b001;
                3'b010: main_state <= in[0] ? 3'b011 : 3'b010;
                3'b011: main_state <= in[0] ? 3'b100 : 3'b011;
                3'b100: main_state <= in[0] ? 3'b101 : 3'b100;
                3'b101: main_state <= in[0] ? 3'b110 : 3'b101;
                3'b110: main_state <= in[0] ? 3'b111 : 3'b110;
                3'b111: main_state <= 3'b000;  // Cycle back to 0
                default: main_state <= 3'b000;  // Safe default
            endcase
        end
    end

    // Sub FSM definition
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            sub_state <= 3'b000;  // Reset sub state
        end else begin
            case (sub_state)
                3'b000: sub_state <= in[1] ? 3'b001 : 3'b000;
                3'b001: sub_state <= in[1] ? 3'b010 : 3'b001;
                3'b010: sub_state <= in[1] ? 3'b011 : 3'b010;
                3'b011: sub_state <= in[1] ? 3'b100 : 3'b011;
                3'b100: sub_state <= 3'b000;  // Cycle back to 0 after reaching state 4
                default: sub_state <= 3'b000;  // Safe default
            endcase
        end
    end

    // Output logic based on main and sub states
    assign out = (main_state == 3'b111 && sub_state == 3'b100);  // Example condition for output

endmodule