//Mux
(* techmap_celltype = "$lut" *)
module \$lut_1 (A, Y);
    parameter LUT = 0;
    parameter WIDTH = 3;

    wire _TECHMAP_FAIL_ = (WIDTH != 3) || LUT != 8'b11011000; 

    input [WIDTH-1:0] A;
    output Y;

    //$mux #(.WIDTH(1)) switch_mux_2 (.A(A[2]),.B(A[1]),.S(A[0]),.Y(Y));
    assign Y = A[0] ? A[2] : A[1];
endmodule

//Xnor
(* techmap_celltype = "$lut" *)
module \$lut_2 (A, Y);
    parameter LUT = 0;
    parameter WIDTH = 2;

    wire _TECHMAP_FAIL_ = (WIDTH != 2) || LUT != 4'b1001; 

    input [WIDTH-1:0] A;
    output Y;

    assign Y = A[0] ^ A[1];
endmodule

//MUXXOR
(* techmap_celltype = "$lut" *)
module \$lut_3 (A, Y);
    parameter LUT = 0;
    parameter WIDTH = 4;

    wire _TECHMAP_FAIL_ = (WIDTH != 4) || LUT != 16'b1111100101100000; 

    input [WIDTH-1:0] A;
    output Y;

    muxxor_inv muxxor1 (.a(A[0]), .b(A[1]), .in0(A[2]), .in1(A[3]), .o(Y));
endmodule