module fsm (
    input wire clk,
    input wire reset,
    input wire in,
    output wire out
);

    // Define state encoding using parameters
    parameter S0 = 3'b000, 
              S1 = 3'b001, 
              S2 = 3'b010, 
              S3 = 3'b011, 
              S4 = 3'b100, 
              S5 = 3'b101;
    
    reg [2:0] state, next_state;  // 3-bit state register

    // Sequential block: state transitions on clock or reset
    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= S0;  // Reset to S0
        else
            state <= next_state;
    end

    // Combinational block: next state logic
    always @(*) begin
        case (state)
            S0: next_state = in ? S1 : S0;
            S1: next_state = in ? S2 : S1;
            S2: next_state = in ? S3 : S2;
            S3: next_state = in ? S4 : S3;
            S4: next_state = in ? S5 : S4;
            S5: next_state = S0;  // Cycle back to S0 after S5
            default: next_state = S0;  // Safe default in case of illegal state
        endcase
    end

    // Combinational block: output logic
    assign out = (next_state == S5);
endmodule