module fsm (
    input wire clk,
    input wire reset,
    input wire in,
    output reg out
);
    // Define state encoding using parameters
    parameter S0 = 2'b00, 
              S1 = 2'b01, 
              S2 = 2'b10;

    reg [1:0] state, next_state;

    // State transition logic
    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= S0;  // Reset to S0
        else
            state <= next_state;  // Move to next state
    end

    // Next state logic
    always @(*) begin
        case (state)
            S0: next_state = in ? S1 : S0;
            S1: next_state = in ? S2 : S1;
            S2: next_state = in ? S0 : S2;
            default: next_state = S0;  // Safe default
        endcase
    end

    // Output logic (Moore: depends only on the state)
    always @(posedge clk or posedge reset) begin
        if (reset)
            out <= 0;  // Reset output
        else begin
            case (state)
                S0: out <= 1;
                S1: out <= 0;
                S2: out <= 1;
                default: out <= 0;  // Safe default
            endcase
        end
    end
endmodule