read_verilog {{FILE}}

#map to basic cells
techmap

write_blif ./temp/{{FILE_BASENAME}}.blif
abc -liberty ./{{LIBERTY_FILE}} -script "+strash; &get -n; collapse; write_eqn ./temp/{{FILE_BASENAME}}.eqn; write_truth ./temp/{{FILE_BASENAME}}.truth; write_pla ./temp/{{FILE_BASENAME}}.pla" 
exec -- ./mockturtle/build/experiments/muxig_rewriting ./temp/{{FILE_BASENAME}}.blif

delete
read_blif ./temp/{{FILE_BASENAME}}_mockturtle.blif

cd top

rename pi1 N1
rename pi2 N2
rename pi3 N3
rename pi4 N6
rename pi5 N7

rename po0 N22
rename po1 N23

cd ..

rename top {{MODULE}}_nem
read_liberty {{LIBERTY_FILE}}

techmap -map ./yosys/mockturtle_map.v
clean
techmap

clean
select c17_nem
write_verilog -selected ./temp/{{FILE_BASENAME}}_nem.v
#Output stats
tee -o ./temp/{{FILE_BASENAME}}_{{LIBERTY_USED}}.stat stat -liberty ./{{LIBERTY_FILE}}