module fsm (
    input wire clk,
    input wire reset,
    input wire [3:0] in,
    output reg [1:0] out
);
    // Define state encoding using parameters
    parameter S0  = 4'b0000, S1  = 4'b0001, S2  = 4'b0011, S3  = 4'b0010,
              S4  = 4'b0110, S5  = 4'b0111, S6  = 4'b0101, S7  = 4'b0100,
              S8  = 4'b1100, S9  = 4'b1101, S10 = 4'b1111, S11 = 4'b1110;

    reg [3:0] state, next_state;

    // State transition logic (sequential)
    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= S0;  // Reset to initial state S0
        else
            state <= next_state;  // Transition to the next state
    end

    // Next state logic (combinational)
    always @(*) begin
        case (state)
            S0: next_state = in[0] ? S1 : S0;
            S1: next_state = in[1] ? S2 : S1;
            S2: next_state = in[2] ? S3 : S2;
            S3: next_state = in[3] ? S4 : S3;
            S4: next_state = in[0] ? S5 : S4;
            S5: next_state = in[1] ? S6 : S5;
            S6: next_state = in[2] ? S7 : S6;
            S7: next_state = in[3] ? S8 : S7;
            S8: next_state = in[0] ? S9 : S8;
            S9: next_state = in[1] ? S10 : S9;
            S10: next_state = in[2] ? S11 : S10;
            S11: next_state = S0;  // Loop back to S0 after S11
            default: next_state = S0;  // Default case
        endcase
    end

    // Output logic (Moore-type, depends only on the state)
    always @(*) begin
        case (state)
            S0, S1: out = 2'b00;
            S2, S3: out = 2'b01;
            S4, S5: out = 2'b10;
            S6, S7: out = 2'b11;
            S8, S9: out = 2'b01;
            S10, S11: out = 2'b10;
            default: out = 2'b00;  // Safe default
        endcase
    end
endmodule