######################### preprocessing ########################################################################### read_verilog {{VERILOG_FILE}} hierarchy -top {{TOP_MODULE}} proc;; opt;;; flatten -noscopeinfo;; opt;;; techmap;; opt;;; splitnets -ports;; opt;;; ########################## write design to a blif file and delete empty line because mockturtle cannot handle that # write_blif {{TEMP_DIR}}/{{BASE_NAME}}.blif exec -- sed -i '/^$/d' {{TEMP_DIR}}/{{BASE_NAME}}.blif rename {{TOP_MODULE}} {{TOP_MODULE}}_golden ########################## execute bdd pass map the result back to yosys names and rename the module ############# exec -- timeout {{TIMEOUT}} time -f "\nTime: %E\nCPU: %P\nMemory: %M KB" -o {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_bdd_time.txt ./build/src/convert_bdd {{TEMP_DIR}}/{{BASE_NAME}}.blif read_blif {{TEMP_DIR}}/{{BASE_NAME}}_bdd.blif rename {{TOP_MODULE}} {{TOP_MODULE}}_bdd techmap -map {{TECHMAP_BBDD}} {{BASE_NAME}}_bdd stat {{BASE_NAME}}_bdd opt {{TOP_MODULE}}_bdd stat {{BASE_NAME}}_bdd opt -full {{TOP_MODULE}}_golden ########################### check equality of the optimization ###################################################### {{SAT}}miter -equiv -make_assert {{TOP_MODULE}}_golden {{TOP_MODULE}}_bdd equal {{SAT}}flatten equal {{SAT}}clean equal {{SAT}}opt -full equal;; {{SAT}}techmap equal {{SAT}}sat -prove-asserts -set-init-zero -tempinduct -verify -show-regs -show-inputs -show-outputs -dump_vcd trace.vcd equal ########################### write stats without abc pass ############################################################# tee -o {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_bdd.json stat -json {{TOP_MODULE}}_bdd tee -o {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_golden.json stat -json {{TOP_MODULE}}_golden tee -o {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_bdd_ltp.txt ltp {{TOP_MODULE}}_bdd tee -o {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_golden_ltp.txt ltp {{TOP_MODULE}}_golden ########################### write netlists without abc pass ############################################################# write_blif -top {{TOP_MODULE}}_bdd {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_bdd.blif write_blif -top {{TOP_MODULE}}_golden {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_golden.blif select {{TOP_MODULE}}_bdd write_verilog -selected {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_bdd.v select {{TOP_MODULE}}_golden write_verilog -selected {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_golden.v ########################### abc pass for the golden solution ######################################################## copy {{TOP_MODULE}}_golden {{TOP_MODULE}}_golden_abc abc -liberty {{LIBERTY_FILE}} {{TOP_MODULE}}_golden_abc tee -o {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_golden_abc.json stat -json {{TOP_MODULE}}_golden_abc ########################### abc pass for the optimization solution ################################################# copy {{TOP_MODULE}}_bdd {{TOP_MODULE}}_bdd_abc abc -liberty {{LIBERTY_FILE}} -script "+attach" tee -o {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_bdd_abc.json stat -json {{TOP_MODULE}}_bdd_abc ########################### write abc blif and verilog ############################################################# write_blif -top {{TOP_MODULE}}_bdd_abc {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_bdd_abc.blif write_blif -top {{TOP_MODULE}}_golden_abc {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_golden_abc.blif select {{TOP_MODULE}}_bdd_abc write_verilog -selected {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_bdd_abc.v select {{TOP_MODULE}}_golden_abc write_verilog -selected {{OUT_DIR}}/{{BASE_NAME}}/{{BASE_NAME}}_golden_abc.v