diff --git a/README.md b/README.md index 8e6053d..dc7b17f 100644 --- a/README.md +++ b/README.md @@ -1,95 +1,103 @@ # 1. NEM synthesis This utility was written to use yosys to synthesize from verilog to a netlist existing out of all standard cells available in the current library of NEM cells. It only uses the freely available yosys oss suite. No license required # 2. data structure The application is ordered as follows: ``` +\bruteforce_approach\: contains all the c script's and a python script to run bruteforce approach on very small functions \sources\ : All the verilog files for synthesis have to be stored here \temp\ : Contains all the output files after synthesis or intermediate yosys / graphviz dots files. \yosys\ : Script that are executed for synthesis, visual, and sat testing. \nem_basic_yosys.lib : This is the file of all the standard cells used in nem \nem_basic_yosys_extended.lib : this is the additional cells added based on some new concepts ``` As a user put the desired source files in .\sources\ and had to the next sessions # 3. How to run Pull the repository to your local working directory. run: ```bash source /enviroment ./run.sh ``` and enter the file you want to use. Auto-complete is aviable, an example would be `sources/test_set/adder2.v`. Then enter the main module name. Just press enter if it is the same as the file name, (in the example `adder2`). You will be presented with the following options: ```bash -------------------------------------------------------------- Current file: sources/test_set/adder2.v with module: adder2 Please select your options (you can choose multiple options): -1) Synthesize NEM mapped replicate of Verilog implementation +1) Synthesize to NEM technology 2) Print initial design 3) Print out NEM optimized design 4) Perform SAT comparison 5) Export FSM as KISS2 format 6) Start shell with modules 7) Switch from normal 3T gate library to new 4T 8) Run test -9) Select a new Verilog file +9) export truth table and MUXIG run +10) export truth table and MIG run +11) Select a new Verilog file 0) Exit the program -------------------------------------------------------------- Enter your choices (e.g., 1 2 3, or 0 to finish): ``` 1: As the text explains option 1 will run the synthesis script under `\yosys\` and will output the file as `_nem.v` extension in the `\temp\` folder. Next to that it will output statistics in the `.stat` file under `\temp\`. 2: Shows the abstract design before any syntehsis is done 3: Shows the final synthesized solution 4: Checks if the original verilog file matches the output of the final synthesised solution. 5: search for fsm model and view it 6: Compile plugins and start a shell to run them 7: Switch to extended liberty file with pass through muxiplexers 8: run synthesis and visual for both liberty files -9: switch to different verilog file +9: pass the circuit to mockturtle to process it into MuxIG graph +10: pass the circuit to mockturtle to process it into MIG graph +11: switch to different verilog file # 4. CLI You can also call the `./run.sh` with some arguments to work as a in-line tool if you want to automate stuff. The options are: -d [DIRECTORY] synthesise all the files in the directory -f [FILE_PATH] syntehsise specific path -m [MODULE_NAME] When -f argument used -v when present will also visuale the file. -x Switch liberty file to extended version # 5. Optimisation adjusments the new extended libary makes use of trivial boolean equivalent muxiplexers and operators for AND and OR operations. More info will be added later. +# Bruteforce approach +In \bruteforce_approach\ are a couple c files to help with small bruteforce approaches to check a minimal circuit. + # 6. Troubleshooting ## 6.1. SAT comparison If the SAT comparison gives a comment that it is not aware of a certain `_DFF_` cell such as `_DFF_PP0` then this specific memeory cell does not exist in the standard cell library therefore it does not have the function to simulate it. These register often have asynchronous reset therefore make sure that your design does not use ``` always@(posedge clk or posedge rst) if (rst) begin result <= 0; ...... ``` but instead ``` always@(posedge clk) if (rst) begin result <= 0; ...... ``` So that reset happens on the same clk as a normal `_DFF_` register. \ No newline at end of file diff --git a/bruteforce_approach/bruteforce_mux-xor.c b/bruteforce_approach/bruteforce_mux-xor.c index ebb3f36..7c37bd6 100644 --- a/bruteforce_approach/bruteforce_mux-xor.c +++ b/bruteforce_approach/bruteforce_mux-xor.c @@ -1,483 +1,486 @@ #include #include #include #include #include #include #include // -------------- config #define MAX_AREA 10000 //Determine the initial max_area -#define NUM_INPUTS 3 //speaks for itself -#define MAX_GATES 6 // determine the max_amount of gates -#define NUM_THREADS 3 //Needs to be <= 9 or 18 or 27 for efficient splitting the work load +#define NUM_INPUTS 4 //speaks for itself +#define MAX_GATES 3 // determine the max_amount of gates +#define NUM_THREADS 4 //Needs to be <= 9 or 18 or 27 for efficient splitting the work load #define use_truth_table 1 //If 1 use the truth table below. If multiple outputs then paste the truth table after another from the [file].truth +#define target_truth_table "00000000" //#define target_truth_table "11101000" //exampe here [Target A][Target B] pasted after another. //MAJ testing -#define target_truth_table "1110100010010110" + + +//#define target_truth_table "1110100010010110" //half adder /* The truth table matching this is that of a increase in value of the input variables Let's say 3 input variables I3 I2 I1 | O2 O1 A, B, Cin, | S Cout 0, 0, 0, | 0 0 0, 0, 1, | 1 0 0, 1, 0, | 1 0 0, 1, 1, | 0 1 1, 0, 0, | 1 0 1, 0, 1, | 0 1 1, 1, 0, | 0 1 1, 1, 1, | 1 1 S = 10010110 Cout = 11101000 MUX = 11001010 target_truth_table = "S Cin" = "1110100010010110" also means that output B */ //AND = &&, OR = ||, XOR = ^, NOT = ! int target_function(int inputs[]) { return inputs[0] ^ inputs[1]; } // -------------- Auto-define #define NUM_COMBINATION (1 << NUM_INPUTS) #define NUM_OUTPUTS (sizeof(target_truth_table)-1)/NUM_COMBINATION // -------------- structs typedef struct { char* type; int area; } GateType; typedef struct { GateType* gate; int8_t in1; int8_t in2; int8_t in3; int8_t in4; } Gate; typedef struct { Gate gates[MAX_GATES]; int8_t gate_count; int area; } Circuit; typedef struct { Circuit volatile best_circuit; GateType *gate_types; int num_inputs; int num_gates; int volatile best_area; int8_t *truth_table; int8_t *target_outputs; int worker_id; int num_circuit[2]; //first is the amount in million and the second is the increment counter. pthread_mutex_t mutex; } ThreadArgs; // -------------- define used gates GateType gate_types[] = { {"INV", 1160}, {"MUX-XOR", 1288} }; // -------------- start functions void tee(FILE *f, char const *fmt, ...) { va_list ap; va_start(ap, fmt); vprintf(fmt, ap); va_end(ap); va_start(ap, fmt); vfprintf(f, fmt, ap); va_end(ap); } void print_circuit(Circuit * circuit){ FILE *fptr; - fptr = fopen("../output/output_bruteforce.txt", "a"); + fptr = fopen("./output/output_bruteforce.txt", "a"); //for(int y=0; ygate_count; y++){ // printf("%d: %s, in1: %d, in2: %d, in3: %d\n",y,circuit->gates[y].gate->type,circuit->gates[y].in1,circuit->gates[y].in2,circuit->gates[y].in3); //} tee(fptr,"---------- Circuit area: %d ----------\n",circuit->area); tee(fptr,"Input "); for(int i='a';(i-'a')gate_count; y++){ int print_in1 = circuit->gates[y].in1 + '0'; int print_in2 = circuit->gates[y].in2 + '0'; int print_in3 = circuit->gates[y].in3 + '0'; int print_in4 = circuit->gates[y].in4 + '0'; if((print_in1-2-'0')=0){ print_in1 = circuit->gates[y].in1-2 + 'a'; } if((print_in2-2-'0')=0){ print_in2 = circuit->gates[y].in2-2 + 'a'; } if((print_in3-2-'0')=0){ print_in3 = circuit->gates[y].in3-2 + 'a'; } if((print_in4-2-'0')=0){ print_in4 = circuit->gates[y].in4-2 + 'a'; } tee(fptr,"%d: %s, in1: %c, in2: %c, in3: %c, in4: %c\n",y+NUM_INPUTS+2,circuit->gates[y].gate->type,print_in1,print_in2,print_in3,print_in4); } tee(fptr,"Output "); for(int i='x';(i-'x')gate_count-NUM_OUTPUTS+(i-'x')+2);} tee(fptr,"\n"); tee(fptr,"----------------------------------------\n"); fclose(fptr); } void write_circuit_to_file(Circuit * circuit, int area, int worker_number, int file_number){ FILE *fptr; char file_name[100]; - sprintf(file_name, "../output/output_%d_%d_%d_bruteforce.dot", area, worker_number, file_number); + sprintf(file_name, "./output/output_%d_%d_%d_bruteforce.dot", area, worker_number, file_number); fptr = fopen(file_name, "w"); //for(int y=0; ygate_count; y++){ // printf("%d: %s, in1: %d, in2: %d, in3: %d\n",y,circuit->gates[y].gate->type,circuit->gates[y].in1,circuit->gates[y].in2,circuit->gates[y].in3); //} fprintf(fptr, "digraph Circuit {\n rankdir=LR; // Makes the graph left-to-right\n node [shape=ellipse]; // Default shape for nodes\n ranksep=2; // Increases vertical separation\n"); for(int i='a';(i-'a')gate_count; y++){ int print_in1 = circuit->gates[y].in1 + '0'; int print_in2 = circuit->gates[y].in2 + '0'; int print_in3 = circuit->gates[y].in3 + '0'; int print_in4 = circuit->gates[y].in4 + '0'; if((print_in1-2-'0')=0){ print_in1 = circuit->gates[y].in1-2 + 'a'; } if((print_in2-2-'0')=0){ print_in2 = circuit->gates[y].in2-2 + 'a'; } if((print_in3-2-'0')=0){ print_in3 = circuit->gates[y].in3-2 + 'a'; } if((print_in4-2-'0')=0){ print_in4 = circuit->gates[y].in4-2 + 'a'; } int unit_number = y+NUM_INPUTS+2; fprintf(fptr," %d [ shape=record, label=\"{{ ==| XOR 0| XOR 1| !=}| MUX-XOR %d |{ Y}}\", color=\"darkred\", fontcolor=\"darkred\" ];\n",unit_number,unit_number); fprintf(fptr," %c:e -> %d:p1;\n %c:e -> %d:p2;\n %c:e -> %d:p3;\n %c:e -> %d:p4;\n",print_in1,unit_number,print_in2,unit_number,print_in3,unit_number,print_in4,unit_number); } for(int i='x';(i-'x') %c;\n",NUM_INPUTS+circuit->gate_count-NUM_OUTPUTS+(i-'x')+2,i);} fprintf(fptr,"}\n"); fclose(fptr); } void evaluate_circuit(GateType* all_gates, Circuit* circuit, int8_t* inputs, int8_t* outputs) { int8_t intermediate_outputs[NUM_INPUTS + MAX_GATES+2]; intermediate_outputs[0] = 0; //Make sure that intermediate_outputs[0] = 0 and [1] = 1 for constant signal attachments intermediate_outputs[1] = 1; memcpy(&intermediate_outputs[2], inputs, NUM_INPUTS * sizeof(int8_t)); //copy boolean value over this for (int i = 0; i < circuit->gate_count; i++) { int out1 = intermediate_outputs[circuit->gates[i].in1]; int out2 = intermediate_outputs[circuit->gates[i].in2]; int out3 = intermediate_outputs[circuit->gates[i].in3]; int out4 = intermediate_outputs[circuit->gates[i].in4]; int output = 0; if (circuit->gates[i].gate == &all_gates[0]) //INV output = ~out1 & 1; else if (circuit->gates[i].gate == &all_gates[1]) //MUX-XOR output = (out4^out3) ? out2 : out1; intermediate_outputs[NUM_INPUTS + i + 2] = output; } for(int z=0; zgate_count-NUM_OUTPUTS+z]; } } int detect_tautology(Circuit *current_circuit, int in1, int in2, int in3, int in4, int gate_selected, ThreadArgs *data){ if ((in1 == in2 && gate_selected != 0) || //(in1 == in3 || in2 == in3) || (in3 == in4)){ //(in1 == 0 && in2 == 1 && gate_selected != 0) ){ //|| //Skip gate if it has the same input both ports NOTE THAT IF i == 0 THEN WE SELECT INV. return 1; } for(int i=0; i<(current_circuit->gate_count-1);i++){ if(current_circuit->gates[i].gate == &data->gate_types[gate_selected]){ if(current_circuit->gates[i].in1 == in1 && current_circuit->gates[i].in2 == in2 && current_circuit->gates[i].in3 == in3){ return 1; //DETECTED A COMPLETE equivalent circuit } } } int input_used[current_circuit->gate_count + data->num_inputs+2]; memset(input_used, 0, sizeof(input_used)); input_used[0] = 1; //make sure that the constant don't trigger a faulty tautology result. input_used[1] = 1; for(int i=0; igate_count; i++){ input_used[current_circuit->gates[i].in1] = 1; input_used[current_circuit->gates[i].in2] = 1; input_used[current_circuit->gates[i].in3] = 1; } input_used[in1] = 1; input_used[in2] = 1; input_used[in3] = 1; input_used[in4] = 1; for(int i=0; i < (current_circuit->gate_count + data->num_inputs - NUM_OUTPUTS+2); i++){ if(input_used[i]==0 && current_circuit->gate_count!=0){ return 2; //missing an used output } } return 0; } void generate_circuits_recursive(Circuit *current_circuit, int depth, ThreadArgs *data) { if (depth == data->num_gates){ // Reached end of amount of gates. return; } GateType* gate_types = data->gate_types; // Loop through gate types and inputs to build possible circuits //int num_gate_types = 1; //int division = (num_gate_types + NUM_THREADS-1)/NUM_THREADS; //int multi_core_division=NUM_THREADS/num_gate_types; //0 - 2, 3 - 5, 6 - 8 //for (int i = 0; i < num_gate_types; i++) { int i = 1; //Only select the multiplexer if((current_circuit->area+data->gate_types[i].area)>data->best_area){ //printf("worker %d: area %d on gate type %d and depth %d larger then best area %d continueing\n",data->worker_id,current_circuit->area,i,depth,data->best_area); return; } for (int in4 = 0; in4 < depth + data->num_inputs + 2; in4++){ for (int in3 = 0; in3 < depth + data->num_inputs + 2; in3++){ //Going for multithread approach if(in3 != data->worker_id+2 && depth == 0){ continue; } for (int in2 = 0; in2 < depth + data->num_inputs + 2; in2++) { for (int in1 = 0; in1 < depth + data->num_inputs + 2; in1++){ data->num_circuit[0] += 1; // Add the new gate to the circuit current_circuit->gates[depth].gate = &gate_types[i]; //set pointer to the type of gate current_circuit->gates[depth].in1 = in1; current_circuit->gates[depth].in2 = in2; current_circuit->gates[depth].in3 = in3; current_circuit->gates[depth].in4 = in4; current_circuit->gate_count = depth + 1; //if(current_circuit->gates[0].in1 == 0 && current_circuit->gates[0].in2 == 1 && current_circuit->gates[0].in3 == 3 && current_circuit->gates[1].in1 == 2 && current_circuit->gates[1].in2 == 3 && current_circuit->gates[1].in3 == 4 && current_circuit->gates[2].in1 == 4 && current_circuit->gates[2].in2 == 5 && current_circuit->gates[2].in3 == 6){// && current_circuit->gates[2].gate==&data->gate_types[6]){ //if(current_circuit->gates[0].in1 == 2 && current_circuit->gates[0].in2 == 3 && current_circuit->gates[0].in3 == 4){ // printf("test\n"); //} int tautology = detect_tautology(current_circuit,in1,in2,in3,in4,i,data); //0: nothing found, 1: direct tautology, 2:unconnected device may still be connected. if(tautology==1){ continue; //Found already unnecessary combo and should skip it } int valid = 0; if(tautology!=2){ //There is an unconnected gate if this holds true valid = 1; int8_t output[NUM_OUTPUTS]; for (int y=0; y < (1 << data->num_inputs); y++){ //CHECK IF IT IS VALID evaluate_circuit(data->gate_types, current_circuit, &data->truth_table[y*data->num_inputs], output); for(int z=0; ztarget_outputs[y+NUM_COMBINATION*z]){ valid = 0; } } } } //valid circuit add area current_circuit->area += gate_types[i].area; // Example area increment (modify as needed) if(data->num_circuit[0]%1000000000 == 0){ data->num_circuit[1] += 1; data->num_circuit[0] = 0; printf("%d:At circuit number %d M current best_area %d and tested area %d\n",data->worker_id,data->num_circuit[1],data->best_area,current_circuit->area); } pthread_mutex_lock(&data->mutex); //get mutex if(valid == 1 && current_circuit->areabest_area){ //Found a valid solution! memcpy((void *)&data->best_circuit, current_circuit, sizeof(Circuit)); //write to best circuit printf("%d: Found proper solution\n",data->worker_id); print_circuit(current_circuit); write_circuit_to_file(current_circuit,current_circuit->area,data->worker_id,data->num_circuit[0]*100 + data->num_circuit[1]); data->best_area = current_circuit->area; } pthread_mutex_unlock(&data->mutex); // Recurse to add more gates generate_circuits_recursive(current_circuit, depth + 1, data); current_circuit->area -= gate_types[i].area; // Example area increment (modify as needed) //printf("worker %d: returning with depth %d and area %d\n",data->worker_id,depth,current_circuit->area); } } } } } void* search_space_worker(void* args) { // Define and initialize worker-specific parameters and loop through circuits // You will need to pass parameters in `args` and cast them in this function ThreadArgs *data; data = (ThreadArgs *) args; Circuit current_circuit; current_circuit.area = 0; current_circuit.gate_count = 0; printf("%d: best Area %d, Going in recusive loop to check all circuits\n",data->worker_id, data->best_area); generate_circuits_recursive(¤t_circuit, 0, data); //finished set worker_id to 1000 to indicate to the management thread that we finished pthread_mutex_lock(&data->mutex); data->worker_id = 1000; pthread_mutex_unlock(&data->mutex); return NULL; // Return the best found circuit and area as needed } void brute_force_boolean(Circuit* best_circuit, int8_t truth_table[], int8_t target_outputs[], int num_inputs, int max_gates, int max_area) { pthread_t threads[NUM_THREADS]; ThreadArgs thread_args[NUM_THREADS]; // Define `ThreadArgs` to pass data to threads int best_area = max_area; int total_circuits = 0; for (int i = 0; i < NUM_THREADS; i++) { thread_args[i].gate_types = gate_types; thread_args[i].num_inputs = num_inputs; thread_args[i].num_gates = max_gates; thread_args[i].best_area = best_area; thread_args[i].truth_table = truth_table; thread_args[i].target_outputs = target_outputs; thread_args[i].worker_id = i; thread_args[i].num_circuit[0] = 0; thread_args[i].num_circuit[1] = 0; pthread_mutex_init(&thread_args[i].mutex, NULL); pthread_create(&threads[i], NULL, search_space_worker, (void *)&thread_args[i]); } clock_t begin = clock(); int number_of_running_threads = NUM_THREADS; while(number_of_running_threads>0){ number_of_running_threads = NUM_THREADS; for (int i = 0; i < NUM_THREADS; i++) { pthread_mutex_lock(&thread_args[i].mutex); //get lock on the data //Check if it found a better circuit then known before. if(thread_args[i].best_areabest_area){ printf("setting the best_area size %d, on worker: %d\n",best_area,i); thread_args[i].best_area = best_area; } //lastly check if the thread_closed if(thread_args[i].worker_id==1000){ number_of_running_threads -= 1; } pthread_mutex_unlock(&thread_args[i].mutex); // Collect best circuits and area from each thread } clock_t toc = clock(); printf("%f: running number of threads: %d\n",(double)(toc - begin) / (CLOCKS_PER_SEC*number_of_running_threads),number_of_running_threads); sleep(5); } printf("no threads running anymore\n"); // Output the best circuit //count total amount of circuits for(int i=0;i> j) & 1; // Extract each bit of i as an input truth_table[i*num_inputs+j] = (i >> j) & 1;; } target_outputs[i] = target_function(inputs); } } int main() { // Define target function output int8_t target_outputs[NUM_COMBINATION*NUM_OUTPUTS]; // 1< #include #include #include #include #include #include // -------------- config #define MAX_AREA 15000 //Determine the initial max_area #define NUM_INPUTS 3 //speaks for itself -#define MAX_GATES 6 // determine the max_amount of gates +#define MAX_GATES 5 // determine the max_amount of gates #define NUM_THREADS 3 //Needs to be <= 9 or 18 or 27 for efficient splitting the work load #define use_truth_table 1 //If 1 use the truth table below. If multiple outputs then paste the truth table after another from the [file].truth -#define target_truth_table "11101000" //exampe here [Target A][Target B] pasted after another. - +//#define target_truth_table "00000000" //exampe here [Target A][Target B] pasted after another. +#define target_truth_table "1110100010010110" /* The truth table matching this is that of a increase in value of the input variables Let's say 3 input variables I3 I2 I1 | O2 O1 A, B, Cin, | S Cout 0, 0, 0, | 0 0 0, 0, 1, | 1 0 0, 1, 0, | 1 0 0, 1, 1, | 0 1 1, 0, 0, | 1 0 1, 0, 1, | 0 1 1, 1, 0, | 0 1 1, 1, 1, | 1 1 S = 10010110 Cout = 11101000 MUX = 11001010 target_truth_table = "S Cin" = "1110100010010110" also means that output B */ //AND = &&, OR = ||, XOR = ^, NOT = ! int target_function(int inputs[]) { return inputs[0] ^ inputs[1]; } // -------------- Auto-define #define NUM_COMBINATION (1 << NUM_INPUTS) #define NUM_OUTPUTS (sizeof(target_truth_table)-1)/NUM_COMBINATION // -------------- structs typedef struct { char* type; int area; } GateType; typedef struct { GateType* gate; int8_t in1; int8_t in2; int8_t in3; } Gate; typedef struct { Gate gates[MAX_GATES]; int8_t gate_count; int area; } Circuit; typedef struct { Circuit volatile best_circuit; GateType *gate_types; int num_inputs; int num_gates; int volatile best_area; int8_t *truth_table; int8_t *target_outputs; int worker_id; int num_circuit[2]; //first is the amount in million and the second is the increment counter. pthread_mutex_t mutex; } ThreadArgs; // -------------- define used gates GateType gate_types[] = { {"INV", 1160}, {"MUX", 1288} }; // -------------- start functions void tee(FILE *f, char const *fmt, ...) { va_list ap; va_start(ap, fmt); vprintf(fmt, ap); va_end(ap); va_start(ap, fmt); vfprintf(f, fmt, ap); va_end(ap); } void print_circuit(Circuit * circuit){ FILE *fptr; - fptr = fopen("../output/output_bruteforce.txt", "a"); + fptr = fopen("./output/output_bruteforce.txt", "a"); //for(int y=0; ygate_count; y++){ // printf("%d: %s, in1: %d, in2: %d, in3: %d\n",y,circuit->gates[y].gate->type,circuit->gates[y].in1,circuit->gates[y].in2,circuit->gates[y].in3); //} tee(fptr,"------- Circuit area: %d -------\n",circuit->area); tee(fptr,"Input "); for(int i='a';(i-'a')gate_count; y++){ int print_in1 = circuit->gates[y].in1 + '0'; int print_in2 = circuit->gates[y].in2 + '0'; int print_in3 = circuit->gates[y].in3 + '0'; if((print_in1-2-'0')=0){ print_in1 = circuit->gates[y].in1-2 + 'a'; } if((print_in2-2-'0')=0){ print_in2 = circuit->gates[y].in2-2 + 'a'; } if((print_in3-2-'0')=0){ print_in3 = circuit->gates[y].in3-2 + 'a'; } - - tee(fptr,"%d: %s, in1: %c, in2: %c, in3: %c\n",y+NUM_INPUTS+2,circuit->gates[y].gate->type,print_in1,print_in2,print_in3); + if(circuit->gates[y].in1==1 && circuit->gates[y].in2 == 0){ //Detected inverter + tee(fptr,"%d: INV, in1: %c\n",y+NUM_INPUTS+2,print_in3); + }else{ //normal muxig + tee(fptr,"%d: %s, in1: %c, in2: %c, in3: %c\n",y+NUM_INPUTS+2,circuit->gates[y].gate->type,print_in1,print_in2,print_in3); + } } tee(fptr,"Output "); for(int i='x';(i-'x')gate_count-NUM_OUTPUTS+(i-'x')+2);} tee(fptr,"\n"); tee(fptr,"----------------------------------\n"); fclose(fptr); } void write_circuit_to_file(Circuit * circuit, int area, int worker_number, int file_number){ FILE *fptr; char file_name[100]; - sprintf(file_name, "../output/output_%d_%d_%d_bruteforce.dot", area, worker_number, file_number); + sprintf(file_name, "./output/output_%d_%d_%d_bruteforce.dot", area, worker_number, file_number); fptr = fopen(file_name, "w"); //for(int y=0; ygate_count; y++){ // printf("%d: %s, in1: %d, in2: %d, in3: %d\n",y,circuit->gates[y].gate->type,circuit->gates[y].in1,circuit->gates[y].in2,circuit->gates[y].in3); //} fprintf(fptr, "digraph Circuit {\n rankdir=LR; // Makes the graph left-to-right\n node [shape=ellipse]; // Default shape for nodes\n ranksep=2; // Increases vertical separation\n"); for(int i='a';(i-'a')gate_count; y++){ int print_in1 = circuit->gates[y].in1 + '0'; int print_in2 = circuit->gates[y].in2 + '0'; int print_in3 = circuit->gates[y].in3 + '0'; if((print_in1-2-'0')=0){ print_in1 = circuit->gates[y].in1-2 + 'a'; } if((print_in2-2-'0')=0){ print_in2 = circuit->gates[y].in2-2 + 'a'; } if((print_in3-2-'0')=0){ print_in3 = circuit->gates[y].in3-2 + 'a'; } int unit_number = y+NUM_INPUTS+2; - fprintf(fptr," %d [ shape=record, label=\"{{ in 0| in 1| S}| MUX %d |{ Y}}\", color=\"darkred\", fontcolor=\"darkred\" ];\n",unit_number,unit_number); - fprintf(fptr," %c:e -> %d:p1;\n %c:e -> %d:p2;\n %c:e -> %d:p3;\n",print_in1,unit_number,print_in2,unit_number,print_in3,unit_number); + + if(circuit->gates[y].in1==1 && circuit->gates[y].in2 == 0){ //Detected inverter + fprintf(fptr," %d [ shape=record, label=\"{{ in }|INV %d |{ out}}\", color=\"darkred\", fontcolor=\"darkred\" ];\n",unit_number,unit_number); + fprintf(fptr," %c:e -> %d:p1;\n",print_in3,unit_number); + } else { //normal muxig + fprintf(fptr," %d [ shape=record, label=\"{{ in 0| in 1| S}| MUX %d |{ Y}}\", color=\"darkred\", fontcolor=\"darkred\" ];\n",unit_number,unit_number); + fprintf(fptr," %c:e -> %d:p1;\n %c:e -> %d:p2;\n %c:e -> %d:p3;\n",print_in1,unit_number,print_in2,unit_number,print_in3,unit_number); + } } for(int i='x';(i-'x') %c;\n",NUM_INPUTS+circuit->gate_count-NUM_OUTPUTS+(i-'x')+2,i);} fprintf(fptr,"}\n"); fclose(fptr); } void evaluate_circuit(GateType* all_gates, Circuit* circuit, int8_t* inputs, int8_t* outputs) { int8_t intermediate_outputs[NUM_INPUTS + MAX_GATES+2]; intermediate_outputs[0] = 0; //Make sure that intermediate_outputs[0] = 0 and [1] = 1 for constant signal attachments intermediate_outputs[1] = 1; memcpy(&intermediate_outputs[2], inputs, NUM_INPUTS * sizeof(int8_t)); //copy boolean value over this for (int i = 0; i < circuit->gate_count; i++) { int out1 = intermediate_outputs[circuit->gates[i].in1]; int out2 = intermediate_outputs[circuit->gates[i].in2]; int out3 = intermediate_outputs[circuit->gates[i].in3]; int output = 0; if (circuit->gates[i].gate == &all_gates[0]) //INV output = ~out1 & 1; else if (circuit->gates[i].gate == &all_gates[1]) //MUX output = out3 ? out2 : out1; intermediate_outputs[NUM_INPUTS + i + 2] = output; } for(int z=0; zgate_count-NUM_OUTPUTS+z]; } } int detect_tautology(Circuit *current_circuit, int in1, int in2, int in3, int gate_selected, ThreadArgs *data){ if ((in1 == in2 && gate_selected != 0) || (in1 == in3 || in2 == in3) || (in1 == 0 && in2 == 1 && gate_selected != 0) ){ //|| //Skip gate if it has the same input both ports NOTE THAT IF i == 0 THEN WE SELECT INV. return 1; } for(int i=0; i<(current_circuit->gate_count-1);i++){ if(current_circuit->gates[i].gate == &data->gate_types[gate_selected]){ if(current_circuit->gates[i].in1 == in1 && current_circuit->gates[i].in2 == in2 && current_circuit->gates[i].in3 == in3){ return 1; //DETECTED A COMPLETE equivalent circuit } } } int input_used[current_circuit->gate_count + data->num_inputs+2]; memset(input_used, 0, sizeof(input_used)); input_used[0] = 1; //make sure that the constant don't trigger a faulty tautology result. input_used[1] = 1; for(int i=0; igate_count; i++){ input_used[current_circuit->gates[i].in1] = 1; input_used[current_circuit->gates[i].in2] = 1; input_used[current_circuit->gates[i].in3] = 1; } input_used[in1] = 1; input_used[in2] = 1; input_used[in3] = 1; for(int i=0; i < (current_circuit->gate_count + data->num_inputs - NUM_OUTPUTS+2); i++){ if(input_used[i]==0 && current_circuit->gate_count!=0){ return 2; //missing an used output } } return 0; } void generate_circuits_recursive(Circuit *current_circuit, int depth, ThreadArgs *data) { if (depth == data->num_gates){ // Reached end of amount of gates. return; } GateType* gate_types = data->gate_types; // Loop through gate types and inputs to build possible circuits //int num_gate_types = 1; //int division = (num_gate_types + NUM_THREADS-1)/NUM_THREADS; //int multi_core_division=NUM_THREADS/num_gate_types; //0 - 2, 3 - 5, 6 - 8 //for (int i = 0; i < num_gate_types; i++) { int i = 1; //Only select the multiplexer if((current_circuit->area+data->gate_types[i].area)>data->best_area){ //printf("worker %d: area %d on gate type %d and depth %d larger then best area %d continueing\n",data->worker_id,current_circuit->area,i,depth,data->best_area); return; } for (int in3 = 2; in3 < depth + data->num_inputs + 2; in3++){ //Going for multithread approach if(in3 != data->worker_id+2 && depth == 0){ continue; } for (int in2 = 0; in2 < depth + data->num_inputs + 2; in2++) { for (int in1 = 0; in1 < depth + data->num_inputs + 2; in1++){ data->num_circuit[0] += 1; // Add the new gate to the circuit current_circuit->gates[depth].gate = &gate_types[i]; //set pointer to the type of gate current_circuit->gates[depth].in1 = in1; current_circuit->gates[depth].in2 = in2; current_circuit->gates[depth].in3 = in3; current_circuit->gate_count = depth + 1; //if(current_circuit->gates[0].in1 == 0 && current_circuit->gates[0].in2 == 1 && current_circuit->gates[0].in3 == 3 && current_circuit->gates[1].in1 == 2 && current_circuit->gates[1].in2 == 3 && current_circuit->gates[1].in3 == 4 && current_circuit->gates[2].in1 == 4 && current_circuit->gates[2].in2 == 5 && current_circuit->gates[2].in3 == 6){// && current_circuit->gates[2].gate==&data->gate_types[6]){ //if(current_circuit->gates[0].in1 == 2 && current_circuit->gates[0].in2 == 3 && current_circuit->gates[0].in3 == 4){ // printf("test\n"); //} int tautology = detect_tautology(current_circuit,in1,in2,in3,i,data); //0: nothing found, 1: direct tautology, 2:unconnected device may still be connected. if(tautology==1){ continue; //Found already unnecessary combo and should skip it } int valid = 0; if(tautology!=2){ //There is an unconnected gate if this holds true valid = 1; int8_t output[NUM_OUTPUTS]; for (int y=0; y < (1 << data->num_inputs); y++){ //CHECK IF IT IS VALID evaluate_circuit(data->gate_types, current_circuit, &data->truth_table[y*data->num_inputs], output); for(int z=0; ztarget_outputs[y+NUM_COMBINATION*z]){ valid = 0; } } } } //valid circuit add area current_circuit->area += gate_types[i].area; // Example area increment (modify as needed) if(data->num_circuit[0]%1000000000 == 0){ data->num_circuit[1] += 1; data->num_circuit[0] = 0; printf("%d:At circuit number %d M current best_area %d and tested area %d\n",data->worker_id,data->num_circuit[1],data->best_area,current_circuit->area); } pthread_mutex_lock(&data->mutex); //get mutex if(valid == 1 && current_circuit->areabest_area){ //Found a valid solution! memcpy((void *)&data->best_circuit, current_circuit, sizeof(Circuit)); //write to best circuit printf("%d: Found proper solution\n",data->worker_id); print_circuit(current_circuit); write_circuit_to_file(current_circuit,current_circuit->area,data->worker_id,data->num_circuit[0]*100 + data->num_circuit[1]); data->best_area = current_circuit->area; } pthread_mutex_unlock(&data->mutex); // Recurse to add more gates generate_circuits_recursive(current_circuit, depth + 1, data); current_circuit->area -= gate_types[i].area; // Example area increment (modify as needed) //printf("worker %d: returning with depth %d and area %d\n",data->worker_id,depth,current_circuit->area); } } } } void* search_space_worker(void* args) { // Define and initialize worker-specific parameters and loop through circuits // You will need to pass parameters in `args` and cast them in this function ThreadArgs *data; data = (ThreadArgs *) args; Circuit current_circuit; current_circuit.area = 0; current_circuit.gate_count = 0; printf("%d: best Area %d, Going in recusive loop to check all circuits\n",data->worker_id, data->best_area); generate_circuits_recursive(¤t_circuit, 0, data); //finished set worker_id to 1000 to indicate to the management thread that we finished pthread_mutex_lock(&data->mutex); data->worker_id = 1000; pthread_mutex_unlock(&data->mutex); return NULL; // Return the best found circuit and area as needed } void brute_force_boolean(Circuit* best_circuit, int8_t truth_table[], int8_t target_outputs[], int num_inputs, int max_gates, int max_area) { pthread_t threads[NUM_THREADS]; ThreadArgs thread_args[NUM_THREADS]; // Define `ThreadArgs` to pass data to threads int best_area = max_area; int total_circuits = 0; for (int i = 0; i < NUM_THREADS; i++) { thread_args[i].gate_types = gate_types; thread_args[i].num_inputs = num_inputs; thread_args[i].num_gates = max_gates; thread_args[i].best_area = best_area; thread_args[i].truth_table = truth_table; thread_args[i].target_outputs = target_outputs; thread_args[i].worker_id = i; thread_args[i].num_circuit[0] = 0; thread_args[i].num_circuit[1] = 0; pthread_mutex_init(&thread_args[i].mutex, NULL); pthread_create(&threads[i], NULL, search_space_worker, (void *)&thread_args[i]); } clock_t begin = clock(); int number_of_running_threads = NUM_THREADS; while(number_of_running_threads>0){ number_of_running_threads = NUM_THREADS; for (int i = 0; i < NUM_THREADS; i++) { pthread_mutex_lock(&thread_args[i].mutex); //get lock on the data //Check if it found a better circuit then known before. if(thread_args[i].best_areabest_area){ printf("setting the best_area size %d, on worker: %d\n",best_area,i); thread_args[i].best_area = best_area; } //lastly check if the thread_closed if(thread_args[i].worker_id==1000){ number_of_running_threads -= 1; } pthread_mutex_unlock(&thread_args[i].mutex); // Collect best circuits and area from each thread } clock_t toc = clock(); printf("%f: running number of threads: %d\n",(double)(toc - begin) / (CLOCKS_PER_SEC*number_of_running_threads),number_of_running_threads); sleep(5); } printf("no threads running anymore\n"); // Output the best circuit //count total amount of circuits for(int i=0;i> j) & 1; // Extract each bit of i as an input truth_table[i*num_inputs+j] = (i >> j) & 1;; } target_outputs[i] = target_function(inputs); } } int main() { // Define target function output int8_t target_outputs[NUM_COMBINATION*NUM_OUTPUTS]; // 1< "$temp_file" + else + sed -e "s|#define target_truth_table \"00000000\"|#define target_truth_table \"$binary\"|" \ + -e "s|#define NUM_INPUTS 3|#define NUM_INPUTS $inputs|" \ + -e "s|#define MAX_GATES 2|#define MAX_GATES 3|" \ + "$file" > "$temp_file" + fi + + # Compile and run the generated C file + gcc -pthreads -o bruteforce_muxig_temp "$temp_file" + ./bruteforce_muxig_temp + + # Save the output in a structured directory + mkdir -p "result_${inputs}/${i}_${binary}" + mv ./output/* "result_${inputs}/${i}_${binary}/" + done +done diff --git a/nem_basic_yosys.lib b/nem_liberty/nem_basic_yosys.lib similarity index 100% rename from nem_basic_yosys.lib rename to nem_liberty/nem_basic_yosys.lib diff --git a/nem_basic_yosys_extended.lib b/nem_liberty/nem_basic_yosys_extended.lib similarity index 92% rename from nem_basic_yosys_extended.lib rename to nem_liberty/nem_basic_yosys_extended.lib index 6253d69..9b9d471 100644 --- a/nem_basic_yosys_extended.lib +++ b/nem_liberty/nem_basic_yosys_extended.lib @@ -1,2604 +1,2514 @@ library (nem_basic) { comment : "Manually created liberty with more gates - ignore any timing information"; date : "$April 26th 2024$"; revision : "0.2"; delay_model : table_lookup; capacitive_load_unit (1,pf); time_unit : "1ns"; current_unit : "1uA"; voltage_unit : "1V"; voltage_map (VCC,15); voltage_map (GND,0); default_cell_leakage_power : 0; default_fanout_load : 1; default_max_transition : 500; default_output_pin_cap : 0; input_threshold_pct_rise : 50.0; input_threshold_pct_fall : 50.0; output_threshold_pct_rise : 50.0; output_threshold_pct_fall : 50.0; slew_lower_threshold_pct_rise : 20.0; slew_lower_threshold_pct_fall : 20.0; slew_upper_threshold_pct_rise : 80.0; slew_upper_threshold_pct_fall : 80.0; slew_derate_from_library : 1.0; nom_process : 1; nom_temperature : 125; nom_voltage : 15; operating_conditions (NEM_BASIC_COND) { process : 1; temperature : 125; voltage : 29; } default_operating_conditions : NEM_BASIC_COND; lu_table_template (delay_template_2x2) { variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1("0.01,0.1"); index_2("0.02,0.2"); } lu_table_template (constraint_template_2x2) { variable_1 : constrained_pin_transition; variable_2 : related_pin_transition; index_1("0.01,0.1"); index_2("0.02,0.2"); } cell(inv_3T) { area : 1160; cell_footprint : inv_3T; /* cell_description : "NEM 3T Inverter"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (in) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "!(in)"; max_capacitance : 10; max_fanout : 10; max_transition : 500; timing () { related_pin : "in"; timing_sense : negative_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(buf_3T) { area : 2240; cell_footprint : buf_3T; /* cell_description : "NEM 3T Buffer"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (in) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "in"; max_capacitance : 10; max_fanout : 10; max_transition : 500; timing () { related_pin : "in"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(nand_3T) { area : 2832; cell_footprint : nand_3T; /* cell_description : "NEM 3T 2-Input NAND"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "!(a&b)"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : negative_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : negative_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(and_3T) { area : 3912; cell_footprint : and_3T; /* cell_description : "NEM 3T 2-Input AND"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "a&b"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(nor_3T) { area : 2832; cell_footprint : nor_3T; /* cell_description : "NEM 3T 2-Input NOR"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "!(a|b)"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : negative_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : negative_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(or_3T) { area : 3952; cell_footprint : or_3T; /* cell_description : "NEM 3T 2-Input OR"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "a|b"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(xnor_3T) { area : 7824; cell_footprint : xnor_3T; /* cell_description : "NEM 3T 2-Input XNOR"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "!(a^b)"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(xor_3T) { area : 7824; cell_footprint : xor_3T; /* cell_description : "NEM 3T 2-Input XOR"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "a^b"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(mux_3T) { area : 8000; cell_footprint : mux_3T; /* cell_description : "NEM 3T 2-Input MUX"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } /*bundle(in) { members(in_0,in_1); direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; }*/ pin(in_0){ direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin(in_1){ direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (sel) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "(!sel & in_0) | (sel & in_1)"; max_fanout : 10; timing () { related_pin : "in_0"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "in_1"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "sel"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(mux_4T) { area : 1288; cell_footprint : mux_4T; /* cell_description : "NEM 4T 2-Input MUX"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } /*bundle(in) { members(in_0,in_1); direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; }*/ pin(in_0){ direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin(in_1){ direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (sel) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "(!sel & in_0) | (sel & in_1)"; max_fanout : 10; timing () { related_pin : "in_0"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "in_1"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "sel"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(and_4T) { area : 1288; cell_footprint : and_4T; /* cell_description : "NEM 4T 2-Input AND based on muxiplayers pass logic"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "a&b"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(nand_4T) { area : 2448; cell_footprint : and_4T; /* cell_description : "NEM 4T 2-Input AND based on muxiplayers pass logic"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "!(a&b)"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(and_not_4T) { area : 1288; cell_footprint : and_4T; /* cell_description : "NEM 4T 2-Input AND based on muxiplayers pass logic having inverted input"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "a&!(b)"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(or_4T) { area : 1288; cell_footprint : or_4T; /* cell_description : "NEM 4T 2-Input OR based on muxiplayers pass logic"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "a|b"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(nor_4T) { area : 2448; cell_footprint : or_4T; /* cell_description : "NEM 4T 2-Input NOR based on muxiplayers pass logic"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "a|b"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(or_not_4T) { area : 1288; cell_footprint : or_4T; /* cell_description : "NEM 4T 2-Input OR based on muxiplayers pass logic having inverted input"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "a|!(b)"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(xor_4T) { area : 2448; cell_footprint : xor_3T; /* cell_description : "NEM 4T 2-Input XOR based on 2 4T and 3T inverter"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "a^b"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(xnor_4T) { area : 2448; cell_footprint : xor_3T; /* cell_description : "NEM 4T 2-Input XNOR based on 2 4T and 3T inverter"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "!(a^b)"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } -cell(xor_4T_test) { - area : 1; - cell_footprint : xor_3T; -/* cell_description : "NEM 4T 2-Input XOR based on 2 4T needs an inverted input"; */ - pg_pin (VCC) { - pg_type : primary_power; - voltage_name : "VCC"; - } - pg_pin (GND) { - pg_type : primary_ground; - voltage_name : "GND"; - } - pin (a) { - direction : "input"; - related_ground_pin : GND; - related_power_pin : VCC; - capacitance : 1; - } - pin (b) { - direction : "input"; - related_ground_pin : GND; - related_power_pin : VCC; - capacitance : 1; - } - pin (c) { - direction : "input"; - related_ground_pin : GND; - related_power_pin : VCC; - capacitance : 1; - } - pin (out) { - direction : "output"; - related_ground_pin : GND; - related_power_pin : VCC; - function : "(a&c)|(!(a)&b)"; - max_fanout : 10; - timing () { - related_pin : "a"; - timing_sense : non_unate; - timing_type : combinational; - cell_rise (delay_template_2x2) { - index_1 ("0.01,0.1"); - index_2 ("0.02,0.2"); - values ("0.2,2.0","0.21,2.1"); - } - rise_transition (delay_template_2x2) { - index_1 ("0.01,0.1"); - index_2 ("0.02,0.2"); - values ("0.2,4.0","0.21,4.1"); - } - cell_fall (delay_template_2x2) { - index_1 ("0.01,0.1"); - index_2 ("0.02,0.2"); - values ("0.2,2.0","0.21,2.1"); - } - fall_transition (delay_template_2x2) { - index_1 ("0.01,0.1"); - index_2 ("0.02,0.2"); - values ("0.2,4.0","0.21,4.1"); - } - } - timing () { - related_pin : "b"; - timing_sense : non_unate; - timing_type : combinational; - cell_rise (delay_template_2x2) { - index_1 ("0.01,0.1"); - index_2 ("0.02,0.2"); - values ("0.2,2.0","0.21,2.1"); - } - rise_transition (delay_template_2x2) { - index_1 ("0.01,0.1"); - index_2 ("0.02,0.2"); - values ("0.2,4.0","0.21,4.1"); - } - cell_fall (delay_template_2x2) { - index_1 ("0.01,0.1"); - index_2 ("0.02,0.2"); - values ("0.2,2.0","0.21,2.1"); - } - fall_transition (delay_template_2x2) { - index_1 ("0.01,0.1"); - index_2 ("0.02,0.2"); - values ("0.2,4.0","0.21,4.1"); - } - } - } - pin_opposite("b","c"); -} - /* cell(SR_latch) { area : 2704; cell_footprint : SR_latch; cell_description : "NEM based S-R type Latch"; pin (S) { direction : "input"; } pin (R) { direction : "input"; } pin (Q) { direction : "output"; function : "IQ"; } pin (Q_bar) { direction : "output"; function : "IQB"; } latch (IQ,IQB) { preset : "S" clear : "R" clear_preset_var1 : L; clear_preset_var2 : L; } statetable (" R S ", " IQ IQB "){ table : "H L : - - : L H ,\ L H : - - : H L ,\ H H : - - : L L ,\ L L : - - : N N"; } } */ cell(D_latch) { area : 9448; cell_footprint : D_latch; /* cell_description : "NEM based D type Latch"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (D) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; /* data_in_type : data;*/ /* timing() { related_pin : "EN"; timing_type : hold_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } timing() { related_pin : "EN"; timing_type : setup_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } */ } pin (EN) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (Q) { direction : "output"; function : "QOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; /* timing () { related_pin : "D"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "EN"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } */ } pin (Q_bar) { direction : "output"; function : "QBOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; /* timing () { related_pin : "D"; timing_sense : negative_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "EN"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } */ } latch (QOUT,QBOUT) { enable : "EN"; data_in : "D"; } } cell(D_latch_rst) { area : 13432; cell_footprint : D_latch_rst; /* cell_description : "NEM based D type Latch with reset"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (D) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; /* data_in_type : data;*/ } pin (EN) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (rst) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (Q) { direction : "output"; function : "QOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "D"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "EN"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4darkblue.0","0.21,4.1"); } } } pin (Q_bar) { direction : "output"; function : "QBOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "D"; timing_sense : negative_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "EN"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } latch (QOUT,QBOUT) { enable : "EN"; data_in : "D"; clear : "rst"; } } cell(D_FF) { area : 20056; cell_footprint : D_FF; /* cell_description : "NEM based M-S D type Flip Flop"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (D) { nextstate_type : data; direction : "input"; related_ground_pin : GND; related_power_pin : VCC; max_transition : 0.2; capacitance : 1; timing () { related_pin : "CLK"; timing_type : hold_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } timing () { related_pin : "CLK"; timing_type : setup_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } } pin (CLK) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (Q) { direction : "output"; function : "QOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } pin (Q_bar) { direction : "output"; function : "QBOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } ff (QOUT,QBOUT) { clocked_on : "CLK"; next_state : "D"; } } cell(D_FF_rst) { area : 28184; cell_footprint : D_FF_rst; /* cell_description : "NEM based M-S D type Flip Flop with reset"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (D) { nextstate_type : data; direction : "input"; related_ground_pin : GND; related_power_pin : VCC; max_transition : 0.2; capacitance : 1; timing () { related_pin : "CLK"; timing_type : hold_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } timing () { related_pin : "CLK"; timing_type : setup_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,-4.0","0.21,4.1"); } } } pin (rst) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_type : recovery_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } } timing () { related_pin : "CLK"; timing_type : removal_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } } } pin (CLK) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (Q) { direction : "output"; function : "QOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } pin (Q_bar) { direction : "output"; function : "QBOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } ff (QOUT,QBOUT) { clear : "rst"; clocked_on : "CLK"; next_state : "D"; } } /* SCAN FUNCTIONALITY HASN'T BEEN ADDED YET */ cell(S_FF) { area : 20056; cell_footprint : D_FF; /* cell_description : "NEM based M-S D type Flip Flop with scan functionality";*/ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (D) { nextstate_type : data; direction : "input"; related_ground_pin : GND; related_power_pin : VCC; max_transition : 0.2; capacitance : 1; timing () { related_pin : "CLK"; timing_type : hold_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } timing () { related_pin : "CLK"; timing_type : setup_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } } pin (SI) { nextstate_type : data; direction : "input"; related_ground_pin : GND; related_power_pin : VCC; max_transition : 0.2; capacitance : 1; timing () { related_pin : "CLK"; timing_type : hold_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } timing () { related_pin : "CLK"; timing_type : setup_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } } pin (CLK) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (Q) { direction : "output"; function : "QOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } pin (Q_bar) { direction : "output"; function : "QBOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } ff (QOUT,QBOUT) { clocked_on : "CLK"; next_state : "D"; } } /* SCAN FUNCTIONALITY HASN'T BEEN ADDED YET */ cell(S_FF_rst) { area : 28184; cell_footprint : S_FF_rst; /* cell_description : "NEM based M-S D type Flip Flop with reset and scan functionality"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (D) { nextstate_type : data; direction : "input"; related_ground_pin : GND; related_power_pin : VCC; max_transition : 0.2; capacitance : 1; timing () { related_pin : "CLK"; timing_type : hold_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } timing () { related_pin : "CLK"; timing_type : setup_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,-4.0","0.21,4.1"); } } } pin (rst) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_type : recovery_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } } timing () { related_pin : "CLK"; timing_type : removal_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } } } pin (CLK) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (Q) { direction : "output"; function : "QOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } pin (Q_bar) { direction : "output"; function : "QBOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } ff (QOUT,QBOUT) { clear : "rst"; clocked_on : "CLK"; next_state : "D"; } } } diff --git a/nem_basic_yosys_extended_old.lib b/nem_liberty/nem_basic_yosys_extended_old.lib similarity index 100% rename from nem_basic_yosys_extended_old.lib rename to nem_liberty/nem_basic_yosys_extended_old.lib diff --git a/nem_basic_yosys_restricted.lib b/nem_liberty/nem_basic_yosys_restricted.lib similarity index 100% rename from nem_basic_yosys_restricted.lib rename to nem_liberty/nem_basic_yosys_restricted.lib diff --git a/plugins/abc.help b/plugins/abc.help new file mode 100644 index 0000000..5dbf3d8 --- /dev/null +++ b/plugins/abc.help @@ -0,0 +1,6535 @@ +ABC command line: "help -d". + + Welcome to ABC compiled on Sep 4 2024 02:05:06! + +ABC9 commands: + &acec &add1hot &addflop &anorm + &append &atree &b &back_reach + &bcore &bidec &blut &bmc + &bmci &bmcs &bmiter &brecover + &cec &cexinfo &cfraig &cfs + &chainbmc &choice &cof &compare + &cone &cycle &dc2 &dch + &decla &deepsyn &demiter &dfs + &dsd &dsdb &dsdinfo &edge + &embed &enable &equiv &equiv2 + &equiv3 &equiv_filter &equiv_mark &era + &esop &exorcism &extract &fadds + &false &fftest &filter &flow + &flow2 &flow3 &force &fraig + &frames &funabs &funtrace &fx + &gen &gen_hie &gencex &genmux + &genqbf &genrel &get &glucose + &glucose2 &gprove &homoqbf &icec + &icheck &if &if2 &iff + &iiff &inse &iso &isonpn + &isost &iwls21test &jf &kf + &lcorr &lf &lneteval &lnetmap + &lnetopt &lnetread &lnetsim &load + &load2 &loadaig &maxi &mesh + &mf &mfs &mfsd &miter + &miter2 &mlgen &mltest &move_names + &mprove &mulfind &muxdec &muxpos + &muxstr &nf &odc &of + &pack &permute &pfan &pms + &polyn &popart &posplit &poxsim + &print_truth &prodadd &profile &ps + &psig &put &putontop &qbf + &qvar &r &reachm &reachn + &reachp &reachy &read &read_blif + &read_cblif &read_stg &read_ver &reduce + &reshape &resim &resub &retime + &reveng &rex2gia &rexwalk &rpm + &sat &satclp &satenum &satfx + &satlut &satsyn &sattest &save + &save2 &saveaig &scl &scorr + &semi &setregnum &show &shrink + &sif &sim &sim2 &sim3 + &sim_gen &sim_print &sim_read &sim_write + &simrsb &slice &sopb &speci + &speedup &splitprove &splitsat &sprove + &srm &srm2 &st &status + &stochsyn &str_eco &struct &sweep + &syn2 &syn3 &syn4 &synch2 + &test × &topand &trace + &transduction &transtoch &trim &ttopt + &uif &unate &undo &unmap + &verify &w &window &wlut + &write &write_ver + +usage: &acec [-CT num] [-mdtbvh] + combinational equivalence checking for arithmetic circuits + -C num : the max number of conflicts at a node [default = 1000] + -T num : approximate runtime limit in seconds [default = 0] + -m : toggle miter vs. two circuits [default = two circuits] + -d : toggle using dual output miter [default = no] + -t : toggle using two-word miter [default = no] + -b : toggle working with Booth multipliers [default = no] + -v : toggle verbose output [default = no] + -h : print the command usage + file1 : (optional) the file with the first network + file2 : (optional) the file with the second network + +usage: &add1hot [-vh] + adds 1-hotness constraints as additional primary outputs + -v : toggle printing verbose information [default = yes] + -h : print the command usage + +usage: &addflop [-vh] + adds one flop to the design + -v : toggles printing verbose information [default = no] + -h : print the command usage + +usage: &anorm [-bvh] + normalize adder trees in the current AIG + -b : toggles working with Booth multipliers [default = no] + -v : toggles printing verbose information [default = no] + -h : print the command usage + +usage: &append [-vh] + appends to the current AIG using new PIs and POs + -v : toggle printing verbose information [default = no] + -h : print the command usage + : AIGER file with the design to miter + +usage: &atree [-ecvwh] + extracts adder tree rooting in primary outputs + -e : toggles adding extra outputs [default = no] + -c : toggles duplicating complete AIG [default = no] + -v : toggles printing verbose information [default = no] + -w : toggles printing very verbose information [default = no] + -h : print the command usage + +usage: &b [-N num] [-dasvwh] + performs AIG balancing to reduce delay and area + -N num : the max fanout count to skip a divisor [default = 1000000000] + -d : toggle delay only balancing [default = no] + -a : toggle using AND instead of AND/XOR/MUX [default = no] + -s : toggle strict control of area in delay-mode ("&b -d") [default = no] + -v : toggle printing verbose information [default = no] + -w : toggle printing additional information [default = no] + -h : print the command usage + +usage: &back_reach [-FCT ] [-vh] + performs backward reachability by circuit cofactoring + -F num : the limit on the depth of induction [default = 1000000] + -C num : the conflict limit at a node during induction [default = 1000000] + -T num : the timeout for property directed reachability [default = 10] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &bcore [-FOTV num] [-vh] + records UNSAT core of the BMC instance + -F num : the zero-based index of a timeframe [default = 10] + -O num : the zero-based index of a primary output [default = 0] + -T num : approximate timeout in seconds [default = 0] + -V file: file name with AIG IDs of pivot variables [default = no pivots] + -v : toggle printing verbose information [default = no] + -h : print the command usage + : file name to write the resulting proof [default = stdout] + +usage: &bidec [-vh] + performs heavy rewriting of the AIG + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &blut [-KC num] [-mravh] + performs AIG balancing for the given LUT size + -K num : LUT size for the mapping (2 <= K <= 6) [default = 6] + -C num : the max number of priority cuts (1 <= C <= 8) [default = 8] + -m : toggle performing MUX restructuring [default = yes] + -r : toggle performing recursive restructuring [default = yes] + -a : toggle performing area-oriented restructuring [default = yes] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &bmc [-SFATK num] [-dscvwh] + performs bounded model checking + -S num : the starting timeframe [default = 0] + -F num : the maximum number of timeframes [default = 0] + -A num : the number of additional frames to unroll [default = 50] + -T num : approximate timeout in seconds [default = 0] + -K num : the maximum cut size for CNF computation [default = 6] + -d : toggle dumping unfolded timeframes [default = no] + -s : toggle synthesizing unrolled timeframes [default = no] + -c : toggle using old CNF computation [default = no] + -v : toggle printing verbose information [default = no] + -w : toggle printing information about unfolding [default = no] + -h : print the command usage + +usage: &bmci [-FWT num] [-svh] + experimental procedure + -F num : the number of timeframes [default = 1000] + -W num : the number of machine words [default = 1000] + -T num : approximate global runtime limit in seconds [default = 0] + -s : toggles using ternary simulation [default = no] + -v : toggles printing verbose information [default = no] + -h : print the command usage + +usage: &bmcs [-PCFAT num] [-gevwh] + performs bounded model checking + -P num : the number of parallel solvers [default = 1] + -C num : the SAT solver conflict limit [default = 0] + -F num : the maximum number of timeframes [default = 0] + -A num : the number of additional frames to unroll [default = 1] + -T num : approximate timeout in seconds [default = 0] + -g : toggle using Glucose 3.0 by Gilles Audemard and Laurent Simon [default = Satoko] + -e : toggle using variable eliminatation [default = no] + -v : toggle printing verbose information [default = no] + -w : toggle printing information about unfolding [default = no] + -h : print the command usage + +usage: &bmiter -I [-vh] + creates the boundary miter + -I : number of boundary inputs + -v : toggles printing verbose information [default = no] + -h : print the command usage + : the implementation file + +usage: &brecover -I [-vh] + recover boundary using SAT-Sweeping + -v : toggles printing verbose information [default = no] + -h : print the command usage + -k : toggle using logic cones in the SAT solver [default = no] + -C num : the max number of conflicts at a node [default = 1000000] + -e : toggle checking the equivalence of the result [default = yes] + -o : toggle checking the equivalence of the outsides in verbose [default = yes] + : the implementation aig. (should be equivalent to spec) + : the modified spec. (should be a hierarchical AIG) + +usage: &cec [-CT num] [-nmdasxytvwh] + new combinational equivalence checker + -C num : the max number of conflicts at a node [default = 1000] + -T num : approximate runtime limit in seconds [default = 0] + -n : toggle using naive SAT-based checking [default = no] + -m : toggle miter vs. two circuits [default = two circuits] + -d : toggle using dual output miter [default = no] + -a : toggle writing dual-output miter [default = no] + -s : toggle silent operation [default = no] + -x : toggle using new solver [default = no] + -y : toggle using new solver [default = no] + -t : toggle using simulation [default = no] + -v : toggle verbose output [default = no] + -w : toggle printing SAT solver statistics [default = no] + -h : print the command usage + +usage: &cexinfo [-vh] + prints information about the current counter-example + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &cfraig [-WC ] [-acvh] + performs combinational SAT sweeping under constraints + which are present in the AIG or set manually using "constr" + (constraints are listed as last POs and true when they are 0) + -W num : the number of simulation words [default = 1] + -C num : the max number of conflicts at a node [default = 1000] + -a : toggle appending constraints to the result [default = no] + -c : toggle performing internal verification [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &cfs [-LNURPrcdvh] + performs simulation + -L num : the limit on the number of occurrences [default = 0] + -N num : the number of repetions of each pattern [default = 1] + -U num : what to do with unseen patterns [default = 2] + -R num : what to do with rare patterns [default = 2] + -P num : base2-log of ramdom flip probability [default = 0.000000] + -r : toggle replacing rare patterns [default = no] + -c : toggle inserting constants [default = no] + -d : toggle using only DAG nodes [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &chainbmc [-FC ] [-vwh] + runs a specialized flavor of BMC + -F : the max number of timeframes (0 = unused) [default = 200] + -C : the max number of conflicts (0 = unused) [default = 0] + -v : toggle printing verbose information [default = no] + -w : toggle printing even more information [default = no] + -h : print the command usage + +usage: &choice [-C num] [-cvh] + performs computation of structural choices + -C num : the max number of conflicts at a node [default = 1000] + -c : toggle using circuit-based SAT solver [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &cof [-VCLN num] [-vh] + performs cofactoring w.r.t. variable(s) + -V num : the zero-based ID of one variable to cofactor [default = 0] + -C num : cofactor one variable with a given constant (0 or 1) [default = unused] + -L num : cofactor vars with fanout count higher than this [default = 0] + -N num : cofactoring the given number of last input variables [default = 0] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &compare [-fvh] + compared two AIGs for structural similarity + -f : toggle functional comparison [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &cone [-ORPLW num] [-aecvh] + extracting multi-output sequential logic cones + -O num : the index of first PO to extract [default = -1] + -R num : (optional) the number of outputs to extract [default = 1] + -P num : (optional) the partition number to extract [default = -1] + -L num : (optional) extract cones with higher level [default = 0] + -W num : (optional) extract cones falling into this window [default = 0] + -a : toggle keeping all CIs or structral support only [default = structural] + -e : toggle writing all outputs into individual files [default = no] + -c : toggle performing cone extraction combinationally [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &cycle [-F num] [-cvh] + cycles sequential circuit for the given number of timeframes + to derive a new initial state (which may be on the envelope) + -F num : the number of frames to simulate [default = 10] + -c : toggle using PI values from the current CEX [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &dc2 [-lvh] + performs heavy rewriting of the AIG + -l : toggle level update during rewriting [default = yes] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &dch [-WCS num] [-sptfremngcxyvh] + computes structural choices using a new approach + -W num : the max number of simulation words [default = 8] + -C num : the max number of conflicts at a node [default = 1000] + -S num : the max number of SAT variables [default = 5000] + -s : toggle synthesizing three snapshots [default = yes] + -p : toggle power-aware rewriting [default = no] + -t : toggle simulation of the TFO classes [default = yes] + -f : toggle using lighter logic synthesis [default = no] + -r : toggle skipping choices with redundant support [default = no] + -e : toggle computing and merging equivalences [default = no] + -m : toggle minimizing logic level after merging equivalences [default = no] + -n : toggle selecting random choices while merging equivalences [default = no] + -g : toggle using GIA to prove equivalences [default = no] + -c : toggle using circuit-based SAT vs. MiniSat [default = no] + -x : toggle using new choice computation [default = no] + -y : toggle using new choice computation [default = no] + -v : toggle verbose printout [default = no] + -h : print the command usage + +usage: &decla [-bvh] + removes carry look ahead adders + -b : toggles working with Booth multipliers [default = no] + -v : toggles printing verbose information [default = no] + -h : print the command usage + +usage: &deepsyn [-IJTAS ] [-tvh] + performs synthesis + -I : the number of iterations [default = 1] + -J : the number of steps without improvements [default = 1000000000] + -T : the timeout in seconds (0 = no timeout) [default = 0] + -A : the number of nodes to stop (0 = no limit) [default = 0] + -S : user-specified random seed (0 <= num <= 100) [default = 0] + -t : toggle using two-input LUTs [default = no] + -v : toggle printing optimization summary [default = no] + -h : print the command usage + +usage: &demiter [-ftdvh] + decomposes a miter (by default, tries to extract an OR gate) + -f : write files with two sides of a dual-output miter [default = no] + -t : write files with two sides of a two-word miter [default = no] + -d : take single-output and decompose into dual-output [default = no] + -v : toggles printing verbose information [default = no] + -h : print the command usage + +usage: &dfs [-nfolvh] + orders objects in the DFS order + -n : toggle using normalized ordering [default = no] + -f : toggle using reverse fanin traversal order [default = no] + -o : toggle using reverse output traversal order [default = no] + -l : toggle using levelized order [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &dsd [-vh] + performs DSD-based collapsing + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &dsdb [-LWKCR num] [-vh] + performs DSD balancing + -L num : optimize paths above this level [default = 0] + -W num : optimize paths falling into this window [default = 0] + -K num : the number of LUT inputs (LUT size) [default = 6] + -C num : the number of cuts at a node [default = 8] + -R num : the delay relaxation ratio (num >= 0) [default = 0] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &dsdinfo [-V num] [-dvh] + computes and displays information related to DSD + -V num : the zero-based index of the input variable [default = -1] + -d : toggles showing DSD structure [default = no] + -v : toggles printing verbose information [default = no] + -h : print the command usage + +usage: &edge [-CDFE num] [-rpomdvh] + find edge assignment of the LUT-mapped network + -C num : the SAT solver conflict limit (0 = unused) [default = 0] + -D num : the upper bound on delay [default = 0] + -F num : skip using edge if fanout higher than this [default = 0] + -E num : the limit on the number of edges (1 <= num <= 2) [default = 1] + -r : toggles using reverse order [default = no] + -p : toggles deriving edges from packing [default = no] + -o : toggles using old algorithm [default = no] + -m : toggles combining edge assignment with mapping [default = no] + -d : toggles dynamic addition of clauses [default = yes] + -v : toggles verbose output [default = no] + -h : prints the command usage + +usage: &embed [-DI ] [-rdlscvh] + fast placement based on high-dimensional embedding from + D. Harel and Y. Koren, "Graph drawing by high-dimensional + embedding", J. Graph Algs & Apps, 2004, Vol 8(2), pp. 195-217 + -D num : the number of dimensions for embedding [default = 30] + -I num : the number of refinement iterations [default = 10] + -r : toggle the use of refinement [default = no] + -c : toggle clustered representation [default = no] + -d : toggle dumping placement into a Gnuplot file [default = no] + -l : toggle dumping Gnuplot for large placement [default = no] + -s : toggle showing image if Gnuplot is installed [default = no] + -v : toggle verbose output [default = no] + -h : print the command usage + +usage: &enable [-rvh] + adds or removes flop enable signals + -r : toggle adding vs. removing enables [default = add] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &equiv [-WFRST num] [-smdvh] + computes candidate equivalence classes + -W num : the number of words to simulate [default = 31] + -F num : the number of frames to simulate [default = 100] + -R num : the max number of simulation rounds [default = 20] + -S num : the max number of rounds w/o refinement to stop [default = 3] + -T num : approximate runtime limit in seconds [default = 0] + -s : toggle seq vs. comb simulation [default = no] + -m : toggle miter vs. any circuit [default = circuit] + -d : toggle using two POs instead of XOR [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &equiv2 [-FCRTS num] [-xlvh] + computes candidate equivalence classes + -F num : the max number of frames for BMC [default = 20] + -C num : the max number of conflicts at a node [default = 500] + -R num : the max number of BMC rounds [default = 10] + -T num : runtime limit in seconds for all rounds [default = 0] + -S num : runtime limit in seconds for one round [default = 0] + -x : toggle using the current cex to perform refinement [default = no] + -l : toggle considering only latch output equivalences [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &equiv3 [-FWRSNT num] [-mxlvh] + computes candidate equivalence classes + -F num : the max number of frames for BMC [default = 20] + -W num : the number of words to simulate [default = 50] + -R num : the max number of simulation rounds [default = 0] + -S num : the number of rounds before a restart [default = 0] + -N num : random number seed (1 <= num <= 1000) [default = 0] + -T num : runtime limit in seconds for all rounds [default = 0] + -m : toggle miter vs. any circuit [default = circuit] + -x : toggle using the current CEX to perform refinement [default = no] + -l : toggle considering only latch output equivalences [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &equiv_filter [-vh] + filters equivalence candidates after disproving some SRM outputs + (the array of disproved outputs should be given as pAbc->vAbcObjIds) + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &equiv_mark [-fvh] + marks equivalences using an external miter + -f : toggle the use of filtered equivalences [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + : file with the external miter to read + + The external miter should be generated by &srm -s + and (partially) solved by any verification engine(s). + The external miter should have as many POs as + the number of POs in the current AIG plus + the number of equivalences in the current AIG. + If some POs are proved, the corresponding equivs + are marked as proved, to be reduced by &reduce. + +usage: &era [-S num] [-mcdvh] + explicit reachability analysis for small sequential AIGs + -S num : the max number of states (num > 0) [default = 1000000000] + -m : stop when the miter output is 1 [default = no] + -c : use state cubes instead of state minterms [default = yes] + -d : toggle dumping STG into a file [default = no] + -v : print verbose information [default = no] + -h : print the command usage + +usage: &esop [-vh] + derives Exclusive Sum of Products from AIG + -v : toggles printing verbose information [default = no] + -h : print the command usage + +usage: &exorcism [-Q N] [-V N] [-C N] -q [file_in] + performs heuristic exclusive sum-of-project minimization + -Q N : minimization quality [default = 2] + increasing this number improves quality and adds to runtime + -V N : verbosity level [default = 0] + 0 = no output; 1 = outline; 2 = verbose + -C N : maximum number of cubes in startign cover [default = 20000] + -q : toggle using quantum cost [default = no] + [file_in] : optional input file in ESOP-PLA format (otherwise current AIG is used) + : output file in ESOP-PLA format + + +usage: &extract [-K ] [-vh] + extract shared logic for XOR-rich circuits + -K : the minimum gate size to consider for extraction [default = 3] + -a : toogle extracting ANDs instead of XORs [default = no] + -v : print verbose information [default = no] + -h : print the command usage + +usage: &fadds [-NBSLP num] [-nafxvh] + detects full-adder chains and puts them into white boxes + -n : toggles detecting natural full-adder chains [default = no] + -N num : minimum length of a natural full-adder chain to detect [default = 3] + -a : toggles detecting artificial full-adder chains [default = no] + -B num : full-adder box delay (percentage of AND-gate delay) [default = 0] + -S num : minimum length of an artificial full-adder chain [default = 3] + -L num : maximum length of an artificial full-adder chain [default = 32] + -P num : maximum number of artificial full-adder chains to detect [default = 50] + -f : toggles allowing external fanouts in artificial chains [default = no] + -x : toggles using XOR to generate fanouts in artificial chains [default = no] + -b : toggles ignoring boxes when computing delays [default = no] + -v : toggles printing verbose information [default = no] + -h : print the command usage + +usage: &false [-ST num] [-vwh] + detecting and elimintation false paths + -S num : maximum slack to identify false paths [default = 0] + -T num : approximate runtime limit in seconds [default = 0] + -v : toggle printing verbose information [default = no] + -w : toggle printing additional information [default = no] + -h : print the command usage + +usage: &fftest [-ATNK num] [-kbsfcdeunvh] [-GF file] [-S str] + performs functional fault test generation + -A num : selects fault model for all gates [default = 0] + 0: fault model is not selected (use -S str) + 1: delay fault testing for sequential circuits + 2: traditional stuck-at fault: -S (((a&b)&~p)|q) + 3: complement fault: -S ((a&b)^p) + 4: functionally observable fault + -T num : specifies approximate runtime limit in seconds [default = 0] + -N num : specifies iteration to check for fixed parameters [default = 0] + -K num : specifies cardinality constraint (num > 0) [default = unused] + -k : toggles non-strict cardinality (n <= K, instead of n == K) [default = no] + -b : toggles testing for single faults (the same as "-K 1") [default = no] + -s : toggles starting with the all-0 and all-1 patterns [default = no] + -f : toggles faults at flop inputs only with "-A 1" and "-S str" [default = no] + -c : toggles checking if there are untestable faults [default = no] + -d : toggles dumping test patterns into file "_tests.txt" [default = no] + -e : toggles dumping test pattern pairs (delay faults only) [default = no] + -u : toggles dumping untestable faults into "_untest.txt" [default = no] + -n : toggles dumping faults not detected by a given test set [default = no] + -v : toggles printing verbose information [default = no] + -h : print the command usage + : (optional) file name with input test patterns + + -G file : (optional) file name with the golden model + + -F file : (optional) file name with the fault model in BLIF format + -S str : (optional) string representing the fault model + The following notations are used: + Functional variables: {a,b} (both a and b are always present) + Parameter variables: {p,q,r,s,t,u,v,w} (any number from 1 to 8) + Boolean operators: AND(&), OR(|), XOR(^), MUX(?:), NOT(~) + Parentheses should be used around each operator. Spaces not allowed. + Complement (~) is only allowed before variables (use DeMorgan law). + Examples: + (((a&b)&~p)|q) stuck-at-0/1 at the output + (((a&~p)|q)&b) stuck-at-0/1 at input a + (((a|p)&(b|q))&~r) stuck-at-1 at the inputs and stuck-at-0 at the output + (((a&~p)&(b&~q))|r) stuck-at-0 at the inputs and stuck-at-1 at the output + ((a&b)^p) complement at the output + (((a^p)&(b^q))^r) complement at the inputs and at the output + (a?(b?~s:r):(b?q:p)) functionally observable fault at the output + (p?(a|b):(a&b)) replace AND by OR + If the BLIF file is used for the formula with option '-F', following rules apply: + - the network should be combinational and have exactly one primary output + - input names should have only one character: + {a, b} (for functional variables) + {p,q,r,s,t,u,v,w} (for parameter variables) + +usage: &filter [-fgivh] + performs filtering of equivalence classes + (if Parts A/B are given, removes classes composed of one part) + -f : toggle removing all elements except flops [default = no] + -g : toggle removing classes without flops [default = no] + -i : toggle using flop inputs instead of flop outputs [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &flow [-KC num] [-tmvh] + integration optimization and mapping flow + -K num : the number of LUT inputs (LUT size) [default = 6] + -C num : the number of cuts at a node [default = 8] + -t : toggle minimizing average rather than max delay [default = no] + -m : toggle using "mfs2" in the script [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &flow2 [-KC num] [-btmvh] + integration optimization and mapping flow + -K num : the number of LUT inputs (LUT size) [default = 6] + -C num : the number of cuts at a node [default = 8] + -b : toggle using SOP balancing during synthesis [default = no] + -t : toggle minimizing average (not maximum) level [default = no] + -m : toggle using "mfs2" in the script [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &flow3 [-KC num] [-btmlvh] + integration optimization and mapping flow + -K num : the number of LUT inputs (LUT size) [default = 6] + -C num : the number of cuts at a node [default = 8] + -b : toggle using SOP balancing during synthesis [default = no] + -t : toggle minimizing average (not maximum) level [default = no] + -m : toggle using "mfs2" in the script [default = yes] + -l : toggle using previously entered LUT library [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &force [-I ] [-cvh] + one-dimensional placement algorithm FORCE introduced by + F. A. Aloul, I. L. Markov, and K. A. Sakallah (GLSVLSI�03). + -I num : the number of refinement iterations [default = 20] + -c : toggle clustered representation [default = yes] + -v : toggle verbose output [default = yes] + -h : print the command usage + +usage: &fraig [-JWRILDCNPM ] [-F filename] [-rmdckngxysopwvh] + performs combinational SAT sweeping + -J num : the solver type [default = 2] + -W num : the number of simulation words [default = 4] + -R num : the number of simulation rounds [default = 10] + -I num : the number of sweeping iterations [default = 2000] + -L num : the max number of levels of nodes to consider [default = 0] + -D num : the max number of steps of speculative reduction [default = 0] + -C num : the max number of conflicts at a node [default = 1000000] + -N num : the min number of calls to recycle the solver [default = 500] + -P num : the number of pattern generation iterations [default = 100] + -M num : the node count limit to call the old sweeper [default = 0] + -F file: the file name to dump primary output information [default = none] + -r : toggle the use of AIG rewriting [default = no] + -m : toggle miter vs. any circuit [default = circuit] + -d : toggle using double output miters [default = no] + -c : toggle using circuit-based solver [default = no] + -k : toggle using logic cones in the SAT solver [default = no] + -n : toggle using new implementation [default = no] + -g : toggle using another new implementation [default = no] + -x : toggle using another new implementation [default = no] + -y : toggle using another new implementation [default = no] + -s : toggle dumping equivalences into a file [default = no] + -o : toggle using the old SAT sweeper [default = no] + -p : toggle trying to prove when running the old SAT sweeper [default = no] + -w : toggle printing even more verbose information [default = no] + -q : toggle printing additional information for boundary miters [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &frames [-FL ] [-soibavh] + unrolls the design for several timeframes + -F num : the number of frames to unroll [default = 32] + -L num : the limit on fanout count of resets/enables to cofactor [default = 0] + -s : toggle disabling structural hashing [default = no] + -o : toggle ORing corresponding POs [default = no] + -i : toggle initializing registers [default = no] + -b : toggle computing special AIG for BMC [default = no] + -a : toggle using new algorithm [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &funabs [-KR num] [-epvh] ... + generates an abstraction of the function + -K num : the number of primary inputs [default = 6] + -R num : the number of random K-set to try [default = 0] + -e : toggles enumerating bound sets of the given size [default = no] + -p : toggles printing statistics only [default = no] + -v : toggles printing verbose information [default = no] + -h : print the command usage + : the index list of primary inputs to be abstrated + +usage: &funtrace [-C num] [-vh] + traces the presence of the function in the current AIG + -C num : the number of cuts to compute at each node [default = 8] + -v : toggles printing verbose information [default = no] + -h : print the command usage + : truth table in the hexadecimal notation + +usage: &fx [-NM ] [-vh] + extract shared logic using the classical "fast_extract" algorithm + -N : max number of divisors to extract during this run [default = 1000000] + -M : upper bound on literal count of divisors to extract [default = 0] + -r : reversing variable order during ISOP computation [default = no] + -v : print verbose information [default = no] + -w : toggle printing additional information [default = no] + -h : print the command usage + +usage: &gen [-AKNDLBMxvh] + generates network + -A num : the generation algorithm [default = 0] + -K num : the number of LUT inputs [default = 6] + -N num : the number of LUTs on one level [default = 256] + -D num : the number of LUT levels [default = 8] + -L num : limit below which we randomize [default = 0] + -B num : select best fanins among this many tries [default = 1] + -M num : the multiplier type (1=array, 2=booth) [default = 0] + -x : toggle using XOR gates [default = yes] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &gen_hie [-F ] [-vh] ... + generates a hierarchical design in Verilog + -F : the output file name (optional) [default = "sandwich.v"] + -v : toggles printing verbose information [default = no] + -h : print the command usage + : the AIG files for the instance modules + (the PO count of should not be less than the PI count of ) + +usage: &gencex [-CM num] [-F file] [-stcvh] + generates satisfying assignments for each output of the miter + -C num : the number of timeframes [default = 1] + -M num : the max simulation runs before using SAT [default = 10] + -F file : the output file name [default = cexes.txt] + -s : toggles using reverse simulation [default = 1640539552] + -t : toggles using SAT solving [default = 1640539552] + -c : toggles outputing care literals only [default = 1640429008] + -v : toggles printing verbose information [default = 1640429008] + -h : print the command usage + +usage: &genmux [-K ] [-vh] + generates the multiplexer + -K num : the number of control inputs [default = undefined] + -v : toggles printing verbose information [default = no] + -h : print the command usage + string : the sizes of control input groups + +usage: &genqbf [-FKN num] [-ovh] + generates QBF miter for computing an inductive invariant + -F num : the number of time frames for induction [default = 1] + -K num : the LUT size [default = 6] + -N num : the number of LUTs [default = 1] + -o : toggle using the last output [default = no] + -v : toggle verbose output [default = no] + -h : print the command usage + +usage: &genrel [-I n1,n2,...nN] [-O m1,m2,...,mM] [-vh] + generates Boolean relation for the given logic window + -I list : comma-separated list of window inputs [default = undefined] + -O list : comma-separated list of window outputs [default = undefined] + -v : toggles printing verbose information [default = 1640429008] + -h : print the command usage + : the output file name (PLA format extended to represented Boolean relations) + +usage: &get [-cmnvh] + converts the current network into GIA and moves it to the &-space + (if the network is a sequential logic network, normalizes the flops + to have const-0 initial values, equivalent to "undc; st; zero") + -c : toggles allowing simple GIA to be imported [default = no] + -m : toggles preserving the current mapping [default = no] + -n : toggles saving CI/CO names of the AIG [default = no] + -v : toggles additional verbose output [default = no] + -h : print the command usage + : the file name + +usage: &glucose [-C num] [-pdvh] + run Glucose 3.0 by Gilles Audemard and Laurent Simon + -C num : conflict limit [default = 0] + -p : enable preprocessing [default = 1] + -d : enable dumping CNF after proprocessing [default = 0] + -v : verbosity [default = 0] + -h : print the command usage + : (optional) CNF file to solve + +usage: &glucose2 [-C num] [-pvh] + run Glucose 3.0 by Gilles Audemard and Laurent Simon + -C num : conflict limit [default = 0] + -p : enable preprocessing [default = 1] + -v : verbosity [default = 0] + -h : print the command usage + : (optional) CNF file to solve + +usage: &gprove [-GS num] [-vh] + proves multi-output testcase by splitting outputs into groups + (currently, group size more than one works only for "bmc3" and "pdr") + -G num : the size of one group [default = 1] + -S str : the command line to be executed for each group [default = none] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &homoqbf [-KN num] [-vh] + generates QBF miter for the encoding problem + -K num : the LUT size [default = 2] + -N num : the number of LUTs [default = 3] + -v : toggle verbose output [default = no] + -h : print the command usage + +usage: &icec [-CT num] [-axvwh] + combinational equivalence checker for inverse circuits + -C num : the max number of conflicts at a node [default = 1000] + -T num : approximate runtime limit in seconds [default = 0] + -a : toggle writing the miter [default = no] + -x : toggle using new solver [default = no] + -v : toggle verbose output [default = no] + -w : toggle printing SAT solver statistics [default = no] + -h : print the command usage + +usage: &icheck [-MT num] [-esrbdvh] + performs specialized induction check + -M num : the number of timeframes used for induction [default = 1] + -T num : approximate global runtime limit in seconds [default = 0] + -e : toggle using empty set of next-state functions [default = no] + -s : toggle searching for a minimal subset [default = yes] + -r : toggle searching in the reverse order [default = no] + -b : toggle searching in backward order from POs [default = no] + -d : toggle printing out the resulting set [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +Error: Empty GIA network. + +usage: &if2 [-KCD num] [-tmzrcuxvwh] + performs technology mapping of the network + -K num : sets the LUT size for the mapping [default = 6] + -C num : the max number of priority cuts (0 < num < 2^12) [default = 8] + -D num : sets the delay constraint for the mapping [default = best possible] + -t : enables using AND/XOR/MUX nodes instead of simple AIG [default = no] + -m : enables cut minimization by removing vacuous variables [default = no] + -z : toggles deriving LUTs when mapping into LUT structures [default = no] + -r : toggles using one round of mapping [default = no] + -c : toggles mapping for CNF computation [default = no] + -u : toggles mapping for AIG computation [default = no] + -x : toggles mapping for standard cells [default = no] + -v : toggles verbose output [default = no] + -w : toggles very verbose output [default = no] + -h : prints the command usage + +usage: &iff [-vh] + performs structural mapping into LUT structures + -v : toggle printing optimization summary [default = no] + -h : print the command usage + +usage: &iiff [-KC num] [-gclvh] + performs techology mapping + -K num : the maximum LUT size [default = 8] + -C num : the maximum cut count [default = 12] + -g : toggle using gates [default = no] + -c : toggle using cells [default = no] + -l : toggle using LUTs [default = no] + -v : toggle verbose output [default = no] + -h : print the command usage + : (optional) output file name + +usage: &inse [-FWT num] [-svh] + experimental procedure + -F num : the number of timeframes [default = 10] + -W num : the number of machine words [default = 1000] + -T num : approximate global runtime limit in seconds [default = 0] + -s : toggles using ternary simulation [default = no] + -v : toggles printing verbose information [default = no] + -h : print the command usage + +usage: &iso [-neqdvwh] + removes POs with isomorphic sequential COI + -n : toggle using new fast algorithm [default = yes] + -e : toggle computing lower bound on equivalence classes [default = no] + -q : toggle improving quality at the expense of runtime [default = no] + -d : toggle treating the current AIG as a dual-output miter [default = no] + -v : toggle printing verbose information [default = no] + -w : toggle printing very verbose information [default = no] + -h : print the command usage + +usage: &isonpn [-vh] + removes POs with functionally isomorphic combinational COI + (currently ignores POs whose structural support is more than 16) + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &isost [-vh] + removes POs with functionally isomorphic combinational COI + (this command relies exclusively on structural hashing) + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &iwls21test [-vh] [-D file] + this command evaluates AIG for 2021 IWLS ML+LS Contest + -v : toggle printing verbose information [default = no] + -h : print the command usage + -D file : file name to dump statistics [default = none] + file1 : file with input AIG (or "&read ; &iwls21test " can be used) + file2 : file with CIFAR10 image data (https://www.cs.toronto.edu/~kriz/cifar.html) + +usage: &jf [-KCDW num] [-akmdcgvwh] + performs technology mapping of the network + -K num : LUT size for the mapping (2 <= K <= 8) [default = 6] + -C num : the max number of priority cuts (1 <= C <= 16) [default = 8] + -D num : sets the delay constraint for the mapping [default = best possible] + -W num : min frequency when printing functions with "-w" [default = 5] + -a : toggles area-oriented mapping [default = yes] + -e : toggles edge vs node minimization [default = yes] + -k : toggles coarsening the subject graph [default = no] + -m : toggles cut minimization [default = no] + -d : toggles using DSD to represent cut functions [default = no] + -c : toggles mapping for CNF generation [default = no] + -g : toggles generating AIG without mapping [default = no] + -v : toggles verbose output [default = no] + -w : toggles very verbose output [default = no] + -h : prints the command usage + +usage: &kf [-KCPDW num] [-akmdcgtsvwh] + performs technology mapping of the network + -K num : LUT size for the mapping (2 <= K <= 16) [default = 6] + -C num : the max number of priority cuts (1 <= C <= 32) [default = 8] + -P num : the number of cut computation processes (0 <= P <= 32) [default = 0] + -D num : sets the delay constraint for the mapping [default = best possible] + -W num : min frequency when printing functions with "-w" [default = 5] + -a : toggles area-oriented mapping [default = no] + -e : toggles edge vs node minimization [default = yes] + -k : toggles coarsening the subject graph [default = no] + -m : toggles cut minimization [default = no] + -d : toggles using DSD to represent cut functions [default = no] + -c : toggles mapping for CNF generation [default = no] + -g : toggles generating AIG without mapping [default = no] + -t : toggles cut computation using hash table [default = no] + -s : toggles cut computation using a simple method [default = no] + -v : toggles verbose output [default = no] + -w : toggles very verbose output [default = no] + -h : prints the command usage + +usage: &lcorr [-FCPX num] [-rcvwh] + performs latch correpondence computation + -C num : the max number of conflicts at a node [default = 100] + -F num : the number of timeframes in inductive case [default = 1] + -P num : the number of timeframes in the prefix [default = 0] + -X num : the number of iterations of little or no improvement [default = 0] + -r : toggle using implication rings during refinement [default = yes] + -c : toggle using circuit-based SAT solver [default = yes] + -v : toggle printing verbose information [default = no] + -w : toggle printing verbose info about equivalent flops [default = no] + -h : print the command usage + +usage: &lf [-KCFARLEDM num] [-kmupstgvwh] + performs technology mapping of the network + -K num : LUT size for the mapping (2 <= K <= 13) [default = 6] + -C num : the max number of priority cuts (1 <= C <= 32) [default = 8] + -F num : the number of area flow rounds [default = 4] + -A num : the number of exact area rounds [default = 1] + -R num : the delay relaxation ratio (num >= 0) [default = 0] + -L num : the fanout limit for coarsening XOR/MUX (num >= 2) [default = 3] + -E num : the area/edge tradeoff parameter (0 <= num <= 100) [default = 1] + -D num : sets the delay constraint for the mapping [default = best possible] + -M num : LUT size when cofactoring is performed (0 <= num <= 100) [default = 0] + -e : toggles edge vs node minimization [default = yes] + -k : toggles coarsening the subject graph [default = yes] + -m : toggles cut minimization [default = no] + -u : toggles using additional MUXes [default = no] + -p : toggles power-aware cut selection heuristics [default = no] + -s : toggles generating AIG without mapping [default = no] + -t : toggles optimizing average rather than maximum level [default = no] + -g : toggles using cut splitting [default = no] + -v : toggles verbose output [default = no] + -w : toggles very verbose output [default = no] + -h : prints the command usage + +usage: &lneteval [-O num] [-vh] + performs testing of the AIG on the simulation data + -O num : the output group size [default = -1] + -v : toggles verbose output [default = no] + -h : prints the command usage + : file name with simulation information + : file name with simulation information + +usage: &lnetmap [-IO num] [-fxvh] + performs specialized LUT mapping + -I num : the input support size [default = 6] + -O num : the output group size [default = 2] + -f : toggles using fixed primitives [default = no] + -x : toggles using another computation [default = yes] + -v : toggles verbose output [default = no] + -h : prints the command usage + : file name with simulation information + +usage: &lnetopt [-IORX num] [-vh] + performs specialized AIG optimization + -I num : the input support size [default = 6] + -O num : the output group size [default = 2] + -R num : patterns are cares starting this value [default = 0] + -X num : the number of optimization rounds [default = 20] + -v : toggles verbose output [default = no] + -h : prints the command usage + : file name with simulation information + +usage: &lnetread [-vh] + reads and converts the network or the simulation data + -v : toggles verbose output [default = no] + -h : prints the command usage + : input file name with simulation information + : output file name with simulation information + +usage: &lnetsim [-vh] + performs specialized AIG simulation + -v : toggles verbose output [default = no] + -h : prints the command usage + : input file name with simulation information + : output file name with simulation information + +usage: &load [-h] + loads AIG with mapping previously saved by &save + (after loading the previously saved AIG can be loaded again) + -h : print the command usage + +usage: &load2 [-h] + loads AIG with mapping previously saved by &save2 + (after loading the previously saved AIG cannot be loaded again) + -h : print the command usage + +usage: &loadaig [-h] + loads AIG previously saved by &saveaig + -h : print the command usage + +usage: &maxi [-FWT num] [-svh] + experimental procedure + -F num : the number of timeframes [default = 5] + -W num : the number of machine words [default = 1000] + -T num : approximate global runtime limit in seconds [default = 0] + -s : toggles using ternary simulation [default = no] + -v : toggles printing verbose information [default = no] + -h : print the command usage + +usage: &mesh [-XYT num] [-sh] + creates a mesh architecture for the given AIG + -X num : horizontal size of the mesh (X >= 3) [default = 4] + -Y num : vertical size of the mesh (Y >= 3) [default = 4] + -T num : the latency of the mesh (T >= 2) [default = 3] + -s : toggle using new SAT solver Satoko [default = yes] + -v : toggle printing verbose information [default = yes] + -h : print the command usage + +usage: &mf [-KCFARLED num] [-akmcgvwh] + performs technology mapping of the network + -K num : LUT size for the mapping (2 <= K <= 10) [default = 6] + -C num : the max number of priority cuts (1 <= C <= 16) [default = 8] + -F num : the number of area flow rounds [default = 2] + -A num : the number of exact area rounds [default = 1] + -R num : the delay relaxation ratio (num >= 0) [default = 0] + -L num : the fanout limit for coarsening XOR/MUX (num >= 2) [default = 3] + -E num : the area/edge tradeoff parameter (0 <= num <= 100) [default = 1] + -D num : sets the delay constraint for the mapping [default = best possible] + -a : toggles area-oriented mapping [default = no] + -e : toggles edge vs node minimization [default = yes] + -k : toggles coarsening the subject graph [default = yes] + -m : toggles cut minimization [default = no] + -c : toggles mapping for CNF generation [default = no] + -l : toggles mapping for literals [default = no] + -g : toggles generating AIG without mapping [default = no] + -v : toggles verbose output [default = no] + -w : toggles very verbose output [default = no] + -h : prints the command usage + +usage: &mfs [-WFDMLCN ] [-daeblvwh] + performs don't-care-based optimization of logic networks + -W : the number of levels in the TFO cone (0 <= num) [default = 5] + -F : the max number of fanouts to skip (1 <= num) [default = 30] + -D : the max depth nodes to try (0 = no limit) [default = 100] + -M : the max node count of windows to consider (0 = no limit) [default = 2000] + -L : the max increase in node level after resynthesis (0 <= num) [default = 0] + -C : the max number of conflicts in one SAT run (0 = no limit) [default = 5000] + -N : the max number of nodes to try (0 = all) [default = 0] + -d : toggle performing redundancy removal [default = no] + -a : toggle minimizing area or area+edges [default = area+edges] + -e : toggle high-effort resubstitution [default = no] + -b : toggle preserving all white boxes [default = no] + -l : toggle deriving don't-cares [default = no] + -v : toggle printing optimization summary [default = no] + -w : toggle printing detailed stats for each node [default = no] + -r : toggle testing re-importing the network unchanged [default = no] + -h : print the command usage + +usage: &mfsd [-KSNPWFMC ] [-mcdpvwh] + performs SAT-based delay-oriented AIG optimization + -K : the LUT size for delay minimization (2 <= num <= 6) [default = 4] + -S : the LUT structure size (1 <= num <= 2) [default = 3] + -N : the cut size considered for optimization (2 <= num <= 10) [default = 10] + -P : the number of cuts computed at a node (1 <= num <= 500) [default = 128] + -W : the number of levels in the TFO cone (0 <= num) [default = 5] + -F : the max number of fanouts to skip (1 <= num) [default = 4] + -M : the max node count of windows to consider (0 = no limit) [default = 2000] + -C : the max number of conflicts in one SAT run (0 = no limit) [default = 0] + -m : toggle generating delay-oriented mapping [default = yes] + -c : toggle using several cuts at each node [default = no] + -d : toggle additional search for good divisors [default = no] + -p : toggle optimizing critical path only [default = no] + -v : toggle printing optimization summary [default = no] + -w : toggle printing detailed stats for each node [default = no] + -h : print the command usage + +usage: &miter [-I num] [-dsptxyzcvh] + creates miter of two designs (current AIG vs. ) + -I num : the number of last PIs to replicate [default = 0] + -d : toggle creating dual-output miter [default = no] + -s : toggle creating sequential miter [default = no] + -p : toggle creating pair-wise miter [default = no] + -t : toggle XORing POs of dual-output miter [default = no] + -x : toggle XORing POs of two-word miter [default = no] + -y : toggle convering two-word miter into dual-output miter [default = no] + -z : toggle ordering sides of the dual-output miter [default = no] + -c : toggle duplicating AIG with the care set [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + : AIGER file with the design to miter + +usage: &miter2 [-vh] + creates miter of two copies of the design + -v : toggle printing verbose information [default = no] + -h : print the command usage + : file name with flop initial values (0/1/x/X) [default = required] + +usage: &mlgen [-WS num] [-bvh] + generates data files for machine learning + -W num : the number of words to simulate [default = 10] + -S num : the random seed for simulation data (num < 10000) [default = 0] + -b : toggle using binary data files [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + : file to store the simulation info + +usage: &mltest [-vh] [-D file] + testing command for machine learning data + -v : toggle printing verbose information [default = no] + -h : print the command usage + -D file : file name to dump statistics [default = none] + file : file with input simulation info + +usage: &move_names [-vh] + move CI/CO names + -v : toggles additional verbose output [default = no] + -h : print the command usage + : the file name + +usage: &mprove [-TLMGH num] [-sdvwh] + proves multi-output testcase by applying several engines + -T num : approximate global runtime limit in seconds [default = 30] + -L num : approximate local runtime limit in seconds [default = 2] + -M num : percentage of local runtime limit increase [default = 100] + -G num : approximate gap runtime limit in seconds [default = 0] + -H num : timeout per output in milliseconds [default = 0] + -s : toggle using combinational synthesis [default = no] + -d : toggle dumping invariant into a file [default = no] + -v : toggle printing verbose information [default = no] + -w : toggle printing additional verbose information [default = no] + -h : print the command usage + +usage: &mulfind [-C num] [-vh] + detects multipliers in the given AIG + -C num : the number of cuts to compute at each node [default = 8] + -v : toggles printing verbose information [default = no] + -h : print the command usage + +usage: &muxdec [-vh] + performs restructuring + -v : toggle verbose output [default = no] + -h : print the command usage + +usage: &muxpos [-vh] + create additional POs to preserve MUXes + -v : toggle verbose output [default = no] + -h : print the command usage + +usage: &muxstr [-vh] + performs restructuring + -v : toggle verbose output [default = no] + -h : print the command usage + +usage: &nf [-KCFARLEDQ num] [-akpqfvwh] + performs technology mapping of the network + -K num : LUT size for the mapping (2 <= K <= 6) [default = 6] + -C num : the max number of priority cuts (1 <= C <= 32) [default = 16] + -F num : the number of area flow rounds [default = 4] + -A num : the number of exact area rounds (when '-a' is used) [default = 2] + -R num : the delay relaxation ratio (num >= 0) [default = 0] + -L num : the fanout limit for coarsening XOR/MUX (num >= 2) [default = 3] + -E num : the area/edge tradeoff parameter (0 <= num <= 100) [default = 0] + -D num : sets the delay constraint for the mapping [default = best possible] + -Q num : internal parameter impacting area of the mapping [default = 0] + -a : toggles SAT-based area-oriented mapping (experimental) [default = no] + -k : toggles coarsening the subject graph [default = no] + -p : toggles pin permutation (more matches - better quality) [default = no] + -q : toggles quick mapping (fewer matches - worse quality) [default = no] + -f : toggles filtering matches (useful with unit delay model) [default = no] + -v : toggles verbose output [default = no] + -w : toggles very verbose output [default = no] + -h : prints the command usage + +usage: &odc [-N num] [-vh] + generates the complement of the ODC for the node + -N num : the node ID [default = undefined] + -v : toggles printing verbose information [default = 1640429008] + -h : print the command usage + +usage: &of [-KCFARLEDNMQ num] [-kmpgtvwh] + performs technology mapping of the network + -K num : LUT size for the mapping (2 <= K <= 6) [default = 4] + -C num : the max number of priority cuts (1 <= C <= 32) [default = 16] + -F num : the number of area flow rounds [default = 3] + -A num : the number of exact area rounds [default = 4] + -R num : the delay relaxation ratio (num >= 0) [default = 0] + -L num : the fanout limit for coarsening XOR/MUX (num >= 2) [default = 3] + -E num : the area/edge tradeoff parameter (0 <= num <= 100) [default = 10] + -D num : sets the delay constraint for the mapping [default = best possible] + -N num : delay of the first LUT [default = 10] + -M num : delay of the second LUT [default = 2] + -Q num : the number of fast non-routable edges [default = 0] + -e : toggles edge vs node minimization [default = yes] + -k : toggles coarsening the subject graph [default = no] + -m : toggles cut minimization [default = no] + -p : toggles power-aware cut selection heuristics [default = no] + -g : toggles generating AIG without mapping [default = no] + -t : toggles optimizing average rather than maximum level [default = no] + -v : toggles verbose output [default = no] + -w : toggles very verbose output [default = no] + -h : prints the command usage + +usage: &pack [-NRD num] [-vh] + performs packing for the LUT mapped network + -N num : the number of LUTs in the block [default = 2] + -R num : the routable delay of a LUT [default = 10] + -D num : the direct (non-routable) delay of a LUT [default = 2] + -v : toggles verbose output [default = no] + -h : prints the command usage + +usage: &permute [-S num] [-vh] + generates a random NPNP transformation of the combinational AIG + -S num : the seed used to randomize the process [default = 0] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &pfan [-N num] [-h] + prints fanin/fanout statistics + -N num : the number of high-fanout nodes to explore [default = 0] + -h : print the command usage + +usage: &pms [-h] + prints miter status after SAT sweeping + -h : print the command usage + +usage: &polyn [-N num] [-oasvwh] [-S str] + derives algebraic polynomial from AIG + -N num : the number of additional primary outputs (-1 = unused) [default = 0] + -o : toggles old computation [default = no] + -a : toggles simple computation [default = yes] + -s : toggles signed computation [default = no] + -v : toggles printing verbose information [default = no] + -w : toggles printing very verbose information [default = no] + -h : print the command usage + + -S str : (optional) the output signature as a character string + The format used to represent the output signature is very restrictive. + It should be a string without spaces containing monomials in terms of + inputs (i) and outputs (o) where is 0-based. Coefficients + are degrees of two, represented by log2 of their value: for example, + "2" is 2^2 = 4, "-4" is -2^4=-16, "-0" is -2^0=-1, etc + Two types of signature are accepted: + (1) a sequence of monomials without parentheses (for example, "-2*o0+1*o1+0*o2") + (2) a product of two sequences followed by a sum with a sequence + (for example, "(4*o0+2*o1+1*o2)*(4*i3+2*i4+1*i5)+(4*o3+2*o4+1*o5)") + Here is the signature of a signed 2-bit multiplier: "(0*o0+1*o1+2*o2-3*o3)" + +usage: &popart [-S num] [-imvh] + partitioning of POs into equivalence classes + -S num : random seed to select the set of pivot nodes [default = 0] + : (if the seed is 0, the nodes with max fanout counts are used) + -i : toggle allowing only CIs to be the pivots [default = no] + -m : toggle using the largest part as the current network [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &posplit [-N num] [-vh] + cofactors the property output w.r.t. a support subset + (the OR of new PO functions is equal to the original property) + -N num : the number of random cofactoring variables [default = 5] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &poxsim [-F num] [-vh] + X-valued simulation of the multi-output sequential miter + -F num : the number of timeframes [default = 1000] + -v : toggles printing verbose information [default = no] + -h : print the command usage + +usage: &print_truth [-OR num] [-vh] + prints truth tables of outputs in hex notation + -O num : the index of first PO to print [default = 0] + -R num : (optional) the number of outputs to extract [default = all] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &prodadd [-ABSscvh] + generates partial products and adder trees + -A num : the bit-width of the first arg [default = 4] + -B num : the bit-width of the second arg [default = 4] + -S num : random seed used the node ordering [default = 0] + -s : toggle using signed operation [default = no] + -c : toggle using CLA in the adder tree [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &profile [-N num] [-nmavh] + profile gate structures appearing in the AIG + -N num : limit on class size to show [default = 0] + -n : toggle profiling NPN-classes (for 3-LUT mapped AIGs) [default = no] + -m : toggle profiling MUX structures [default = no] + -a : toggle profiling adder structures [default = no] + -v : toggle verbose output [default = no] + -h : print the command usage + +usage: &ps [-tpcnlmaszxbh] [-D file] + prints stats of the current AIG + -t : toggle printing BMC tents [default = no] + -p : toggle printing switching activity [default = no] + -c : toggle printing the size of frontier cut [default = no] + -n : toggle printing NPN classes of functions [default = no] + -l : toggle printing LUT size profile [default = no] + -m : toggle printing MUX/XOR statistics [default = no] + -a : toggle printing miter statistics [default = no] + -s : toggle printing slack distribution [default = no] + -z : skip mapping statistics even if mapped [default = no] + -x : toggle using no color in the printout [default = no] + -b : toggle printing saved AIG statistics [default = no] + -D file : file name to dump statistics [default = none] + -h : print the command usage + +usage: &psig [-rh] + prints enable/set/reset statistics + -r : toggle printing set/reset signals [default = yes] + -h : print the command usage + +usage: &put [-seovh] + transfer the current network into the old ABC + -s : toggle clearning verification status [default = yes] + -e : toggle extracting MUXes for flop enables [default = no] + -o : toggles using buffers to decouple combinational outputs [default = no] + -v : toggle verbose output [default = no] + -h : print the command usage + +usage: &putontop [-vh] ... + generates an AIG by stacking several AIGs on top of each other + -v : toggles printing verbose information [default = no] + -h : print the command usage + : the AIGER files containing the input AIGs + the outputs of each AIG are connected to the inputs of the one on top of it + if there are more outputs than inputs, new POs will be created + if there are more inputs than outputs, new PIs are created + +usage: &qbf [-PICTK num] [-degvh] + solves QBF problem EpVxM(p,x) + -P num : number of parameters p (should be the first PIs) [default = -1] + -I num : quit after the given iteration even if unsolved [default = 0] + -C num : conflict limit per problem [default = 0] + -T num : global timeout [default = 0] + -K num : the number of input bits (for encoding miters only) [default = 0] + -d : toggle dumping QDIMACS file instead of solving (complemented QBF) [default = no] + -e : toggle dumping QDIMACS file instead of solving (original QBF) [default = no] + -g : toggle using Glucose 3.0 by Gilles Audemard and Laurent Simon [default = no] + -v : toggle verbose output [default = no] + -h : print the command usage + + As an example of using this command, consider specification (the three-input AND-gate) and implementation + (the circuit with function AND(XOR(x0, x1), x2)). The problem is to check whether the output of the XOR (node n) + can be implemented differently, so that these two circuits are equivalent. Obviously this can be done! + Simply replace XOR gate by AND gate. + + > # file s2.blif + > .model and3 + > .inputs x0 x1 x2 n + > .outputs F + > .names m x2 F + > 11 1 + > .names x0 x1 m + > 11 1 + > .end + + > # file i2.blif + > .model impl + > .inputs x0 x1 x2 n + > .outputs F + > .names n x2 F + > 11 1 + > #.names x0 x1 n + > #01 1 + > #10 1 + > .end + + > abc 08> miter -n i2.blif s2.blif; ps + > impl_and3_miter : i/o = 4/ 1 lat = 0 and = 6 lev = 4 + > abc 09> &get; &qbf -P 3 + > The problem is UNSAT after 1 iterations. Time = 0.00 sec + + UNSAT here means that the ECO solution with the given rectification point *has* a solution. + + For more info, refer to Figure 1 in the following paper A. Q. Dao, N.-Z. Lee, L.-C. Chen, M. P.-H. Lin, + J.-H. R. Jiang, A. Mishchenko, and R. Brayton, "Efficient computation of ECO patch functions", Proc. DAC'18. + https://people.eecs.berkeley.edu/~alanmi/publications/2018/dac18_eco.pdf + +usage: &qvar [-P num] [-uevh] + derives cofactors w.r.t. the last NumPi- variables + -P num : number of parameters p (should be the first PIs) [default = -1] + -u : toggle ANDing cofactors (universal quantification) [default = no] + -e : toggle ORing cofactors (existential quantification) [default = no] + -v : toggle verbose output [default = no] + -h : print the command usage + +usage: &r [-csxmnlvh] + reads the current AIG from the AIGER file + -c : toggles reading simple AIG [default = no] + -s : toggles structural hashing while reading [default = yes] + -x : toggles detecting XORs while reading [default = no] + -m : toggles reading MiniAIG rather than AIGER file [default = no] + -n : toggles reading MiniAIG as a set of supergates [default = no] + -l : toggles reading MiniLUT rather than AIGER file [default = no] + -v : toggles additional verbose output [default = no] + -h : print the command usage + : the file name + +usage: &reachm [-TBFCHS num] [-L file] [-ripcsyzvwh] + model checking via BDD-based reachability (dependence-matrix-based) + -T num : approximate time limit in seconds (0=infinite) [default = 0] + -B num : max number of nodes in the intermediate BDDs [default = 10000000] + -F num : max number of reachability iterations [default = 10000000] + -C num : max number of variables in a cluster [default = 20] + -H num : max number of hints to use [default = 0] + -S num : the number of the starting hint [default = 0] + -L file: the log file name [default = no logging] + -r : enable dynamic BDD variable reordering [default = yes] + -i : enable extraction of inductive constraints [default = no] + -p : enable partitions for internal cut-points [default = no] + -c : enable clustering of partitions [default = no] + -s : enable scheduling of clusters [default = no] + -y : skip checking property outputs [default = no] + -z : skip reachability (run preparation phase only) [default = no] + -v : prints verbose information [default = no] + -w : prints dependency matrix [default = no] + -h : print the command usage + +usage: &reachn [-BFT num] [-L file] [-ryzvh] + model checking via BDD-based reachability (non-linear-QS-based) + -B num : the BDD node increase when hints kick in [default = 10000000] + -F num : max number of reachability iterations [default = 10000000] + -T num : approximate time limit in seconds (0=infinite) [default = 0] + -L file: the log file name [default = no logging] + -r : enable additional BDD var reordering before image [default = yes] + -y : skip checking property outputs [default = no] + -z : skip reachability (run preparation phase only) [default = no] + -v : prints verbose information [default = no] + -h : print the command usage + +usage: &reachp [-NFT num] [-L file] [-rbyzdvwh] + model checking via BDD-based reachability (partitioning-based) + -N num : partitioning value (MinVol=nANDs/N/2; MaxVol=nANDs/N) [default = 5] + -F num : max number of reachability iterations [default = 10000000] + -T num : approximate time limit in seconds (0=infinite) [default = 0] + -L file: the log file name [default = no logging] + -r : enable additional BDD var reordering before image [default = yes] + -b : perform backward reachability analysis [default = no] + -y : skip checking property outputs [default = no] + -z : skip reachability (run preparation phase only) [default = no] + -d : dump BDD of reached states into file "reached.blif" [default = no] + -v : prints verbose information [default = no] + -w : prints additional information [default = no] + -h : print the command usage + +usage: &reachy [-BCFT num] [-L file] [-bcryzvh] + model checking via BDD-based reachability (non-linear-QS-based) + -B num : the max BDD size to introduce cut points [default = 100] + -C num : the max BDD size to reparameterize/cluster [default = 500] + -F num : max number of reachability iterations [default = 10000000] + -T num : approximate time limit in seconds (0=infinite) [default = 0] + -L file: the log file name [default = no logging] + -b : enable using backward enumeration [default = no] + -c : enable reparametrization clustering [default = no] + -r : enable additional BDD var reordering before image [default = no] + -y : skip checking property outputs [default = no] + -z : skip reachability (run preparation phase only) [default = no] + -v : prints verbose information [default = no] + -h : print the command usage + +usage: &r [-csxmnlvh] + reads the current AIG from the AIGER file + -c : toggles reading simple AIG [default = no] + -s : toggles structural hashing while reading [default = yes] + -x : toggles detecting XORs while reading [default = no] + -m : toggles reading MiniAIG rather than AIGER file [default = no] + -n : toggles reading MiniAIG as a set of supergates [default = no] + -l : toggles reading MiniLUT rather than AIGER file [default = no] + -v : toggles additional verbose output [default = no] + -h : print the command usage + : the file name + +usage: &read_blif [-vh] + a specialized reader for hierarchical BLIF files + (for general-purpose BLIFs, please use "read_blif") + -v : toggles additional verbose output [default = no] + -h : print the command usage + : the file name + +usage: &read_cblif [-M name] [-vh] + reads CBLIF file and collapse it into an AIG + -M name: module name to collapse [default = ] + -v : toggles additional verbose output [default = no] + -h : print the command usage + : the file name + +usage: &read_stg [-K ] [-vh] + reads STG file and generates K-hot-encoded AIG + -K num : the K parameter for hotness of the encoding (1 <= K <= 5) [default = 1] + -v : toggles printing state codes [default = no] + -h : print the command usage + : the file name + +usage: &read_ver [-vh] + a specialized reader for hierarchical Verilog files + -v : toggles additional verbose output [default = no] + -h : print the command usage + : the file name + +usage: &reduce [-advh] + reduces the circuit using equivalence classes + -a : toggle merging all equivalences [default = no] + -d : toggle using dual-output merging [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &reshape [-asvwh] + performs AIG resubstitution + -a : toggles selecting the algorithm [default = no] + -s : toggles using simple method [default = no] + -v : toggles printing verbose information [default = no] + -w : toggles printing additional information [default = no] + -h : print the command usage + +usage: &resim [-F num] [-mvh] + resimulates equivalence classes using counter-example + -F num : the number of additinal frames to simulate [default = 100] + -m : toggle miter vs. any circuit [default = circuit] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &resub [-NSD num] [-vwh] + performs AIG resubstitution + -N num : the limit on added nodes (num >= 0) [default = 0] + -S num : the limit on support size (num > 0) [default = 0] + -D num : the limit on divisor count (num > 0) [default = 0] + -v : toggles printing verbose information [default = no] + -w : toggles printing additional information [default = no] + -h : print the command usage + +usage: &retime [-N ] [-vh] + performs most-forward retiming + -N num : the number of incremental iterations [default = 100] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &reveng [-W num] [-vh] + compares two AIGs for structural similarity + the current AIG is expected to contain some hierarchy + the given AIG from is expected to be flat + -W num : the number of 64-bit words of simulation info [default = 4] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &rex2gia [-avh] [string] + converts a regular expression into a sequential AIG + -a : toggle ordering input symbols alphabetically [default = yes] + -v : toggle verbose output [default = no] + -h : print the command usage + string : representation of a regular expression + Special symbols: parentheses '(' and ')', Kleene closure '*', union '|' + All other characters are treated as symbols of the input alphabet. + For example, ((A*B|AC)D) is defined over the alphabet {A, B, C, D} + and generates the following language: {BD, ABD, AABD, AAABD, ..., ACD} + A known limitation: For the command to work correctly, each two-input union + should have a dedicated pair of parentheses: ((A|B)|C) rather than (A|B|C) + +usage: &rexwalk [-SR] [-vh] + performs simulation of an AIG representing a regular expression + -S num : the number of steps to take [default = 50] + -R num : the number of walks to make [default = 5] + -v : toggle verbose output [default = no] + -h : print the command usage + +usage: &rpm [-C num] [-navwh] + performs structural reparametrization + -C num : max cut size for testing range equivalence [default = 16] + -n : toggle using naive reparametrization [default = no] + -a : toggle using old algorithm [default = no] + -v : toggle printing verbose information [default = no] + -w : toggle printing more verbose information [default = no] + -h : print the command usage + +usage: &sat [-JCRSN ] [-anmctxzvh] + performs SAT solving for the combinational outputs + -J num : the SAT solver type [default = -1] + -C num : the max number of conflicts at a node [default = 100] + -R num : the max number of restarts at a node [default = 1] + -S num : the min number of variables to recycle the solver [default = 2000] + -N num : the min number of calls to recycle the solver [default = 200] + -a : toggle solving all outputs and saving counter-examples [default = no] + -n : toggle using non-chronological backtracking [default = yes] + -m : toggle miter vs. any circuit [default = circuit] + -c : toggle using circuit-based SAT solver [default = no] + -t : toggle using learning in curcuit-based solver [default = no] + -x : toggle using new solver [default = no] + -y : toggle using new solver [default = no] + -z : toggle replacing proved cones by const0 [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &satclp [-CL num] [-cvh] + performs SAT based collapsing + -C num : the limit on the SOP size of one output [default = 1000] + -L num : the limit on the number of conflicts in one SAT call [default = 1000000] + -c : toggles using canonical ISOP computation [default = no] + -v : toggles printing verbose information [default = no] + -h : print the command usage + +usage: &satenum [-CT ] [-vh] + enumerates solutions of the combinational miter + -C num : the max number of conflicts at a node [default = 0] + -T num : global timeout [default = 0] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &satfx [-ID num] [-dvh] + performs SAT based shared logic extraction + -I num : the number of iterations of divisor extraction [default = 5] + -D num : the number of divisors to extract in each iteration [default = 10] + -d : toggles decomposing the first output [default = yes] + -v : toggles printing verbose information [default = no] + -h : print the command usage + +usage: &satlut [-NICDQ num] [-drwvh] + performs SAT-based remapping of the LUT-mapped network + -N num : the limit on AIG nodes in the window (num <= 128) [default = 32] + -I num : the limit on the number of improved windows [default = 0] + -C num : the limit on the number of conflicts [default = 100] + -D num : the user-specified required times at the outputs [default = 0] + -Q num : the maximum number of edges [default = 0] + -d : toggles delay optimization [default = no] + -r : toggles using reverse search [default = no] + -v : toggles verbose output [default = no] + -h : prints the command usage + +usage: &satsyn [-NOT ] [-afvh] + performs synthesis + -N : the number of window nodes [default = 0] + -O : the number of window outputs [default = 0] + -T : the timeout in seconds (0 = no timeout) [default = 0] + -a : toggle using xor-nodes [default = no] + -f : toggle using additional feature [default = no] + -v : toggle printing optimization summary [default = no] + -h : print the command usage + +usage: &sattest [-cvh] + performs testing of dynamic CNF loading + -c : toggle dynamic CNF loading [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &save [-ah] + compares and possibly saves AIG with mapping + -a : toggle using area as the primary metric [default = no] + -h : print the command usage + +usage: &save2 [-ah] + compares and possibly saves AIG with mapping + -a : toggle using area as the primary metric [default = no] + -h : print the command usage + +usage: &saveaig [-cah] + saves the current AIG into the internal storage + -c : toggle clearing the saved AIG [default = no] + -a : toggle saving AIG with the smaller area [default = no] + -h : print the command usage + +usage: &scl [-cevwh] + performs structural sequential cleanup + -c : toggle removing stuck-at constant registers [default = yes] + -e : toggle removing equivalent-driver registers [default = yes] + -v : toggle printing verbose information [default = no] + -w : toggle printing verbose info about equivalent flops [default = no] + -h : print the command usage + +usage: &scorr [-FCGXPSZ num] [-pkrecqowvh] + performs signal correpondence computation + -C num : the max number of conflicts at a node [default = 100] + -F num : the number of timeframes in inductive case [default = 1] + -G num : the number of timeframes in the prefix [default = 0] + -X num : the number of iterations of little or no improvement [default = 0] + -P num : the number of concurrent processes [default = 1] + -S num : the number of flops in one partition [default = 0] + -Z num : the average flop include frequency [default = 0] + -p : toggle using partitioning for the input AIG [default = no] + -k : toggle using constant correspondence [default = no] + -r : toggle using implication rings during refinement [default = yes] + -e : toggle using equivalences as choices [default = no] + -c : toggle using circuit-based SAT solver [default = yes] + -q : toggle quitting when PO is not a constant candidate [default = no] + -o : toggle calling old engine [default = no] + -w : toggle printing verbose info about equivalent flops [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &semi [-WRFSMCT num] [-mdvh] + performs semiformal refinement of equivalence classes + -W num : the number of words to simulate [default = 31] + -R num : the max number of rounds to simulate [default = 200] + -F num : the max number of frames to unroll [default = 200] + -S num : the max number of rounds w/o refinement to stop [default = 3] + -M num : the min number of outputs of bounded SRM [default = 0] + -C num : the max number of conflicts at a node [default = 100] + -T num : approximate runtime limit in seconds [default = 0] + -m : toggle miter vs. any circuit [default = circuit] + -d : toggle using two POs instead of XOR [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &setregnum [-N num] [-h] + manually sets the number of registers to combine the last PI/PO pairs + -N num : set the number of registers to be the given number [default = 0] + -h : print the command usage + +usage: &show [-afph] + shows the current GIA using GSView + -a : toggle visualazing adders [default = no] + -f : toggle showing only full-adders with "-a" [default = no] + -p : toggle showing the critical path of a LUT mapping [default = no] + -h : print the command usage + +usage: &shrink [-N num] [-lvh] + performs fast shrinking using current mapping + -N num : the max fanout count to skip a divisor [default = 50] + -l : toggle level update during shrinking [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &sif [-K num] [-evh] + performs technology mapping + -K num : sets the LUT size for the mapping [default = 6] + -e : toggles the evaluation mode [default = no] + -v : toggles verbose output [default = no] + -h : prints the command usage + +usage: &sim [-FWNT num] [-mvh] -I + performs random simulation of the sequential miter + (if candidate equivalences are defined, performs refinement) + -F num : the number of frames to simulate [default = 32] + -W num : the number of words to simulate [default = 8] + -N num : random number seed (1 <= num <= 1000) [default = 0] + -T num : approximate runtime limit in seconds [default = 60] + -m : toggle miter vs. any circuit [default = circuit] + -v : toggle printing verbose information [default = no] + -h : print the command usage + -I file: (optional) file with input patterns (one line per frame, as many as PIs) + +usage: &sim2 [-WRNT num] [-vh] + performs random of two circuits + -W num : the number of words to simulate [default = 16] + -R num : the number of simulation rounds [default = 10] + -N num : random number seed (1 <= num <= 1000) [default = 1] + -T num : approximate runtime limit in seconds [default = 0] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &sim3 [-FWBRNT num] [-gvh] + performs random simulation of the sequential miter + -F num : the number of frames to simulate [default = 20] + -W num : the number of words to simulate [default = 50] + -B num : the number of flops in one bin [default = 8] + -R num : the number of simulation rounds [default = 0] + -S num : the number of rounds before a restart [default = 0] + -N num : random number seed (1 <= num <= 1000) [default = 0] + -T num : approximate runtime limit in seconds [default = 0] + -g : toggle heuristic flop grouping [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &sim_gen [-WR num] [-sdvh] + generates random simulation patterns + -W num : the number of 64-bit words of simulation info [default = 4] + -R num : the rarity parameter used to define scope [default = -1] + -s : toggle using SAT-based improvement of available patterns [default = no] + -d : toggle using one improvement of available patterns [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &sim_print [-vh] + writes simulation patterns into a file + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &sim_read [-W num] [-trovh] + reads simulation patterns from file + -W num : the number of words to simulate [default = 4] + -t : toggle creating exhaustive simulation info [default = no] + -r : toggle reversing MSB and LSB input variables [default = no] + -o : toggle reading output information [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + : file to store the simulation info + +usage: &sim_write [-otbvh] + writes simulation patterns into a file + -o : toggle writing output information [default = no] + -t : toggle transposing the simulation information [default = no] + -b : toggle dumping in boolean vs hexadecimal notation [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + : file to store the simulation info + +usage: &simrsb [-N num] [-vh] + performs resubstitution + -C num : the number of candidates to try [default = 32] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &slice [-S num] [-vh] + cuts the lower part of the AIG with nodes using their support + -S num : the largest support size to keep in the slide [default = 6] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &sopb [-LWCR num] [-vh] + performs SOP balancing + -L num : optimize paths above this level [default = 0] + -W num : optimize paths falling into this window [default = 0] + -C num : the number of cuts at a node [default = 8] + -R num : the delay relaxation ratio (num >= 0) [default = 0] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &speci [-FC num] [-fmvh] + refines equivalence classes using speculative reduction + -F num : the max number of time frames [default = 100] + -C num : the max number of conflicts at a node [default = 25000] + -f : toggle starting BMC from a later frame [default = yes] + -m : toggle miter vs. any circuit [default = miter] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &speedup [-P num] [-N num] [-lvwh] + transforms LUT-mapped network into an AIG with choices; + the choices are added to speedup the next round of mapping + -P : delay delta defining critical path for library model [default = 5%] + -N : the max critical path degree for resynthesis (0 < num < 6) [default = 2] + -l : toggle using unit- or LUT-library-delay model [default = unit] + -v : toggle printing optimization summary [default = no] + -w : toggle printing detailed stats for each node [default = no] + -h : print the command usage + +usage: &splitprove [-PTIL num] [-svwh] + proves CEC problem by case-splitting + -P num : the number of concurrent processes [default = 1] + -T num : runtime limit in seconds per subproblem [default = 10] + -I num : the max number of iterations (0 = infinity) [default = 0] + -L num : maximum look-ahead during cofactoring [default = 1] + -s : enable silent computation (no reporting) [default = no] + -v : toggle printing verbose information [default = no] + -w : toggle printing more verbose information [default = no] + -h : print the command usage + +usage: &splitsat [-BENVTPIS num] [-pvh] + solves CNF-based SAT problem by randomized case-splitting + -B num : the first CNF variable to use for splitting [default = 0] + -E num : the last CNF variable to use for splitting [default = 1000000000] + -N num : the number of CNF variables to use for splitting [default = 10] + -V num : the variable values to use (0, 1, or 2 for "any") [default = 2] + -T num : the runtime limit in seconds per subproblem [default = 5] + -P num : the number of concurrent processes [default = 1] + -I num : the max number of iterations (0 = infinity) [default = 1] + -S num : the random seed used to generate cofactors [default = 0] + -p : toggle using SatELIte (http://minisat.se/SatELite.html) [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &sprove [-PTUW num] [-svwh] + proves CEC problem by case-splitting + -P num : the number of concurrent processes [default = 5] + -T num : runtime limit in seconds per subproblem [default = 3] + -U num : runtime limit in seconds per subproblem [default = 10] + -W num : runtime limit in seconds per subproblem [default = 100] + -s : enable silent computation (no reporting) [default = no] + -v : toggle printing verbose information [default = no] + -w : toggle printing more verbose information [default = no] + -h : print the command usage + +usage: &srm [-A file] [-drsfcvh] + derives or writes speculatively reduced model into file "gsrm.aig" + -A file : file name for dumping speculative-reduced model [default = "gsrm.aig"] + -d : toggle creating dual-output miter [default = no] + -r : toggle writing reduced network for synthesis [default = no] + -s : toggle using speculation at the internal nodes [default = yes] + -f : toggle filtering to remove redundant equivalences [default = no] + -c : toggle using combinational speculation [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &srm2 [-abvh] + writes speculatively reduced model into file "l,ˆÿ" + only preserves equivalences across PartA and PartB + -a : toggle using latches only in PartA [default = no] + -b : toggle using latches only in PartB [default = no] + -v : toggle printing verbose information [default = no] + -h : print the command usage + +usage: &st [-LM num] [-bacmrsh] + performs structural hashing + -b : toggle adding buffers at the inputs and outputs [default = no] + -a : toggle additional hashing [default = no] + -c : toggle collapsing hierarchical AIG [default = no] + -m : toggle converting to larger gates [default = no] + -L num : create MUX when sum of refs does not exceed this limit [default = 2] + (use L = 1 to create AIG with XORs but without MUXes) + -M num : create an AIG with additional primary inputs [default = 0] + -r : toggle rehashing AIG while preserving mapping [default = no] + -s : toggle using MUX restructuring [default = no] + -h : print the command usage + +usage: &status [-h] + prints status of the miter + -h : print the command usage + +usage: &stochsyn [-NITSP ] [-tvh]