diff --git a/README.md b/README.md
index 8e6053d..dc7b17f 100644
--- a/README.md
+++ b/README.md
@@ -1,95 +1,103 @@
 # 1. NEM synthesis
 
 This utility was written to use yosys to synthesize from verilog to a netlist existing out of all standard cells available in the current library of NEM cells. It only uses the freely available yosys oss suite. No license required
 
 # 2. data structure
 
 The application is ordered as follows:
 
 ```
+\bruteforce_approach\: contains all the c script's and a python script to run bruteforce approach on very small functions
 \sources\ : All the verilog files for synthesis have to be stored here
 \temp\ : Contains all the output files after synthesis or intermediate yosys / graphviz dots files.
 \yosys\ : Script that are executed for synthesis, visual, and sat testing.
 \nem_basic_yosys.lib : This is the file of all the standard cells used in nem
 \nem_basic_yosys_extended.lib : this is the additional cells added based on some new concepts
  ```
 
 As a user put the desired source files in .\sources\ and had to the next sessions
 # 3. How to run
 
 Pull the repository to your local working directory.
 
 run:
 
 ```bash
 source <oss-suite-location>/enviroment
 ./run.sh
 ```
 
 and enter the file you want to use. Auto-complete is aviable, an example would be `sources/test_set/adder2.v`. Then enter the main module name. Just press enter if it is the same as the file name, (in the example `adder2`).
 
 You will be presented with the following options:
 
 ```bash
 --------------------------------------------------------------
 Current file: sources/test_set/adder2.v with module: adder2
 Please select your options (you can choose multiple options):
 
-1) Synthesize NEM mapped replicate of Verilog implementation
+1) Synthesize to NEM technology
 2) Print initial design
 3) Print out NEM optimized design
 4) Perform SAT comparison
 5) Export FSM as KISS2 format
 6) Start shell with modules
 7) Switch from normal 3T gate library to new 4T
 8) Run test
-9) Select a new Verilog file
+9) export truth table and MUXIG run
+10) export truth table and MIG run
+11) Select a new Verilog file
 0) Exit the program
 --------------------------------------------------------------
 Enter your choices (e.g., 1 2 3, or 0 to finish):
 ```
 
 1: As the text explains option 1 will run the synthesis script under `\yosys\` and will output the file as `_nem.v` extension in the `\temp\` folder. Next to that it will output statistics in the `.stat` file under `\temp\`.
 2: Shows the abstract design before any syntehsis is done
 3: Shows the final synthesized solution
 4: Checks if the original verilog file matches the output of the final synthesised solution.
 5: search for fsm model and view it
 6: Compile plugins and start a shell to run them
 7: Switch to extended liberty file with pass through muxiplexers
 8: run synthesis and visual for both liberty files
-9: switch to different verilog file
+9: pass the circuit to mockturtle to process it into MuxIG graph 
+10: pass the circuit to mockturtle to process it into MIG graph
+11: switch to different verilog file
 
 # 4. CLI
 
 You can also call the `./run.sh` with some arguments to work as a in-line tool if you want to automate stuff. The options are:
 
 -d [DIRECTORY]      synthesise all the files in the directory
 -f [FILE_PATH]      syntehsise specific path
 -m [MODULE_NAME]    When -f argument used
 -v                  when present will also visuale the file.
 -x                  Switch liberty file to extended version
 
 # 5. Optimisation adjusments
 
 the new extended libary makes use of trivial boolean equivalent muxiplexers and operators for AND and OR operations. More info will be added later.
 
+# Bruteforce approach
+In \bruteforce_approach\ are a couple c files to help with small bruteforce approaches to check a minimal circuit. 
+
 # 6. Troubleshooting
 
 ## 6.1. SAT comparison
 If the SAT comparison gives a comment that it is not aware of a certain `_DFF_` cell such as `_DFF_PP0` then this specific memeory cell does not exist in the standard cell library therefore it does not have the function to simulate it. These register often have asynchronous reset therefore make sure that your design does not use 
 
 ```
 always@(posedge clk or posedge rst)
     if (rst) begin
         result <= 0;
 ......
 ```
 but instead
 ```
 always@(posedge clk)
     if (rst) begin
         result <= 0;
 ......
 ```
 
 So that reset happens on the same clk as a normal `_DFF_` register.
\ No newline at end of file
diff --git a/bruteforce_approach/bruteforce_mux-xor.c b/bruteforce_approach/bruteforce_mux-xor.c
index ebb3f36..7c37bd6 100644
--- a/bruteforce_approach/bruteforce_mux-xor.c
+++ b/bruteforce_approach/bruteforce_mux-xor.c
@@ -1,483 +1,486 @@
 #include <stdarg.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <pthread.h>
 #include <stdint.h>
 #include <string.h>
 #include <unistd.h>
 
 // -------------- config
 
 #define MAX_AREA 10000 //Determine the initial max_area
-#define NUM_INPUTS 3 //speaks for itself
-#define MAX_GATES 6 // determine the max_amount of gates
-#define NUM_THREADS 3 //Needs to be <= 9 or 18 or 27 for efficient splitting the work load
+#define NUM_INPUTS 4 //speaks for itself
+#define MAX_GATES 3 // determine the max_amount of gates
+#define NUM_THREADS 4 //Needs to be <= 9 or 18 or 27 for efficient splitting the work load
 
 #define use_truth_table 1 //If 1 use the truth table below. If multiple outputs then paste the truth table after another from the [file].truth
+#define target_truth_table "00000000"
 //#define target_truth_table "11101000" //exampe here [Target A][Target B] pasted after another. 
 //MAJ testing
 
-#define target_truth_table "1110100010010110"
+
+
+//#define target_truth_table "1110100010010110"
 //half adder
 /*
 The truth table matching this is that of a increase in value of the input variables
 Let's say 3 input variables
 
 I3 I2 I1   | O2 O1
 A, B, Cin, | S Cout 
 0, 0,   0, | 0 0
 0, 0,   1, | 1 0
 0, 1,   0, | 1 0
 0, 1,   1, | 0 1
 1, 0,   0, | 1 0
 1, 0,   1, | 0 1
 1, 1,   0, | 0 1
 1, 1,   1, | 1 1
 
 S =     10010110
 Cout =  11101000
 MUX =   11001010
 target_truth_table = "S Cin" = "1110100010010110"
 also means that output B
 */
 //AND = &&, OR = ||, XOR = ^, NOT = !
 int target_function(int inputs[]) {
     return inputs[0] ^ inputs[1];
 }
 
 // -------------- Auto-define
 
 #define NUM_COMBINATION (1 << NUM_INPUTS)
 #define NUM_OUTPUTS (sizeof(target_truth_table)-1)/NUM_COMBINATION
 
 // -------------- structs
 
 typedef struct {
     char* type;
     int area;
 } GateType;
 
 typedef struct {
     GateType* gate;
     int8_t in1;
     int8_t in2;
     int8_t in3;
     int8_t in4;
 } Gate;
 
 typedef struct {
     Gate gates[MAX_GATES];
     int8_t gate_count;
     int area;
 } Circuit;
 
 typedef struct {
     Circuit volatile best_circuit;
     GateType *gate_types;
     int num_inputs;
     int num_gates;
     int volatile best_area;
     int8_t  *truth_table;
     int8_t  *target_outputs;
     int worker_id;
     int num_circuit[2]; //first is the amount in million  and the second is the increment counter.
     pthread_mutex_t mutex;
 } ThreadArgs;
 
 
 // -------------- define used gates
 GateType gate_types[] = {
     {"INV", 1160},
     {"MUX-XOR", 1288}
 };
 
 // -------------- start functions
 void tee(FILE *f, char const *fmt, ...) { 
     va_list ap;
     va_start(ap, fmt);
     vprintf(fmt, ap);
     va_end(ap);
     va_start(ap, fmt);
     vfprintf(f, fmt, ap);
     va_end(ap);
 }
 
 void print_circuit(Circuit * circuit){
     FILE *fptr;
 
-    fptr = fopen("../output/output_bruteforce.txt", "a");
+    fptr = fopen("./output/output_bruteforce.txt", "a");
 
     //for(int y=0; y<circuit->gate_count; y++){
     //    printf("%d: %s, in1: %d, in2: %d, in3: %d\n",y,circuit->gates[y].gate->type,circuit->gates[y].in1,circuit->gates[y].in2,circuit->gates[y].in3);
     //}
 
     tee(fptr,"---------- Circuit area: %d ----------\n",circuit->area);
     tee(fptr,"Input ");
     for(int i='a';(i-'a')<NUM_INPUTS;i++){tee(fptr,"%c, ",i);}
     tee(fptr,"\n");
 
     for(int y=0; y<circuit->gate_count; y++){
         int print_in1 = circuit->gates[y].in1 + '0';
         int print_in2 = circuit->gates[y].in2 + '0';
         int print_in3 = circuit->gates[y].in3 + '0';
         int print_in4 = circuit->gates[y].in4 + '0';
         if((print_in1-2-'0')<NUM_INPUTS && (print_in1-2-'0')>=0){
          print_in1 = circuit->gates[y].in1-2 + 'a';
         }
         if((print_in2-2-'0')<NUM_INPUTS && (print_in2-2-'0')>=0){
          print_in2 = circuit->gates[y].in2-2 + 'a';
         }
         if((print_in3-2-'0')<NUM_INPUTS && (print_in3-2-'0')>=0){
          print_in3 = circuit->gates[y].in3-2 + 'a';
         }
         if((print_in4-2-'0')<NUM_INPUTS && (print_in4-2-'0')>=0){
          print_in4 = circuit->gates[y].in4-2 + 'a';
         }
         
         tee(fptr,"%d: %s, in1: %c, in2: %c, in3: %c, in4: %c\n",y+NUM_INPUTS+2,circuit->gates[y].gate->type,print_in1,print_in2,print_in3,print_in4);
     }
     
     tee(fptr,"Output ");
     for(int i='x';(i-'x')<NUM_OUTPUTS;i++){tee(fptr,"%c:%lu, ",i,NUM_INPUTS+circuit->gate_count-NUM_OUTPUTS+(i-'x')+2);}
     tee(fptr,"\n");
     tee(fptr,"----------------------------------------\n");
     fclose(fptr);
 }
 
 void write_circuit_to_file(Circuit * circuit, int area, int worker_number, int file_number){
     FILE *fptr;
 
     char file_name[100];
-    sprintf(file_name, "../output/output_%d_%d_%d_bruteforce.dot", area, worker_number, file_number);
+    sprintf(file_name, "./output/output_%d_%d_%d_bruteforce.dot", area, worker_number, file_number);
 
     fptr = fopen(file_name, "w");
 
     //for(int y=0; y<circuit->gate_count; y++){
     //    printf("%d: %s, in1: %d, in2: %d, in3: %d\n",y,circuit->gates[y].gate->type,circuit->gates[y].in1,circuit->gates[y].in2,circuit->gates[y].in3);
     //}
     fprintf(fptr, "digraph Circuit {\n  rankdir=LR; // Makes the graph left-to-right\n  node [shape=ellipse]; // Default shape for nodes\n ranksep=2; // Increases vertical separation\n");
 
 
     for(int i='a';(i-'a')<NUM_INPUTS;i++){fprintf(fptr,"  %c [ shape=octagon, label=\"%c\", color=\"black\", fontcolor=\"black\"]; \n",i,i);}
 
 
     for(int y=0; y<circuit->gate_count; y++){
         int print_in1 = circuit->gates[y].in1 + '0';
         int print_in2 = circuit->gates[y].in2 + '0';
         int print_in3 = circuit->gates[y].in3 + '0';
         int print_in4 = circuit->gates[y].in4 + '0';
         if((print_in1-2-'0')<NUM_INPUTS && (print_in1-2-'0')>=0){
          print_in1 = circuit->gates[y].in1-2 + 'a';
         }
         if((print_in2-2-'0')<NUM_INPUTS && (print_in2-2-'0')>=0){
          print_in2 = circuit->gates[y].in2-2 + 'a';
         }
         if((print_in3-2-'0')<NUM_INPUTS && (print_in3-2-'0')>=0){
          print_in3 = circuit->gates[y].in3-2 + 'a';
         }
         if((print_in4-2-'0')<NUM_INPUTS && (print_in4-2-'0')>=0){
          print_in4 = circuit->gates[y].in4-2 + 'a';
         }
 
         int unit_number = y+NUM_INPUTS+2;
         fprintf(fptr,"  %d [ shape=record, label=\"{{<p1> ==|<p3> XOR 0|<p4> XOR 1|<p2> !=}| MUX-XOR %d |{<p4> Y}}\", color=\"darkred\", fontcolor=\"darkred\" ];\n",unit_number,unit_number);
         fprintf(fptr,"  %c:e -> %d:p1;\n  %c:e -> %d:p2;\n  %c:e -> %d:p3;\n %c:e -> %d:p4;\n",print_in1,unit_number,print_in2,unit_number,print_in3,unit_number,print_in4,unit_number);
     }
     
     for(int i='x';(i-'x')<NUM_OUTPUTS;i++){fprintf(fptr,"  %lu:e -> %c;\n",NUM_INPUTS+circuit->gate_count-NUM_OUTPUTS+(i-'x')+2,i);}
     
 
     fprintf(fptr,"}\n");
     fclose(fptr);
 }
 
 void evaluate_circuit(GateType* all_gates, Circuit* circuit, int8_t* inputs, int8_t* outputs) {
     int8_t intermediate_outputs[NUM_INPUTS + MAX_GATES+2];
     intermediate_outputs[0] = 0; //Make sure that intermediate_outputs[0] = 0 and [1] = 1 for constant signal attachments
     intermediate_outputs[1] = 1;
     memcpy(&intermediate_outputs[2], inputs, NUM_INPUTS * sizeof(int8_t)); //copy boolean value over this
 
     for (int i = 0; i < circuit->gate_count; i++) {
         int out1 = intermediate_outputs[circuit->gates[i].in1];
         int out2 = intermediate_outputs[circuit->gates[i].in2];
         int out3 = intermediate_outputs[circuit->gates[i].in3];
         int out4 = intermediate_outputs[circuit->gates[i].in4];
         int output = 0;
 
         if (circuit->gates[i].gate ==  &all_gates[0]) //INV
             output =  ~out1 & 1;
         else if (circuit->gates[i].gate ==  &all_gates[1]) //MUX-XOR
             output = (out4^out3) ? out2 : out1;
 
         intermediate_outputs[NUM_INPUTS + i + 2] = output;
     }
 
     for(int z=0; z<NUM_OUTPUTS;z++){
         outputs[z] = intermediate_outputs[NUM_INPUTS + 2 + circuit->gate_count-NUM_OUTPUTS+z];
     }
 }
 
 int detect_tautology(Circuit *current_circuit, int in1, int in2, int in3, int in4, int gate_selected, ThreadArgs *data){
     if ((in1 == in2 && gate_selected != 0) ||
         //(in1 == in3 || in2 == in3) ||
         (in3 == in4)){ 
         //(in1 == 0 && in2 == 1 && gate_selected != 0) ){ //|| //Skip gate if it has the same input both ports NOTE THAT IF i == 0 THEN WE SELECT INV.
         return 1;
     }
     
 
     for(int i=0; i<(current_circuit->gate_count-1);i++){
         if(current_circuit->gates[i].gate == &data->gate_types[gate_selected]){
             if(current_circuit->gates[i].in1 == in1 && current_circuit->gates[i].in2 == in2 && current_circuit->gates[i].in3 == in3){
                 return 1; //DETECTED A COMPLETE equivalent circuit
             }
         }
     }
 
     int input_used[current_circuit->gate_count + data->num_inputs+2];
     memset(input_used, 0, sizeof(input_used));
 
     input_used[0] = 1; //make sure that the constant don't trigger a faulty tautology result.
     input_used[1] = 1;
 
     for(int i=0; i<current_circuit->gate_count; i++){
         input_used[current_circuit->gates[i].in1] = 1;
         input_used[current_circuit->gates[i].in2] = 1;
         input_used[current_circuit->gates[i].in3] = 1;
     }
 
     input_used[in1] = 1;
     input_used[in2] = 1;
     input_used[in3] = 1;
     input_used[in4] = 1;
 
     for(int i=0; i < (current_circuit->gate_count + data->num_inputs - NUM_OUTPUTS+2); i++){
         if(input_used[i]==0 && current_circuit->gate_count!=0){
             return 2; //missing an used output
         }
     }
 
     return 0;
 }
 
 void generate_circuits_recursive(Circuit *current_circuit, int depth, ThreadArgs *data) {
     if (depth == data->num_gates){
         // Reached end of amount of gates. 
         return;
     }
 
     GateType* gate_types = data->gate_types;
 
     // Loop through gate types and inputs to build possible circuits
     //int num_gate_types = 1;
     //int division = (num_gate_types + NUM_THREADS-1)/NUM_THREADS;
     //int multi_core_division=NUM_THREADS/num_gate_types;
     //0 - 2, 3 - 5, 6 - 8
     //for (int i = 0; i < num_gate_types; i++) {
     int i = 1; //Only select the multiplexer
 
     if((current_circuit->area+data->gate_types[i].area)>data->best_area){
         //printf("worker %d: area %d on gate type %d and depth %d larger then best area %d continueing\n",data->worker_id,current_circuit->area,i,depth,data->best_area);
         return;
     }
 
     for (int in4 = 0; in4 < depth + data->num_inputs + 2; in4++){
         for (int in3 = 0; in3 < depth + data->num_inputs + 2; in3++){
 
             //Going for multithread approach
             if(in3 != data->worker_id+2 && depth == 0){
                 continue;
             }
 
             for (int in2 = 0; in2 < depth + data->num_inputs + 2; in2++) {
                 for (int in1 = 0; in1 < depth + data->num_inputs + 2; in1++){
                     data->num_circuit[0] += 1;
 
 
 
                     // Add the new gate to the circuit
                     current_circuit->gates[depth].gate = &gate_types[i]; //set pointer to the type of gate
                     current_circuit->gates[depth].in1 = in1;
                     current_circuit->gates[depth].in2 = in2;
                     current_circuit->gates[depth].in3 = in3;
                     current_circuit->gates[depth].in4 = in4;
                     current_circuit->gate_count = depth + 1;
 
                     //if(current_circuit->gates[0].in1 == 0 && current_circuit->gates[0].in2 == 1 && current_circuit->gates[0].in3 == 3 && current_circuit->gates[1].in1 == 2 && current_circuit->gates[1].in2 == 3 && current_circuit->gates[1].in3 == 4 && current_circuit->gates[2].in1 == 4 && current_circuit->gates[2].in2 == 5 && current_circuit->gates[2].in3 == 6){// && current_circuit->gates[2].gate==&data->gate_types[6]){
                     //if(current_circuit->gates[0].in1 == 2 && current_circuit->gates[0].in2 == 3 && current_circuit->gates[0].in3 == 4){
                     //    printf("test\n");
                     //}
 
                     int tautology = detect_tautology(current_circuit,in1,in2,in3,in4,i,data); //0: nothing found, 1: direct tautology, 2:unconnected device may still be connected.
                     if(tautology==1){
                         continue; //Found already unnecessary combo and should skip it
                     }
 
 
                     int valid = 0;
 
                     if(tautology!=2){ //There is an unconnected gate if this holds true
                         valid = 1;
                         int8_t output[NUM_OUTPUTS];
                         for (int y=0; y < (1 << data->num_inputs); y++){ //CHECK IF IT IS VALID
                             evaluate_circuit(data->gate_types, current_circuit, &data->truth_table[y*data->num_inputs], output);
                             for(int z=0; z<NUM_OUTPUTS;z++){
                                 if(output[z]!=data->target_outputs[y+NUM_COMBINATION*z]){
                                     valid = 0;
                                 }
                             }
                         }
                     }
                     //valid circuit add area
                     current_circuit->area += gate_types[i].area;  // Example area increment (modify as needed)
                     
                     if(data->num_circuit[0]%1000000000 == 0){
                         data->num_circuit[1] += 1;
                         data->num_circuit[0] = 0;
                         printf("%d:At circuit number %d M current best_area %d and tested area %d\n",data->worker_id,data->num_circuit[1],data->best_area,current_circuit->area);
                     }
 
                     pthread_mutex_lock(&data->mutex); //get mutex
                     if(valid == 1 && current_circuit->area<data->best_area){
                         //Found a valid solution!
                         memcpy((void *)&data->best_circuit, current_circuit, sizeof(Circuit)); //write to best circuit
                         printf("%d: Found proper solution\n",data->worker_id);
                         print_circuit(current_circuit);
                         write_circuit_to_file(current_circuit,current_circuit->area,data->worker_id,data->num_circuit[0]*100 + data->num_circuit[1]);
                         data->best_area = current_circuit->area;
                     }
                     pthread_mutex_unlock(&data->mutex);
                     // Recurse to add more gates
                     
                     generate_circuits_recursive(current_circuit, depth + 1, data);
                     current_circuit->area -= gate_types[i].area;  // Example area increment (modify as needed)
                     //printf("worker %d: returning with depth %d and area %d\n",data->worker_id,depth,current_circuit->area);
                 }
             }
         }
     }
 }
 
 void* search_space_worker(void* args) {
     // Define and initialize worker-specific parameters and loop through circuits
     // You will need to pass parameters in `args` and cast them in this function
     ThreadArgs *data;
     data = (ThreadArgs *) args;
 
     Circuit current_circuit;
     current_circuit.area = 0;
     current_circuit.gate_count = 0;
 
     printf("%d: best Area %d, Going in recusive loop to check all circuits\n",data->worker_id, data->best_area);
     generate_circuits_recursive(&current_circuit, 0, data);
 
     //finished set worker_id to 1000 to indicate to the management thread that we finished
     pthread_mutex_lock(&data->mutex);
     data->worker_id = 1000;
     pthread_mutex_unlock(&data->mutex);
 
     return NULL;  // Return the best found circuit and area as needed
 }
 
 
 void brute_force_boolean(Circuit* best_circuit, int8_t truth_table[], int8_t target_outputs[], int num_inputs, int max_gates, int max_area) {
     pthread_t threads[NUM_THREADS];
     ThreadArgs thread_args[NUM_THREADS];  // Define `ThreadArgs` to pass data to threads
     int best_area = max_area;
     int total_circuits = 0;
 
 
 
     for (int i = 0; i < NUM_THREADS; i++) {
         thread_args[i].gate_types = gate_types;
         thread_args[i].num_inputs = num_inputs;
         thread_args[i].num_gates = max_gates;
         thread_args[i].best_area = best_area;
         thread_args[i].truth_table = truth_table;
         thread_args[i].target_outputs = target_outputs;
         thread_args[i].worker_id = i;
         thread_args[i].num_circuit[0] = 0;
         thread_args[i].num_circuit[1] = 0;
         pthread_mutex_init(&thread_args[i].mutex, NULL);
         pthread_create(&threads[i], NULL, search_space_worker, (void *)&thread_args[i]);
     }
 
     clock_t begin = clock();
     int number_of_running_threads = NUM_THREADS;
     while(number_of_running_threads>0){
         number_of_running_threads = NUM_THREADS;
         for (int i = 0; i < NUM_THREADS; i++) {
             pthread_mutex_lock(&thread_args[i].mutex); //get lock on the data
 
             //Check if it found a better circuit then known before.
             if(thread_args[i].best_area<best_area){
                 best_area = thread_args[i].best_area;
                 printf("Found best circuit at size %d, on worker: %d\n",best_area,i);
                 memcpy(best_circuit, (void *)&thread_args[i].best_circuit, sizeof(Circuit));
             }
 
             //found a better circuit by another thread. Update data variable so that it does not searche longer where not necessary
             if(thread_args[i].best_area>best_area){
                 printf("setting the best_area size %d, on worker: %d\n",best_area,i);
                 thread_args[i].best_area = best_area;
             }
 
             //lastly check if the thread_closed
             if(thread_args[i].worker_id==1000){
                 number_of_running_threads -= 1;
             }
             pthread_mutex_unlock(&thread_args[i].mutex);
             // Collect best circuits and area from each thread
         }
 
         clock_t toc = clock();
         printf("%f: running number of threads: %d\n",(double)(toc - begin) / (CLOCKS_PER_SEC*number_of_running_threads),number_of_running_threads);
         sleep(5);
     }
     printf("no threads running anymore\n");
     // Output the best circuit
 
     //count total amount of circuits
     for(int i=0;i<NUM_THREADS;i++){
         total_circuits += thread_args[i].num_circuit[1];
     }
 
     printf("Total amount of circuits searched is %d M\n",total_circuits);
 }
 
 void fill_target_outputs(int8_t truth_table[], int8_t target_outputs[], int num_inputs) {
     int num_combinations = NUM_COMBINATION;
     for (int i = 0; i < num_combinations; i++) {
         int inputs[num_inputs];
         for (int j = 0; j < num_inputs; j++) {
             inputs[j] = (i >> j) & 1;  // Extract each bit of i as an input
             truth_table[i*num_inputs+j] = (i >> j) & 1;;
         }
         target_outputs[i] = target_function(inputs);
     }
 }
 
 
 
 int main() {
     // Define target function output
     int8_t target_outputs[NUM_COMBINATION*NUM_OUTPUTS]; // 1<<NUM_INPUTS is equivalent to 2^NUM_INPUTS
     int8_t truth_table[NUM_COMBINATION*NUM_INPUTS]; // create a truth_table the size of target_output with an entry for every input.
     fill_target_outputs(truth_table, target_outputs, NUM_INPUTS);
 
     if(use_truth_table){
         for(int i=0; i<(NUM_COMBINATION*NUM_OUTPUTS); i++){
             target_outputs[i] = target_truth_table[(NUM_COMBINATION*NUM_OUTPUTS-1)-i]-'0'; //load in the truth table but then flipped
         }
     }
 
     Circuit best_circuit;
     brute_force_boolean(&best_circuit, truth_table, target_outputs, NUM_INPUTS, MAX_GATES, MAX_AREA);
 
     printf("Found best solution\n");
     print_circuit(&best_circuit);
     write_circuit_to_file(&best_circuit,best_circuit.area,0,0);
     // Print best circuit details
     return 0;
 }
 
diff --git a/bruteforce_approach/bruteforce_muxig.c b/bruteforce_approach/bruteforce_muxig.c
index 9a44f9f..df632ce 100644
--- a/bruteforce_approach/bruteforce_muxig.c
+++ b/bruteforce_approach/bruteforce_muxig.c
@@ -1,464 +1,473 @@
 #include <stdarg.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <pthread.h>
 #include <stdint.h>
 #include <string.h>
 #include <unistd.h>
 
 // -------------- config
 
 #define MAX_AREA 15000 //Determine the initial max_area
 #define NUM_INPUTS 3 //speaks for itself
-#define MAX_GATES 6 // determine the max_amount of gates
+#define MAX_GATES 5 // determine the max_amount of gates
 #define NUM_THREADS 3 //Needs to be <= 9 or 18 or 27 for efficient splitting the work load
 
 #define use_truth_table 1 //If 1 use the truth table below. If multiple outputs then paste the truth table after another from the [file].truth
-#define target_truth_table "11101000" //exampe here [Target A][Target B] pasted after another. 
-
+//#define target_truth_table "00000000" //exampe here [Target A][Target B] pasted after another. 
+#define target_truth_table "1110100010010110"
 /*
 The truth table matching this is that of a increase in value of the input variables
 Let's say 3 input variables
 
 I3 I2 I1   | O2 O1
 A, B, Cin, | S Cout 
 0, 0,   0, | 0 0
 0, 0,   1, | 1 0
 0, 1,   0, | 1 0
 0, 1,   1, | 0 1
 1, 0,   0, | 1 0
 1, 0,   1, | 0 1
 1, 1,   0, | 0 1
 1, 1,   1, | 1 1
 
 S =     10010110
 Cout =  11101000
 MUX =   11001010
 target_truth_table = "S Cin" = "1110100010010110"
 also means that output B
 */
 //AND = &&, OR = ||, XOR = ^, NOT = !
 int target_function(int inputs[]) {
     return inputs[0] ^ inputs[1];
 }
 
 // -------------- Auto-define
 
 #define NUM_COMBINATION (1 << NUM_INPUTS)
 #define NUM_OUTPUTS (sizeof(target_truth_table)-1)/NUM_COMBINATION
 
 // -------------- structs
 
 typedef struct {
     char* type;
     int area;
 } GateType;
 
 typedef struct {
     GateType* gate;
     int8_t in1;
     int8_t in2;
     int8_t in3;
 } Gate;
 
 typedef struct {
     Gate gates[MAX_GATES];
     int8_t gate_count;
     int area;
 } Circuit;
 
 typedef struct {
     Circuit volatile best_circuit;
     GateType *gate_types;
     int num_inputs;
     int num_gates;
     int volatile best_area;
     int8_t  *truth_table;
     int8_t  *target_outputs;
     int worker_id;
     int num_circuit[2]; //first is the amount in million  and the second is the increment counter.
     pthread_mutex_t mutex;
 } ThreadArgs;
 
 
 // -------------- define used gates
 GateType gate_types[] = {
     {"INV", 1160},
     {"MUX", 1288}
 };
 
 // -------------- start functions
 void tee(FILE *f, char const *fmt, ...) { 
     va_list ap;
     va_start(ap, fmt);
     vprintf(fmt, ap);
     va_end(ap);
     va_start(ap, fmt);
     vfprintf(f, fmt, ap);
     va_end(ap);
 }
 
 void print_circuit(Circuit * circuit){
     FILE *fptr;
 
-    fptr = fopen("../output/output_bruteforce.txt", "a");
+    fptr = fopen("./output/output_bruteforce.txt", "a");
 
     //for(int y=0; y<circuit->gate_count; y++){
     //    printf("%d: %s, in1: %d, in2: %d, in3: %d\n",y,circuit->gates[y].gate->type,circuit->gates[y].in1,circuit->gates[y].in2,circuit->gates[y].in3);
     //}
 
     tee(fptr,"------- Circuit area: %d -------\n",circuit->area);
     tee(fptr,"Input ");
     for(int i='a';(i-'a')<NUM_INPUTS;i++){tee(fptr,"%c, ",i);}
     tee(fptr,"\n");
 
     for(int y=0; y<circuit->gate_count; y++){
         int print_in1 = circuit->gates[y].in1 + '0';
         int print_in2 = circuit->gates[y].in2 + '0';
         int print_in3 = circuit->gates[y].in3 + '0';
         if((print_in1-2-'0')<NUM_INPUTS && (print_in1-2-'0')>=0){
          print_in1 = circuit->gates[y].in1-2 + 'a';
         }
         if((print_in2-2-'0')<NUM_INPUTS && (print_in2-2-'0')>=0){
          print_in2 = circuit->gates[y].in2-2 + 'a';
         }
         if((print_in3-2-'0')<NUM_INPUTS && (print_in3-2-'0')>=0){
          print_in3 = circuit->gates[y].in3-2 + 'a';
         }
-        
-        tee(fptr,"%d: %s, in1: %c, in2: %c, in3: %c\n",y+NUM_INPUTS+2,circuit->gates[y].gate->type,print_in1,print_in2,print_in3);
+        if(circuit->gates[y].in1==1 && circuit->gates[y].in2 == 0){ //Detected inverter
+            tee(fptr,"%d: INV, in1: %c\n",y+NUM_INPUTS+2,print_in3);
+        }else{ //normal muxig
+            tee(fptr,"%d: %s, in1: %c, in2: %c, in3: %c\n",y+NUM_INPUTS+2,circuit->gates[y].gate->type,print_in1,print_in2,print_in3);
+        }
     }
     
     tee(fptr,"Output ");
     for(int i='x';(i-'x')<NUM_OUTPUTS;i++){tee(fptr,"%c:%lu, ",i,NUM_INPUTS+circuit->gate_count-NUM_OUTPUTS+(i-'x')+2);}
     tee(fptr,"\n");
     tee(fptr,"----------------------------------\n");
     fclose(fptr);
 }
 
 void write_circuit_to_file(Circuit * circuit, int area, int worker_number, int file_number){
     FILE *fptr;
 
     char file_name[100];
-    sprintf(file_name, "../output/output_%d_%d_%d_bruteforce.dot", area, worker_number, file_number);
+    sprintf(file_name, "./output/output_%d_%d_%d_bruteforce.dot", area, worker_number, file_number);
 
     fptr = fopen(file_name, "w");
 
     //for(int y=0; y<circuit->gate_count; y++){
     //    printf("%d: %s, in1: %d, in2: %d, in3: %d\n",y,circuit->gates[y].gate->type,circuit->gates[y].in1,circuit->gates[y].in2,circuit->gates[y].in3);
     //}
     fprintf(fptr, "digraph Circuit {\n  rankdir=LR; // Makes the graph left-to-right\n  node [shape=ellipse]; // Default shape for nodes\n ranksep=2; // Increases vertical separation\n");
 
 
     for(int i='a';(i-'a')<NUM_INPUTS;i++){fprintf(fptr,"  %c [ shape=octagon, label=\"%c\", color=\"black\", fontcolor=\"black\"]; \n",i,i);}
 
 
     for(int y=0; y<circuit->gate_count; y++){
         int print_in1 = circuit->gates[y].in1 + '0';
         int print_in2 = circuit->gates[y].in2 + '0';
         int print_in3 = circuit->gates[y].in3 + '0';
         if((print_in1-2-'0')<NUM_INPUTS && (print_in1-2-'0')>=0){
          print_in1 = circuit->gates[y].in1-2 + 'a';
         }
         if((print_in2-2-'0')<NUM_INPUTS && (print_in2-2-'0')>=0){
          print_in2 = circuit->gates[y].in2-2 + 'a';
         }
         if((print_in3-2-'0')<NUM_INPUTS && (print_in3-2-'0')>=0){
          print_in3 = circuit->gates[y].in3-2 + 'a';
         }
         int unit_number = y+NUM_INPUTS+2;
-        fprintf(fptr,"  %d [ shape=record, label=\"{{<p1> in 0|<p2> in 1|<p3> S}| MUX %d |{<p4> Y}}\", color=\"darkred\", fontcolor=\"darkred\" ];\n",unit_number,unit_number);
-        fprintf(fptr,"  %c:e -> %d:p1;\n  %c:e -> %d:p2;\n  %c:e -> %d:p3;\n",print_in1,unit_number,print_in2,unit_number,print_in3,unit_number);
+
+        if(circuit->gates[y].in1==1 && circuit->gates[y].in2 == 0){ //Detected inverter
+            fprintf(fptr,"  %d [ shape=record, label=\"{{<p1> in }|INV %d |{<p4> out}}\", color=\"darkred\", fontcolor=\"darkred\" ];\n",unit_number,unit_number);
+            fprintf(fptr,"  %c:e -> %d:p1;\n",print_in3,unit_number);
+        } else { //normal muxig
+            fprintf(fptr,"  %d [ shape=record, label=\"{{<p1> in 0|<p2> in 1|<p3> S}| MUX %d |{<p4> Y}}\", color=\"darkred\", fontcolor=\"darkred\" ];\n",unit_number,unit_number);
+            fprintf(fptr,"  %c:e -> %d:p1;\n  %c:e -> %d:p2;\n  %c:e -> %d:p3;\n",print_in1,unit_number,print_in2,unit_number,print_in3,unit_number);
+        }
     }
     
     for(int i='x';(i-'x')<NUM_OUTPUTS;i++){fprintf(fptr,"  %lu:e -> %c;\n",NUM_INPUTS+circuit->gate_count-NUM_OUTPUTS+(i-'x')+2,i);}
     
 
     fprintf(fptr,"}\n");
     fclose(fptr);
 }
 
 void evaluate_circuit(GateType* all_gates, Circuit* circuit, int8_t* inputs, int8_t* outputs) {
     int8_t intermediate_outputs[NUM_INPUTS + MAX_GATES+2];
     intermediate_outputs[0] = 0; //Make sure that intermediate_outputs[0] = 0 and [1] = 1 for constant signal attachments
     intermediate_outputs[1] = 1;
     memcpy(&intermediate_outputs[2], inputs, NUM_INPUTS * sizeof(int8_t)); //copy boolean value over this
 
     for (int i = 0; i < circuit->gate_count; i++) {
         int out1 = intermediate_outputs[circuit->gates[i].in1];
         int out2 = intermediate_outputs[circuit->gates[i].in2];
         int out3 = intermediate_outputs[circuit->gates[i].in3];
         int output = 0;
 
         if (circuit->gates[i].gate ==  &all_gates[0]) //INV
             output =  ~out1 & 1;
         else if (circuit->gates[i].gate ==  &all_gates[1]) //MUX
             output =  out3 ? out2 : out1;
 
         intermediate_outputs[NUM_INPUTS + i + 2] = output;
     }
 
     for(int z=0; z<NUM_OUTPUTS;z++){
         outputs[z] = intermediate_outputs[NUM_INPUTS + 2 + circuit->gate_count-NUM_OUTPUTS+z];
     }
 }
 
 int detect_tautology(Circuit *current_circuit, int in1, int in2, int in3, int gate_selected, ThreadArgs *data){
     if ((in1 == in2 && gate_selected != 0) ||
         (in1 == in3 || in2 == in3) ||
         (in1 == 0 && in2 == 1 && gate_selected != 0) ){ //|| //Skip gate if it has the same input both ports NOTE THAT IF i == 0 THEN WE SELECT INV.
         return 1;
     }
     
 
     for(int i=0; i<(current_circuit->gate_count-1);i++){
         if(current_circuit->gates[i].gate == &data->gate_types[gate_selected]){
             if(current_circuit->gates[i].in1 == in1 && current_circuit->gates[i].in2 == in2 && current_circuit->gates[i].in3 == in3){
                 return 1; //DETECTED A COMPLETE equivalent circuit
             }
         }
     }
 
     int input_used[current_circuit->gate_count + data->num_inputs+2];
     memset(input_used, 0, sizeof(input_used));
 
     input_used[0] = 1; //make sure that the constant don't trigger a faulty tautology result.
     input_used[1] = 1;
 
     for(int i=0; i<current_circuit->gate_count; i++){
         input_used[current_circuit->gates[i].in1] = 1;
         input_used[current_circuit->gates[i].in2] = 1;
         input_used[current_circuit->gates[i].in3] = 1;
     }
 
     input_used[in1] = 1;
     input_used[in2] = 1;
     input_used[in3] = 1;
 
     for(int i=0; i < (current_circuit->gate_count + data->num_inputs - NUM_OUTPUTS+2); i++){
         if(input_used[i]==0 && current_circuit->gate_count!=0){
             return 2; //missing an used output
         }
     }
 
     return 0;
 }
 
 void generate_circuits_recursive(Circuit *current_circuit, int depth, ThreadArgs *data) {
     if (depth == data->num_gates){
         // Reached end of amount of gates. 
         return;
     }
 
     GateType* gate_types = data->gate_types;
 
     // Loop through gate types and inputs to build possible circuits
     //int num_gate_types = 1;
     //int division = (num_gate_types + NUM_THREADS-1)/NUM_THREADS;
     //int multi_core_division=NUM_THREADS/num_gate_types;
     //0 - 2, 3 - 5, 6 - 8
     //for (int i = 0; i < num_gate_types; i++) {
     int i = 1; //Only select the multiplexer
 
     if((current_circuit->area+data->gate_types[i].area)>data->best_area){
         //printf("worker %d: area %d on gate type %d and depth %d larger then best area %d continueing\n",data->worker_id,current_circuit->area,i,depth,data->best_area);
         return;
     }
 
     for (int in3 = 2; in3 < depth + data->num_inputs + 2; in3++){
 
         //Going for multithread approach
         if(in3 != data->worker_id+2 && depth == 0){
             continue;
         }
 
         for (int in2 = 0; in2 < depth + data->num_inputs + 2; in2++) {
             for (int in1 = 0; in1 < depth + data->num_inputs + 2; in1++){
                 data->num_circuit[0] += 1;
 
 
 
                 // Add the new gate to the circuit
                 current_circuit->gates[depth].gate = &gate_types[i]; //set pointer to the type of gate
                 current_circuit->gates[depth].in1 = in1;
                 current_circuit->gates[depth].in2 = in2;
                 current_circuit->gates[depth].in3 = in3;
                 current_circuit->gate_count = depth + 1;
 
                 //if(current_circuit->gates[0].in1 == 0 && current_circuit->gates[0].in2 == 1 && current_circuit->gates[0].in3 == 3 && current_circuit->gates[1].in1 == 2 && current_circuit->gates[1].in2 == 3 && current_circuit->gates[1].in3 == 4 && current_circuit->gates[2].in1 == 4 && current_circuit->gates[2].in2 == 5 && current_circuit->gates[2].in3 == 6){// && current_circuit->gates[2].gate==&data->gate_types[6]){
                 //if(current_circuit->gates[0].in1 == 2 && current_circuit->gates[0].in2 == 3 && current_circuit->gates[0].in3 == 4){
                 //    printf("test\n");
                 //}
 
                 int tautology = detect_tautology(current_circuit,in1,in2,in3,i,data); //0: nothing found, 1: direct tautology, 2:unconnected device may still be connected.
                 if(tautology==1){
                     continue; //Found already unnecessary combo and should skip it
                 }
 
 
                 int valid = 0;
 
                 if(tautology!=2){ //There is an unconnected gate if this holds true
                     valid = 1;
                     int8_t output[NUM_OUTPUTS];
                     for (int y=0; y < (1 << data->num_inputs); y++){ //CHECK IF IT IS VALID
                         evaluate_circuit(data->gate_types, current_circuit, &data->truth_table[y*data->num_inputs], output);
                         for(int z=0; z<NUM_OUTPUTS;z++){
                             if(output[z]!=data->target_outputs[y+NUM_COMBINATION*z]){
                                 valid = 0;
                             }
                         }
                     }
                 }
                 //valid circuit add area
                 current_circuit->area += gate_types[i].area;  // Example area increment (modify as needed)
                 
                 if(data->num_circuit[0]%1000000000 == 0){
                     data->num_circuit[1] += 1;
                     data->num_circuit[0] = 0;
                     printf("%d:At circuit number %d M current best_area %d and tested area %d\n",data->worker_id,data->num_circuit[1],data->best_area,current_circuit->area);
                 }
 
                 pthread_mutex_lock(&data->mutex); //get mutex
                 if(valid == 1 && current_circuit->area<data->best_area){
                     //Found a valid solution!
                     memcpy((void *)&data->best_circuit, current_circuit, sizeof(Circuit)); //write to best circuit
                     printf("%d: Found proper solution\n",data->worker_id);
                     print_circuit(current_circuit);
                     write_circuit_to_file(current_circuit,current_circuit->area,data->worker_id,data->num_circuit[0]*100 + data->num_circuit[1]);
                     data->best_area = current_circuit->area;
                 }
                 pthread_mutex_unlock(&data->mutex);
                 // Recurse to add more gates
                 
                 generate_circuits_recursive(current_circuit, depth + 1, data);
                 current_circuit->area -= gate_types[i].area;  // Example area increment (modify as needed)
                 //printf("worker %d: returning with depth %d and area %d\n",data->worker_id,depth,current_circuit->area);
             }
         }
     }
 }
 
 void* search_space_worker(void* args) {
     // Define and initialize worker-specific parameters and loop through circuits
     // You will need to pass parameters in `args` and cast them in this function
     ThreadArgs *data;
     data = (ThreadArgs *) args;
 
     Circuit current_circuit;
     current_circuit.area = 0;
     current_circuit.gate_count = 0;
 
     printf("%d: best Area %d, Going in recusive loop to check all circuits\n",data->worker_id, data->best_area);
     generate_circuits_recursive(&current_circuit, 0, data);
 
     //finished set worker_id to 1000 to indicate to the management thread that we finished
     pthread_mutex_lock(&data->mutex);
     data->worker_id = 1000;
     pthread_mutex_unlock(&data->mutex);
 
     return NULL;  // Return the best found circuit and area as needed
 }
 
 
 void brute_force_boolean(Circuit* best_circuit, int8_t truth_table[], int8_t target_outputs[], int num_inputs, int max_gates, int max_area) {
     pthread_t threads[NUM_THREADS];
     ThreadArgs thread_args[NUM_THREADS];  // Define `ThreadArgs` to pass data to threads
     int best_area = max_area;
     int total_circuits = 0;
 
 
 
     for (int i = 0; i < NUM_THREADS; i++) {
         thread_args[i].gate_types = gate_types;
         thread_args[i].num_inputs = num_inputs;
         thread_args[i].num_gates = max_gates;
         thread_args[i].best_area = best_area;
         thread_args[i].truth_table = truth_table;
         thread_args[i].target_outputs = target_outputs;
         thread_args[i].worker_id = i;
         thread_args[i].num_circuit[0] = 0;
         thread_args[i].num_circuit[1] = 0;
         pthread_mutex_init(&thread_args[i].mutex, NULL);
         pthread_create(&threads[i], NULL, search_space_worker, (void *)&thread_args[i]);
     }
 
     clock_t begin = clock();
     int number_of_running_threads = NUM_THREADS;
     while(number_of_running_threads>0){
         number_of_running_threads = NUM_THREADS;
         for (int i = 0; i < NUM_THREADS; i++) {
             pthread_mutex_lock(&thread_args[i].mutex); //get lock on the data
 
             //Check if it found a better circuit then known before.
             if(thread_args[i].best_area<best_area){
                 best_area = thread_args[i].best_area;
                 printf("Found best circuit at size %d, on worker: %d\n",best_area,i);
                 memcpy(best_circuit, (void *)&thread_args[i].best_circuit, sizeof(Circuit));
             }
 
             //found a better circuit by another thread. Update data variable so that it does not searche longer where not necessary
             if(thread_args[i].best_area>best_area){
                 printf("setting the best_area size %d, on worker: %d\n",best_area,i);
                 thread_args[i].best_area = best_area;
             }
 
             //lastly check if the thread_closed
             if(thread_args[i].worker_id==1000){
                 number_of_running_threads -= 1;
             }
             pthread_mutex_unlock(&thread_args[i].mutex);
             // Collect best circuits and area from each thread
         }
 
         clock_t toc = clock();
         printf("%f: running number of threads: %d\n",(double)(toc - begin) / (CLOCKS_PER_SEC*number_of_running_threads),number_of_running_threads);
         sleep(5);
     }
     printf("no threads running anymore\n");
     // Output the best circuit
 
     //count total amount of circuits
     for(int i=0;i<NUM_THREADS;i++){
         total_circuits += thread_args[i].num_circuit[1];
     }
 
     printf("Total amount of circuits searched is %d M\n",total_circuits);
 }
 
 void fill_target_outputs(int8_t truth_table[], int8_t target_outputs[], int num_inputs) {
     int num_combinations = NUM_COMBINATION;
     for (int i = 0; i < num_combinations; i++) {
         int inputs[num_inputs];
         for (int j = 0; j < num_inputs; j++) {
             inputs[j] = (i >> j) & 1;  // Extract each bit of i as an input
             truth_table[i*num_inputs+j] = (i >> j) & 1;;
         }
         target_outputs[i] = target_function(inputs);
     }
 }
 
 
 
 int main() {
     // Define target function output
     int8_t target_outputs[NUM_COMBINATION*NUM_OUTPUTS]; // 1<<NUM_INPUTS is equivalent to 2^NUM_INPUTS
     int8_t truth_table[NUM_COMBINATION*NUM_INPUTS]; // create a truth_table the size of target_output with an entry for every input.
     fill_target_outputs(truth_table, target_outputs, NUM_INPUTS);
 
     if(use_truth_table){
         for(int i=0; i<(NUM_COMBINATION*NUM_OUTPUTS); i++){
             target_outputs[i] = target_truth_table[(NUM_COMBINATION*NUM_OUTPUTS-1)-i]-'0'; //load in the truth table but then flipped
         }
     }
 
     Circuit best_circuit;
     brute_force_boolean(&best_circuit, truth_table, target_outputs, NUM_INPUTS, MAX_GATES, MAX_AREA);
 
     printf("Found best solution\n");
     print_circuit(&best_circuit);
     write_circuit_to_file(&best_circuit,best_circuit.area,0,0);
     // Print best circuit details
     return 0;
 }
 
diff --git a/bruteforce_approach/run_exhaustive_search.sh b/bruteforce_approach/run_exhaustive_search.sh
new file mode 100755
index 0000000..5c5f311
--- /dev/null
+++ b/bruteforce_approach/run_exhaustive_search.sh
@@ -0,0 +1,39 @@
+#!/bin/bash
+
+D2B_1=({0..1}{0..1})
+D2B_2=({0..1}{0..1}{0..1}{0..1})
+D2B_3=({0..1}{0..1}{0..1}{0..1}{0..1}{0..1}{0..1}{0..1})
+D2B_4=({0..1}{0..1}{0..1}{0..1}{0..1}{0..1}{0..1}{0..1}{0..1}{0..1}{0..1}{0..1}{0..1}{0..1}{0..1}{0..1})
+file="../bruteforce_muxig.c"
+temp_file="./bruteforce_muxig_temp.c"
+
+for inputs in $(seq 3 4); do
+    # Dynamically access the D2B arrays
+    eval "current_array=(\"\${D2B_${inputs}[@]}\")"
+
+    # Iterate through the array elements
+    for i in "${!current_array[@]}"; do
+        binary="${current_array[$i]}"
+        echo "Processing: Input $inputs, Index $i, Binary $binary"
+
+        # Update the file with the current binary
+        if[inputs -le 2]; then
+            sed -e "s|#define target_truth_table \"00000000\"|#define target_truth_table \"$binary\"|" \
+            -e "s|#define NUM_INPUTS 3|#define NUM_INPUTS $inputs|" \
+            "$file" > "$temp_file"
+        else
+            sed -e "s|#define target_truth_table \"00000000\"|#define target_truth_table \"$binary\"|" \
+            -e "s|#define NUM_INPUTS 3|#define NUM_INPUTS $inputs|" \
+            -e "s|#define MAX_GATES 2|#define MAX_GATES 3|" \
+            "$file" > "$temp_file"
+        fi
+
+        # Compile and run the generated C file
+        gcc -pthreads -o bruteforce_muxig_temp "$temp_file"
+        ./bruteforce_muxig_temp
+
+        # Save the output in a structured directory
+        mkdir -p "result_${inputs}/${i}_${binary}"
+        mv ./output/* "result_${inputs}/${i}_${binary}/"
+    done
+done
diff --git a/nem_basic_yosys.lib b/nem_liberty/nem_basic_yosys.lib
similarity index 100%
rename from nem_basic_yosys.lib
rename to nem_liberty/nem_basic_yosys.lib
diff --git a/nem_basic_yosys_extended.lib b/nem_liberty/nem_basic_yosys_extended.lib
similarity index 92%
rename from nem_basic_yosys_extended.lib
rename to nem_liberty/nem_basic_yosys_extended.lib
index 6253d69..9b9d471 100644
--- a/nem_basic_yosys_extended.lib
+++ b/nem_liberty/nem_basic_yosys_extended.lib
@@ -1,2604 +1,2514 @@
 library (nem_basic) {
 comment : "Manually created liberty with more gates - ignore any timing information";
 date : "$April 26th 2024$";
 revision : "0.2";
 delay_model : table_lookup;
 capacitive_load_unit (1,pf);
 time_unit : "1ns";
 current_unit : "1uA";
 voltage_unit : "1V";
 voltage_map (VCC,15);
 voltage_map (GND,0);
 default_cell_leakage_power : 0;
 default_fanout_load : 1;
 default_max_transition : 500;
 default_output_pin_cap : 0;
 input_threshold_pct_rise : 50.0;
 input_threshold_pct_fall : 50.0;
 output_threshold_pct_rise : 50.0;
 output_threshold_pct_fall : 50.0;
 slew_lower_threshold_pct_rise : 20.0;
 slew_lower_threshold_pct_fall : 20.0;
 slew_upper_threshold_pct_rise : 80.0;
 slew_upper_threshold_pct_fall : 80.0;
 slew_derate_from_library : 1.0;
 nom_process : 1;
 nom_temperature : 125;
 nom_voltage : 15;
 
 operating_conditions (NEM_BASIC_COND) {
   process : 1;
   temperature : 125;
   voltage : 29;
 }
 default_operating_conditions : NEM_BASIC_COND;
 
 lu_table_template (delay_template_2x2) {
   variable_1 : input_net_transition;
   variable_2 : total_output_net_capacitance;
   index_1("0.01,0.1");
   index_2("0.02,0.2");
 }
 
 lu_table_template (constraint_template_2x2) {
   variable_1 : constrained_pin_transition;
   variable_2 : related_pin_transition;
   index_1("0.01,0.1");
   index_2("0.02,0.2");
 }
 
 cell(inv_3T) {
   area : 1160;
   cell_footprint : inv_3T;
 /*  cell_description : "NEM 3T Inverter"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (in) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "!(in)";
     max_capacitance : 10;
     max_fanout : 10;
     max_transition : 500;
     timing () {
       related_pin : "in";
       timing_sense : negative_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 
 cell(buf_3T) {
   area : 2240;
   cell_footprint : buf_3T;
 /*  cell_description : "NEM 3T Buffer"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (in) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "in";
     max_capacitance : 10;
     max_fanout : 10;
     max_transition : 500;
     timing () {
       related_pin : "in";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 
 cell(nand_3T) {
   area :  2832;
   cell_footprint : nand_3T;
 /*  cell_description : "NEM 3T 2-Input NAND"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (a) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (b) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "!(a&b)";
     max_fanout : 10;
     timing () {
       related_pin : "a";
       timing_sense : negative_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "b";
       timing_sense : negative_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 
 
 cell(and_3T) {
   area :  3912;
   cell_footprint : and_3T;
   /* cell_description : "NEM 3T 2-Input AND"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (a) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (b) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "a&b";
     max_fanout : 10;
     timing () {
       related_pin : "a";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "b";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 
 cell(nor_3T) {
   area :  2832;
   cell_footprint : nor_3T;
   /* cell_description : "NEM 3T 2-Input NOR"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (a) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (b) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "!(a|b)";
     max_fanout : 10;
     timing () {
       related_pin : "a";
       timing_sense : negative_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "b";
       timing_sense : negative_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 
 cell(or_3T) {
   area :  3952;
   cell_footprint : or_3T;
 /*  cell_description : "NEM 3T 2-Input OR"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (a) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (b) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "a|b";
     max_fanout : 10;
     timing () {
       related_pin : "a";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "b";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 
 cell(xnor_3T) {
   area :  7824;
   cell_footprint : xnor_3T;
 /*  cell_description : "NEM 3T 2-Input XNOR"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (a) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (b) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "!(a^b)";
     max_fanout : 10;
     timing () {
       related_pin : "a";
       timing_sense : non_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "b";
       timing_sense : non_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 
 cell(xor_3T) {
   area :  7824;
   cell_footprint : xor_3T;
 /*  cell_description : "NEM 3T 2-Input XOR"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (a) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (b) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "a^b";
     max_fanout : 10;
     timing () {
       related_pin : "a";
       timing_sense : non_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "b";
       timing_sense : non_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 
 
 cell(mux_3T) {
   area :  8000;
   cell_footprint : mux_3T;
 /*  cell_description : "NEM 3T 2-Input MUX"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   /*bundle(in) {
     members(in_0,in_1);
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }*/
   pin(in_0){
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin(in_1){
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (sel) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "(!sel & in_0) | (sel & in_1)";
     max_fanout : 10;
     timing () {
       related_pin : "in_0";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "in_1";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "sel";
       timing_sense : non_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 
 
 cell(mux_4T) {
   area :  1288;
   cell_footprint : mux_4T;
 /*  cell_description : "NEM 4T 2-Input MUX"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   /*bundle(in) {
     members(in_0,in_1);
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }*/
   pin(in_0){
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin(in_1){
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (sel) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "(!sel & in_0) | (sel & in_1)";
     max_fanout : 10;
     timing () {
       related_pin : "in_0";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "in_1";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "sel";
       timing_sense : non_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 cell(and_4T) {
   area :  1288;
   cell_footprint : and_4T;
 /* cell_description : "NEM 4T 2-Input AND based on muxiplayers pass logic"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (a) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (b) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "a&b";
     max_fanout : 10;
     timing () {
       related_pin : "a";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "b";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 
 cell(nand_4T) {
   area :  2448;
   cell_footprint : and_4T;
 /* cell_description : "NEM 4T 2-Input AND based on muxiplayers pass logic"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (a) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (b) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "!(a&b)";
     max_fanout : 10;
     timing () {
       related_pin : "a";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "b";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 
 cell(and_not_4T) {
   area :  1288;
   cell_footprint : and_4T;
 /* cell_description : "NEM 4T 2-Input AND based on muxiplayers pass logic having inverted input"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (a) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (b) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "a&!(b)";
     max_fanout : 10;
     timing () {
       related_pin : "a";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "b";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 
 cell(or_4T) {
   area :  1288;
   cell_footprint : or_4T;
 /*  cell_description : "NEM 4T 2-Input OR based on muxiplayers pass logic"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (a) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (b) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "a|b";
     max_fanout : 10;
     timing () {
       related_pin : "a";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "b";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 
 cell(nor_4T) {
   area :  2448;
   cell_footprint : or_4T;
 /*  cell_description : "NEM 4T 2-Input NOR based on muxiplayers pass logic"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (a) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (b) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "a|b";
     max_fanout : 10;
     timing () {
       related_pin : "a";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "b";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 
 
 cell(or_not_4T) {
   area :  1288;
   cell_footprint : or_4T;
 /*  cell_description : "NEM 4T 2-Input OR based on muxiplayers pass logic having inverted input"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (a) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (b) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "a|!(b)";
     max_fanout : 10;
     timing () {
       related_pin : "a";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "b";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 
 cell(xor_4T) {
   area :  2448;
   cell_footprint : xor_3T;
 /*  cell_description : "NEM 4T 2-Input XOR based on 2 4T and 3T inverter"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (a) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (b) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "a^b";
     max_fanout : 10;
     timing () {
       related_pin : "a";
       timing_sense : non_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "b";
       timing_sense : non_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 
 cell(xnor_4T) {
   area :  2448;
   cell_footprint : xor_3T;
 /*  cell_description : "NEM 4T 2-Input XNOR based on 2 4T and 3T inverter"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (a) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (b) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (out) {
     direction : "output";
     related_ground_pin : GND;
     related_power_pin : VCC;
     function : "!(a^b)";
     max_fanout : 10;
     timing () {
       related_pin : "a";
       timing_sense : non_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "b";
       timing_sense : non_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
 }
 
-cell(xor_4T_test) {
-  area :  1;
-  cell_footprint : xor_3T;
-/*  cell_description : "NEM 4T 2-Input XOR based on 2 4T needs an inverted input"; */
-  pg_pin (VCC) {
-    pg_type : primary_power;
-    voltage_name : "VCC";
-  }
-  pg_pin (GND) {
-    pg_type : primary_ground;
-    voltage_name : "GND";
-  }
-  pin (a) {
-    direction : "input";
-    related_ground_pin : GND;
-    related_power_pin : VCC;
-    capacitance : 1;
-  }
-  pin (b) {
-    direction : "input";
-    related_ground_pin : GND;
-    related_power_pin : VCC;
-    capacitance : 1;
-  }
-  pin (c) {
-    direction : "input";
-    related_ground_pin : GND;
-    related_power_pin : VCC;
-    capacitance : 1;
-  }
-  pin (out) {
-    direction : "output";
-    related_ground_pin : GND;
-    related_power_pin : VCC;
-    function : "(a&c)|(!(a)&b)";
-    max_fanout : 10;
-    timing () {
-      related_pin : "a";
-      timing_sense : non_unate;
-      timing_type : combinational;
-      cell_rise (delay_template_2x2) {
-        index_1 ("0.01,0.1");
-        index_2 ("0.02,0.2");
-        values ("0.2,2.0","0.21,2.1");
-      }
-      rise_transition (delay_template_2x2) {
-        index_1 ("0.01,0.1");
-        index_2 ("0.02,0.2");
-        values ("0.2,4.0","0.21,4.1");
-      }
-      cell_fall (delay_template_2x2) {
-        index_1 ("0.01,0.1");
-        index_2 ("0.02,0.2");
-        values ("0.2,2.0","0.21,2.1");
-      }
-      fall_transition (delay_template_2x2) {
-        index_1 ("0.01,0.1");
-        index_2 ("0.02,0.2");
-        values ("0.2,4.0","0.21,4.1");
-      }
-    }
-    timing () {
-      related_pin : "b";
-      timing_sense : non_unate;
-      timing_type : combinational;
-      cell_rise (delay_template_2x2) {
-        index_1 ("0.01,0.1");
-        index_2 ("0.02,0.2");
-        values ("0.2,2.0","0.21,2.1");
-      }
-      rise_transition (delay_template_2x2) {
-        index_1 ("0.01,0.1");
-        index_2 ("0.02,0.2");
-        values ("0.2,4.0","0.21,4.1");
-      }
-      cell_fall (delay_template_2x2) {
-        index_1 ("0.01,0.1");
-        index_2 ("0.02,0.2");
-        values ("0.2,2.0","0.21,2.1");
-      }
-      fall_transition (delay_template_2x2) {
-        index_1 ("0.01,0.1");
-        index_2 ("0.02,0.2");
-        values ("0.2,4.0","0.21,4.1");
-      }
-    }
-  }
-  pin_opposite("b","c");
-}
-
 /*
 cell(SR_latch) {
   area : 2704;
   cell_footprint : SR_latch;
  cell_description : "NEM based S-R type Latch"; 
   pin (S) {
     direction : "input";
   }
   pin (R) {
     direction : "input";
   }
   pin (Q) {
     direction : "output";
     function  : "IQ";
   }
   pin (Q_bar) {
     direction : "output";
     function  : "IQB";
   }
   latch (IQ,IQB) {
     preset : "S"
     clear : "R" 
     clear_preset_var1 : L;
     clear_preset_var2 : L;
   }
   statetable (" R S ", " IQ IQB "){
     table :   "H L : - - : L H ,\
                L H : - - : H L ,\
                H H : - - : L L ,\
                L L : - - : N N";
   }
 }
 */
 
 cell(D_latch) {
   area : 9448;
   cell_footprint : D_latch;
 /*  cell_description : "NEM based D type Latch"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }   
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (D) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
     /* data_in_type : data;*/
 /*
     timing() {
       related_pin : "EN";
       timing_type : hold_rising;
       rise_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("-0.2,-2.0","-0.21,-2.1");
       }
       fall_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","-0.21,4.1");
       }
     }
     timing() {
       related_pin : "EN";
       timing_type : setup_rising;
       rise_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("-0.2,-2.0","-0.21,-2.1");
       }
       fall_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","-0.21,4.1");
       }
     }
 */
   }
   pin (EN) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (Q) {
     direction : "output";
     function  : "QOUT";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
 /*
     timing () {
       related_pin : "D";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "EN";
       timing_sense : non_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
 */
   }
   pin (Q_bar) {
     direction : "output";
     function  : "QBOUT";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
 /*
     timing () {
       related_pin : "D";
       timing_sense : negative_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "EN";
       timing_sense : non_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
 */
   }
   latch (QOUT,QBOUT) {
     enable : "EN";
     data_in : "D";
   }
 }
 
 
 cell(D_latch_rst) {
   area : 13432;
   cell_footprint : D_latch_rst;
 /*  cell_description : "NEM based D type Latch with reset"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }   
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (D) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   /*  data_in_type : data;*/
   }
   pin (EN) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (rst) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (Q) {
     direction : "output";
     function  : "QOUT";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
     timing () {
       related_pin : "D";
       timing_sense : positive_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "EN";
       timing_sense : non_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4darkblue.0","0.21,4.1");
       }
     }
   }
   pin (Q_bar) {
     direction : "output";
     function  : "QBOUT";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
     timing () {
       related_pin : "D";
       timing_sense : negative_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
     timing () {
       related_pin : "EN";
       timing_sense : non_unate;
       timing_type : combinational;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
   latch (QOUT,QBOUT) {
     enable : "EN";
     data_in : "D";
     clear : "rst";
   }
 }
 
 cell(D_FF) {
   area : 20056;
   cell_footprint : D_FF;
 /*  cell_description : "NEM based M-S D type Flip Flop"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }   
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (D) {
     nextstate_type : data;
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     max_transition : 0.2;
     capacitance : 1;
     timing () {
       related_pin : "CLK";
       timing_type : hold_rising;
       rise_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("-0.2,-2.0","-0.21,-2.1");
       }
       fall_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","-0.21,4.1");
       }
     }
     timing () {
       related_pin : "CLK";
       timing_type : setup_rising;
       rise_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","-0.21,4.1");
       }
     }
   }
   pin (CLK) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (Q) {
     direction : "output";
     function  : "QOUT";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
     timing () {
       related_pin : "CLK";
       timing_sense : non_unate;
       timing_type : rising_edge;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
   pin (Q_bar) {
     direction : "output";
     function  : "QBOUT";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
     timing () {
       related_pin : "CLK";
       timing_sense : non_unate;
       timing_type : rising_edge;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
   ff (QOUT,QBOUT) {
     clocked_on : "CLK";
     next_state : "D";
   }
 }
 
 cell(D_FF_rst) {
   area : 28184;
   cell_footprint : D_FF_rst;
 /*  cell_description : "NEM based M-S D type Flip Flop with reset"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }   
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (D) {
     nextstate_type : data;
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     max_transition : 0.2;
     capacitance : 1;
     timing () {
       related_pin : "CLK";
       timing_type : hold_rising;
       rise_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("-0.2,-2.0","-0.21,-2.1");
       }
       fall_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","-0.21,4.1");
       }
     }
     timing () {
       related_pin : "CLK";
       timing_type : setup_rising;
       rise_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,-4.0","0.21,4.1");
       }
     }
   }
   pin (rst) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
     timing () {
       related_pin : "CLK";
       timing_type : recovery_rising;
       rise_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("-0.2,-2.0","-0.21,-2.1");
       }
     }
     timing () {
       related_pin : "CLK";
       timing_type : removal_rising;
       rise_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
     }
   }
   pin (CLK) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (Q) {
     direction : "output";
     function  : "QOUT";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
     timing () {
       related_pin : "CLK";
       timing_sense : non_unate;
       timing_type : rising_edge;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
   pin (Q_bar) {
     direction : "output";
     function  : "QBOUT";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
     timing () {
       related_pin : "CLK";
       timing_sense : non_unate;
       timing_type : rising_edge;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
   ff (QOUT,QBOUT) {
     clear      : "rst";
     clocked_on : "CLK";
     next_state : "D";
   }
 }
 
 /* SCAN FUNCTIONALITY HASN'T BEEN ADDED YET */
 cell(S_FF) {
   area : 20056;
   cell_footprint : D_FF;
 /*  cell_description : "NEM based M-S D type Flip Flop with scan functionality";*/
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }   
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (D) {
     nextstate_type : data;
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     max_transition : 0.2;
     capacitance : 1;
     timing () {
       related_pin : "CLK";
       timing_type : hold_rising;
       rise_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("-0.2,-2.0","-0.21,-2.1");
       }
       fall_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","-0.21,4.1");
       }
     }
     timing () {
       related_pin : "CLK";
       timing_type : setup_rising;
       rise_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","-0.21,4.1");
       }
     }
   }
   pin (SI) {
     nextstate_type : data;
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     max_transition : 0.2;
     capacitance : 1;
     timing () {
       related_pin : "CLK";
       timing_type : hold_rising;
       rise_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("-0.2,-2.0","-0.21,-2.1");
       }
       fall_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","-0.21,4.1");
       }
     }
     timing () {
       related_pin : "CLK";
       timing_type : setup_rising;
       rise_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","-0.21,4.1");
       }
     }
   }
   pin (CLK) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (Q) {
     direction : "output";
     function  : "QOUT";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
     timing () {
       related_pin : "CLK";
       timing_sense : non_unate;
       timing_type : rising_edge;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
   pin (Q_bar) {
     direction : "output";
     function  : "QBOUT";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
     timing () {
       related_pin : "CLK";
       timing_sense : non_unate;
       timing_type : rising_edge;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
   ff (QOUT,QBOUT) {
     clocked_on : "CLK";
     next_state : "D";
   }
 }
 
 /* SCAN FUNCTIONALITY HASN'T BEEN ADDED YET */
 cell(S_FF_rst) {
   area : 28184;
   cell_footprint : S_FF_rst;
 /*  cell_description : "NEM based M-S D type Flip Flop with reset and scan functionality"; */
   pg_pin (VCC) {
     pg_type : primary_power;
     voltage_name : "VCC";
   }   
   pg_pin (GND) {
     pg_type : primary_ground;
     voltage_name : "GND";
   }
   pin (D) {
     nextstate_type : data;
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     max_transition : 0.2;
     capacitance : 1;
     timing () {
       related_pin : "CLK";
       timing_type : hold_rising;
       rise_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("-0.2,-2.0","-0.21,-2.1");
       }
       fall_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","-0.21,4.1");
       }
     }
     timing () {
       related_pin : "CLK";
       timing_type : setup_rising;
       rise_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,-4.0","0.21,4.1");
       }
     }
   }
   pin (rst) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
     timing () {
       related_pin : "CLK";
       timing_type : recovery_rising;
       rise_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("-0.2,-2.0","-0.21,-2.1");
       }
     }
     timing () {
       related_pin : "CLK";
       timing_type : removal_rising;
       rise_constraint (constraint_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
     }
   }
   pin (CLK) {
     direction : "input";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
   }
   pin (Q) {
     direction : "output";
     function  : "QOUT";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
     timing () {
       related_pin : "CLK";
       timing_sense : non_unate;
       timing_type : rising_edge;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
   pin (Q_bar) {
     direction : "output";
     function  : "QBOUT";
     related_ground_pin : GND;
     related_power_pin : VCC;
     capacitance : 1;
     timing () {
       related_pin : "CLK";
       timing_sense : non_unate;
       timing_type : rising_edge;
       cell_rise (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       rise_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
       cell_fall (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,2.0","0.21,2.1");
       }
       fall_transition (delay_template_2x2) {
         index_1 ("0.01,0.1");
         index_2 ("0.02,0.2");
         values ("0.2,4.0","0.21,4.1");
       }
     }
   }
   ff (QOUT,QBOUT) {
     clear      : "rst";
     clocked_on : "CLK";
     next_state : "D";
   }
 }
 }
diff --git a/nem_basic_yosys_extended_old.lib b/nem_liberty/nem_basic_yosys_extended_old.lib
similarity index 100%
rename from nem_basic_yosys_extended_old.lib
rename to nem_liberty/nem_basic_yosys_extended_old.lib
diff --git a/nem_basic_yosys_restricted.lib b/nem_liberty/nem_basic_yosys_restricted.lib
similarity index 100%
rename from nem_basic_yosys_restricted.lib
rename to nem_liberty/nem_basic_yosys_restricted.lib
diff --git a/plugins/abc.help b/plugins/abc.help
new file mode 100644
index 0000000..5dbf3d8
--- /dev/null
+++ b/plugins/abc.help
@@ -0,0 +1,6535 @@
+ABC command line: "help -d".
+
+      Welcome to ABC compiled on Sep  4 2024 02:05:06!
+
+ABC9 commands:
+ &acec            &add1hot         &addflop         &anorm          
+ &append          &atree           &b               &back_reach     
+ &bcore           &bidec           &blut            &bmc            
+ &bmci            &bmcs            &bmiter          &brecover       
+ &cec             &cexinfo         &cfraig          &cfs            
+ &chainbmc        &choice          &cof             &compare        
+ &cone            &cycle           &dc2             &dch            
+ &decla           &deepsyn         &demiter         &dfs            
+ &dsd             &dsdb            &dsdinfo         &edge           
+ &embed           &enable          &equiv           &equiv2         
+ &equiv3          &equiv_filter    &equiv_mark      &era            
+ &esop            &exorcism        &extract         &fadds          
+ &false           &fftest          &filter          &flow           
+ &flow2           &flow3           &force           &fraig          
+ &frames          &funabs          &funtrace        &fx             
+ &gen             &gen_hie         &gencex          &genmux         
+ &genqbf          &genrel          &get             &glucose        
+ &glucose2        &gprove          &homoqbf         &icec           
+ &icheck          &if              &if2             &iff            
+ &iiff            &inse            &iso             &isonpn         
+ &isost           &iwls21test      &jf              &kf             
+ &lcorr           &lf              &lneteval        &lnetmap        
+ &lnetopt         &lnetread        &lnetsim         &load           
+ &load2           &loadaig         &maxi            &mesh           
+ &mf              &mfs             &mfsd            &miter          
+ &miter2          &mlgen           &mltest          &move_names     
+ &mprove          &mulfind         &muxdec          &muxpos         
+ &muxstr          &nf              &odc             &of             
+ &pack            &permute         &pfan            &pms            
+ &polyn           &popart          &posplit         &poxsim         
+ &print_truth     &prodadd         &profile         &ps             
+ &psig            &put             &putontop        &qbf            
+ &qvar            &r               &reachm          &reachn         
+ &reachp          &reachy          &read            &read_blif      
+ &read_cblif      &read_stg        &read_ver        &reduce         
+ &reshape         &resim           &resub           &retime         
+ &reveng          &rex2gia         &rexwalk         &rpm            
+ &sat             &satclp          &satenum         &satfx          
+ &satlut          &satsyn          &sattest         &save           
+ &save2           &saveaig         &scl             &scorr          
+ &semi            &setregnum       &show            &shrink         
+ &sif             &sim             &sim2            &sim3           
+ &sim_gen         &sim_print       &sim_read        &sim_write      
+ &simrsb          &slice           &sopb            &speci          
+ &speedup         &splitprove      &splitsat        &sprove         
+ &srm             &srm2            &st              &status         
+ &stochsyn        &str_eco         &struct          &sweep          
+ &syn2            &syn3            &syn4            &synch2         
+ &test            &times           &topand          &trace          
+ &transduction    &transtoch       &trim            &ttopt          
+ &uif             &unate           &undo            &unmap          
+ &verify          &w               &window          &wlut           
+ &write           &write_ver      
+
+usage: &acec [-CT num] [-mdtbvh] <file1> <file2>
+	         combinational equivalence checking for arithmetic circuits
+	-C num : the max number of conflicts at a node [default = 1000]
+	-T num : approximate runtime limit in seconds [default = 0]
+	-m     : toggle miter vs. two circuits [default = two circuits]
+	-d     : toggle using dual output miter [default = no]
+	-t     : toggle using two-word miter [default = no]
+	-b     : toggle working with Booth multipliers [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+	file1  : (optional) the file with the first network
+	file2  : (optional) the file with the second network
+
+usage: &add1hot [-vh]
+	        adds 1-hotness constraints as additional primary outputs
+	-v    : toggle printing verbose information [default = yes]
+	-h    : print the command usage
+
+usage: &addflop [-vh]
+	         adds one flop to the design
+	-v     : toggles printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &anorm [-bvh]
+	         normalize adder trees in the current AIG
+	-b     : toggles working with Booth multipliers [default = no]
+	-v     : toggles printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &append [-vh] <file>
+	         appends <file> to the current AIG using new PIs and POs
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+	<file> : AIGER file with the design to miter
+
+usage: &atree [-ecvwh]
+	         extracts adder tree rooting in primary outputs
+	-e     : toggles adding extra outputs [default = no]
+	-c     : toggles duplicating complete AIG [default = no]
+	-v     : toggles printing verbose information [default = no]
+	-w     : toggles printing very verbose information [default = no]
+	-h     : print the command usage
+
+usage: &b [-N num] [-dasvwh]
+	         performs AIG balancing to reduce delay and area
+	-N num : the max fanout count to skip a divisor [default = 1000000000]
+	-d     : toggle delay only balancing [default = no]
+	-a     : toggle using AND instead of AND/XOR/MUX [default = no]
+	-s     : toggle strict control of area in delay-mode ("&b -d") [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing additional information [default = no]
+	-h     : print the command usage
+
+usage: &back_reach [-FCT <num>] [-vh]
+	         performs backward reachability by circuit cofactoring
+	-F num : the limit on the depth of induction [default = 1000000]
+	-C num : the conflict limit at a node during induction [default = 1000000]
+	-T num : the timeout for property directed reachability [default = 10]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &bcore [-FOTV num] [-vh] <file>
+	         records UNSAT core of the BMC instance
+	-F num : the zero-based index of a timeframe [default = 10]
+	-O num : the zero-based index of a primary output [default = 0]
+	-T num : approximate timeout in seconds [default = 0]
+	-V file: file name with AIG IDs of pivot variables [default = no pivots]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+	<file> : file name to write the resulting proof [default = stdout]
+
+usage: &bidec [-vh]
+	         performs heavy rewriting of the AIG
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &blut [-KC num] [-mravh]
+	           performs AIG balancing for the given LUT size
+	-K num   : LUT size for the mapping (2 <= K <= 6) [default = 6]
+	-C num   : the max number of priority cuts (1 <= C <= 8) [default = 8]
+	-m       : toggle performing MUX restructuring [default = yes]
+	-r       : toggle performing recursive restructuring [default = yes]
+	-a       : toggle performing area-oriented restructuring [default = yes]
+	-v       : toggle printing verbose information [default = no]
+	-h       : print the command usage
+
+usage: &bmc [-SFATK num] [-dscvwh]
+	         performs bounded model checking
+	-S num : the starting timeframe [default = 0]
+	-F num : the maximum number of timeframes [default = 0]
+	-A num : the number of additional frames to unroll [default = 50]
+	-T num : approximate timeout in seconds [default = 0]
+	-K num : the maximum cut size for CNF computation [default = 6]
+	-d     : toggle dumping unfolded timeframes [default = no]
+	-s     : toggle synthesizing unrolled timeframes [default = no]
+	-c     : toggle using old CNF computation [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing information about unfolding [default = no]
+	-h     : print the command usage
+
+usage: &bmci [-FWT num] [-svh]
+	         experimental procedure
+	-F num : the number of timeframes [default = 1000]
+	-W num : the number of machine words [default = 1000]
+	-T num : approximate global runtime limit in seconds [default = 0]
+	-s     : toggles using ternary simulation [default = no]
+	-v     : toggles printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &bmcs [-PCFAT num] [-gevwh]
+	         performs bounded model checking
+	-P num : the number of parallel solvers [default = 1]
+	-C num : the SAT solver conflict limit [default = 0]
+	-F num : the maximum number of timeframes [default = 0]
+	-A num : the number of additional frames to unroll [default = 1]
+	-T num : approximate timeout in seconds [default = 0]
+	-g     : toggle using Glucose 3.0 by Gilles Audemard and Laurent Simon [default = Satoko]
+	-e     : toggle using variable eliminatation [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing information about unfolding [default = no]
+	-h     : print the command usage
+
+usage: &bmiter -I <biNum> [-vh] <file>
+	         creates the boundary miter
+	-I <biNum>:   number of boundary inputs
+	-v     : toggles printing verbose information [default = no]
+	-h     : print the command usage
+	<file> : the implementation file
+
+usage: &brecover -I <biNum> [-vh] <impl> <patch>
+	         recover boundary using SAT-Sweeping
+	-v     : toggles printing verbose information [default = no]
+	-h     : print the command usage
+	-k     : toggle using logic cones in the SAT solver [default = no]
+	-C num : the max number of conflicts at a node [default = 1000000]
+	-e     : toggle checking the equivalence of the result [default = yes]
+	-o     : toggle checking the equivalence of the outsides in verbose [default = yes]
+	<impl> : the implementation aig. (should be equivalent to spec)
+	<patch> : the modified spec. (should be a hierarchical AIG)
+
+usage: &cec [-CT num] [-nmdasxytvwh]
+	         new combinational equivalence checker
+	-C num : the max number of conflicts at a node [default = 1000]
+	-T num : approximate runtime limit in seconds [default = 0]
+	-n     : toggle using naive SAT-based checking [default = no]
+	-m     : toggle miter vs. two circuits [default = two circuits]
+	-d     : toggle using dual output miter [default = no]
+	-a     : toggle writing dual-output miter [default = no]
+	-s     : toggle silent operation [default = no]
+	-x     : toggle using new solver [default = no]
+	-y     : toggle using new solver [default = no]
+	-t     : toggle using simulation [default = no]
+	-v     : toggle verbose output [default = no]
+	-w     : toggle printing SAT solver statistics [default = no]
+	-h     : print the command usage
+
+usage: &cexinfo [-vh]
+	         prints information about the current counter-example
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &cfraig [-WC <num>] [-acvh]
+	         performs combinational SAT sweeping under constraints
+	         which are present in the AIG or set manually using "constr"
+	         (constraints are listed as last POs and true when they are 0)
+	-W num : the number of simulation words [default = 1]
+	-C num : the max number of conflicts at a node [default = 1000]
+	-a     : toggle appending constraints to the result [default = no]
+	-c     : toggle performing internal verification [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &cfs [-LNURPrcdvh]
+	          performs simulation
+	-L num  : the limit on the number of occurrences [default = 0]
+	-N num  : the number of repetions of each pattern [default = 1]
+	-U num  : what to do with unseen patterns [default = 2]
+	-R num  : what to do with rare patterns [default = 2]
+	-P num  : base2-log of ramdom flip probability [default = 0.000000]
+	-r      : toggle replacing rare patterns [default = no]
+	-c      : toggle inserting constants [default = no]
+	-d      : toggle using only DAG nodes [default = no]
+	-v      : toggle printing verbose information [default = no]
+	-h      : print the command usage
+
+usage: &chainbmc [-FC <num>] [-vwh]
+	           runs a specialized flavor of BMC
+	-F <num> : the max number of timeframes (0 = unused) [default = 200]
+	-C <num> : the max number of conflicts (0 = unused) [default = 0]
+	-v       : toggle printing verbose information [default = no]
+	-w       : toggle printing even more information [default = no]
+	-h       : print the command usage
+
+usage: &choice [-C num] [-cvh]
+	         performs computation of structural choices
+	-C num : the max number of conflicts at a node [default = 1000]
+	-c     : toggle using circuit-based SAT solver [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &cof [-VCLN num] [-vh]
+	         performs cofactoring w.r.t. variable(s)
+	-V num : the zero-based ID of one variable to cofactor [default = 0]
+	-C num : cofactor one variable with a given constant (0 or 1) [default = unused]
+	-L num : cofactor vars with fanout count higher than this [default = 0]
+	-N num : cofactoring the given number of last input variables [default = 0]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &compare <file1> <file2> [-fvh]
+	         compared two AIGs for structural similarity
+	-f     : toggle functional comparison [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &cone [-ORPLW num] [-aecvh]
+	         extracting multi-output sequential logic cones
+	-O num : the index of first PO to extract [default = -1]
+	-R num : (optional) the number of outputs to extract [default = 1]
+	-P num : (optional) the partition number to extract [default = -1]
+	-L num : (optional) extract cones with higher level [default = 0]
+	-W num : (optional) extract cones falling into this window [default = 0]
+	-a     : toggle keeping all CIs or structral support only [default = structural]
+	-e     : toggle writing all outputs into individual files [default = no]
+	-c     : toggle performing cone extraction combinationally [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &cycle [-F num] [-cvh]
+	         cycles sequential circuit for the given number of timeframes
+	         to derive a new initial state (which may be on the envelope)
+	-F num : the number of frames to simulate [default = 10]
+	-c     : toggle using PI values from the current CEX [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &dc2 [-lvh]
+	         performs heavy rewriting of the AIG
+	-l     : toggle level update during rewriting [default = yes]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &dch [-WCS num] [-sptfremngcxyvh]
+	         computes structural choices using a new approach
+	-W num : the max number of simulation words [default = 8]
+	-C num : the max number of conflicts at a node [default = 1000]
+	-S num : the max number of SAT variables [default = 5000]
+	-s     : toggle synthesizing three snapshots [default = yes]
+	-p     : toggle power-aware rewriting [default = no]
+	-t     : toggle simulation of the TFO classes [default = yes]
+	-f     : toggle using lighter logic synthesis [default = no]
+	-r     : toggle skipping choices with redundant support [default = no]
+	-e     : toggle computing and merging equivalences [default = no]
+	-m     : toggle minimizing logic level after merging equivalences [default = no]
+	-n     : toggle selecting random choices while merging equivalences [default = no]
+	-g     : toggle using GIA to prove equivalences [default = no]
+	-c     : toggle using circuit-based SAT vs. MiniSat [default = no]
+	-x     : toggle using new choice computation [default = no]
+	-y     : toggle using new choice computation [default = no]
+	-v     : toggle verbose printout [default = no]
+	-h     : print the command usage
+
+usage: &decla [-bvh]
+	         removes carry look ahead adders
+	-b     : toggles working with Booth multipliers [default = no]
+	-v     : toggles printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &deepsyn [-IJTAS <num>] [-tvh]
+	           performs synthesis
+	-I <num> : the number of iterations [default = 1]
+	-J <num> : the number of steps without improvements [default = 1000000000]
+	-T <num> : the timeout in seconds (0 = no timeout) [default = 0]
+	-A <num> : the number of nodes to stop (0 = no limit) [default = 0]
+	-S <num> : user-specified random seed (0 <= num <= 100) [default = 0]
+	-t       : toggle using two-input LUTs [default = no]
+	-v       : toggle printing optimization summary [default = no]
+	-h       : print the command usage
+
+usage: &demiter [-ftdvh]
+	         decomposes a miter (by default, tries to extract an OR gate)
+	-f     : write files with two sides of a dual-output miter [default = no]
+	-t     : write files with two sides of a two-word miter [default = no]
+	-d     : take single-output and decompose into dual-output [default = no]
+	-v     : toggles printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &dfs [-nfolvh]
+	        orders objects in the DFS order
+	-n    : toggle using normalized ordering [default = no]
+	-f    : toggle using reverse fanin traversal order [default = no]
+	-o    : toggle using reverse output traversal order [default = no]
+	-l    : toggle using levelized order [default = no]
+	-v    : toggle printing verbose information [default = no]
+	-h    : print the command usage
+
+usage: &dsd [-vh]
+	         performs DSD-based collapsing
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &dsdb [-LWKCR num] [-vh]
+	         performs DSD balancing
+	-L num : optimize paths above this level [default = 0]
+	-W num : optimize paths falling into this window [default = 0]
+	-K num : the number of LUT inputs (LUT size) [default = 6]
+	-C num : the number of cuts at a node [default = 8]
+	-R num : the delay relaxation ratio (num >= 0) [default = 0]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &dsdinfo [-V num] [-dvh]
+	          computes and displays information related to DSD
+	-V num  : the zero-based index of the input variable [default = -1]
+	-d      : toggles showing DSD structure [default = no]
+	-v      : toggles printing verbose information [default = no]
+	-h      : print the command usage
+
+usage: &edge [-CDFE num] [-rpomdvh]
+	           find edge assignment of the LUT-mapped network
+	-C num   : the SAT solver conflict limit (0 = unused) [default = 0]
+	-D num   : the upper bound on delay [default = 0]
+	-F num   : skip using edge if fanout higher than this [default = 0]
+	-E num   : the limit on the number of edges (1 <= num <= 2) [default = 1]
+	-r       : toggles using reverse order [default = no]
+	-p       : toggles deriving edges from packing [default = no]
+	-o       : toggles using old algorithm [default = no]
+	-m       : toggles combining edge assignment with mapping [default = no]
+	-d       : toggles dynamic addition of clauses [default = yes]
+	-v       : toggles verbose output [default = no]
+	-h       : prints the command usage
+
+usage: &embed [-DI <num>] [-rdlscvh]
+	         fast placement based on high-dimensional embedding from
+	         D. Harel and Y. Koren, "Graph drawing by high-dimensional
+	         embedding", J. Graph Algs & Apps, 2004, Vol 8(2), pp. 195-217
+	-D num : the number of dimensions for embedding [default = 30]
+	-I num : the number of refinement iterations [default = 10]
+	-r     : toggle the use of refinement [default = no]
+	-c     : toggle clustered representation [default = no]
+	-d     : toggle dumping placement into a Gnuplot file [default = no]
+	-l     : toggle dumping Gnuplot for large placement [default = no]
+	-s     : toggle showing image if Gnuplot is installed [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: &enable [-rvh]
+	         adds or removes flop enable signals
+	-r     : toggle adding vs. removing enables [default = add]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &equiv [-WFRST num] [-smdvh]
+	         computes candidate equivalence classes
+	-W num : the number of words to simulate [default = 31]
+	-F num : the number of frames to simulate [default = 100]
+	-R num : the max number of simulation rounds [default = 20]
+	-S num : the max number of rounds w/o refinement to stop [default = 3]
+	-T num : approximate runtime limit in seconds [default = 0]
+	-s     : toggle seq vs. comb simulation [default = no]
+	-m     : toggle miter vs. any circuit [default = circuit]
+	-d     : toggle using two POs instead of XOR [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &equiv2 [-FCRTS num] [-xlvh]
+	         computes candidate equivalence classes
+	-F num : the max number of frames for BMC [default = 20]
+	-C num : the max number of conflicts at a node [default = 500]
+	-R num : the max number of BMC rounds [default = 10]
+	-T num : runtime limit in seconds for all rounds [default = 0]
+	-S num : runtime limit in seconds for one round [default = 0]
+	-x     : toggle using the current cex to perform refinement [default = no]
+	-l     : toggle considering only latch output equivalences [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &equiv3 [-FWRSNT num] [-mxlvh]
+	         computes candidate equivalence classes
+	-F num : the max number of frames for BMC [default = 20]
+	-W num : the number of words to simulate [default = 50]
+	-R num : the max number of simulation rounds [default = 0]
+	-S num : the number of rounds before a restart [default = 0]
+	-N num : random number seed (1 <= num <= 1000) [default = 0]
+	-T num : runtime limit in seconds for all rounds [default = 0]
+	-m     : toggle miter vs. any circuit [default = circuit]
+	-x     : toggle using the current CEX to perform refinement [default = no]
+	-l     : toggle considering only latch output equivalences [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &equiv_filter [-vh]
+	              filters equivalence candidates after disproving some SRM outputs
+	              (the array of disproved outputs should be given as pAbc->vAbcObjIds)
+	-v          : toggle printing verbose information [default = no]
+	-h          : print the command usage
+
+usage: &equiv_mark [-fvh] <miter.aig>
+	              marks equivalences using an external miter
+	-f          : toggle the use of filtered equivalences [default = no]
+	-v          : toggle printing verbose information [default = no]
+	-h          : print the command usage
+	<miter.aig> : file with the external miter to read
+	              
+	              The external miter should be generated by &srm -s
+	              and (partially) solved by any verification engine(s).
+	              The external miter should have as many POs as
+	              the number of POs in the current AIG plus
+	              the number of equivalences in the current AIG.
+	              If some POs are proved, the corresponding equivs
+	              are marked as proved, to be reduced by &reduce.
+
+usage: &era [-S num] [-mcdvh]
+	          explicit reachability analysis for small sequential AIGs
+	-S num  : the max number of states (num > 0) [default = 1000000000]
+	-m      : stop when the miter output is 1 [default = no]
+	-c      : use state cubes instead of state minterms [default = yes]
+	-d      : toggle dumping STG into a file [default = no]
+	-v      : print verbose information [default = no]
+	-h      : print the command usage
+
+usage: &esop [-vh]
+	         derives Exclusive Sum of Products from AIG
+	-v     : toggles printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &exorcism [-Q N] [-V N] [-C N] -q [file_in] <file_out>
+                     performs heuristic exclusive sum-of-project minimization
+        -Q N       : minimization quality [default = 2]
+                     increasing this number improves quality and adds to runtime
+        -V N       : verbosity level [default = 0]
+                     0 = no output; 1 = outline; 2 = verbose
+        -C N       : maximum number of cubes in startign cover [default = 20000]
+        -q         : toggle using quantum cost [default = no]
+        [file_in]  : optional input file in ESOP-PLA format (otherwise current AIG is used)
+        <file_out> : output file in ESOP-PLA format
+
+
+usage: &extract [-K <num>] [-vh]
+	           extract shared logic for XOR-rich circuits
+	-K <num> : the minimum gate size to consider for extraction [default = 3]
+	-a       : toogle extracting ANDs instead of XORs [default = no]
+	-v       : print verbose information [default = no]
+	-h       : print the command usage
+
+usage: &fadds [-NBSLP num] [-nafxvh]
+	         detects full-adder chains and puts them into white boxes
+	-n     : toggles detecting natural full-adder chains [default = no]
+	-N num : minimum length of a natural full-adder chain to detect [default = 3]
+	-a     : toggles detecting artificial full-adder chains [default = no]
+	-B num : full-adder box delay (percentage of AND-gate delay) [default = 0]
+	-S num : minimum length of an artificial full-adder chain [default = 3]
+	-L num : maximum length of an artificial full-adder chain [default = 32]
+	-P num : maximum number of artificial full-adder chains to detect [default = 50]
+	-f     : toggles allowing external fanouts in artificial chains [default = no]
+	-x     : toggles using XOR to generate fanouts in artificial chains [default = no]
+	-b     : toggles ignoring boxes when computing delays [default = no]
+	-v     : toggles printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &false [-ST num] [-vwh]
+	         detecting and elimintation false paths
+	-S num : maximum slack to identify false paths [default = 0]
+	-T num : approximate runtime limit in seconds [default = 0]
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing additional information [default = no]
+	-h     : print the command usage
+
+usage: &fftest [-ATNK num] [-kbsfcdeunvh] <file> [-GF file] [-S str]
+	          performs functional fault test generation
+	-A num  : selects fault model for all gates [default = 0]
+	                0: fault model is not selected (use -S str)
+	                1: delay fault testing for sequential circuits
+	                2: traditional stuck-at fault: -S (((a&b)&~p)|q)
+	                3: complement fault: -S ((a&b)^p)
+	                4: functionally observable fault
+	-T num  : specifies approximate runtime limit in seconds [default = 0]
+	-N num  : specifies iteration to check for fixed parameters [default = 0]
+	-K num  : specifies cardinality constraint (num > 0) [default = unused]
+	-k      : toggles non-strict cardinality (n <= K, instead of n == K) [default = no]
+	-b      : toggles testing for single faults (the same as "-K 1") [default = no]
+	-s      : toggles starting with the all-0 and all-1 patterns [default = no]
+	-f      : toggles faults at flop inputs only with "-A 1" and "-S str" [default = no]
+	-c      : toggles checking if there are untestable faults [default = no]
+	-d      : toggles dumping test patterns into file "<file>_tests.txt" [default = no]
+	-e      : toggles dumping test pattern pairs (delay faults only) [default = no]
+	-u      : toggles dumping untestable faults into "<file>_untest.txt" [default = no]
+	-n      : toggles dumping faults not detected by a given test set [default = no]
+	-v      : toggles printing verbose information [default = no]
+	-h      : print the command usage
+	<file>  : (optional) file name with input test patterns
+
+	-G file : (optional) file name with the golden model
+
+	-F file : (optional) file name with the fault model in BLIF format
+	-S str  : (optional) string representing the fault model
+	          The following notations are used:
+	            Functional variables: {a,b} (both a and b are always present)
+	            Parameter variables: {p,q,r,s,t,u,v,w} (any number from 1 to 8)
+	            Boolean operators: AND(&), OR(|), XOR(^), MUX(?:), NOT(~)
+	            Parentheses should be used around each operator. Spaces not allowed.
+	            Complement (~) is only allowed before variables (use DeMorgan law).
+	            Examples:
+	              (((a&b)&~p)|q)        stuck-at-0/1 at the output
+	              (((a&~p)|q)&b)        stuck-at-0/1 at input a
+	              (((a|p)&(b|q))&~r)    stuck-at-1 at the inputs and stuck-at-0 at the output
+	              (((a&~p)&(b&~q))|r)   stuck-at-0 at the inputs and stuck-at-1 at the output
+	              ((a&b)^p)             complement at the output
+	              (((a^p)&(b^q))^r)     complement at the inputs and at the output
+	              (a?(b?~s:r):(b?q:p))  functionally observable fault at the output
+	              (p?(a|b):(a&b))       replace AND by OR
+	           If the BLIF file is used for the formula with option '-F', following rules apply:
+	              - the network should be combinational and have exactly one primary output
+	              - input names should have only one character:
+	                {a, b} (for functional variables)
+	                {p,q,r,s,t,u,v,w} (for parameter variables)
+
+usage: &filter [-fgivh] <PartA_FileName> <PartB_FileName>
+	         performs filtering of equivalence classes
+	         (if Parts A/B are given, removes classes composed of one part)
+	-f     : toggle removing all elements except flops [default = no]
+	-g     : toggle removing classes without flops [default = no]
+	-i     : toggle using flop inputs instead of flop outputs [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &flow [-KC num] [-tmvh]
+	         integration optimization and mapping flow
+	-K num : the number of LUT inputs (LUT size) [default = 6]
+	-C num : the number of cuts at a node [default = 8]
+	-t     : toggle minimizing average rather than max delay [default = no]
+	-m     : toggle using "mfs2" in the script [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &flow2 [-KC num] [-btmvh]
+	         integration optimization and mapping flow
+	-K num : the number of LUT inputs (LUT size) [default = 6]
+	-C num : the number of cuts at a node [default = 8]
+	-b     : toggle using SOP balancing during synthesis [default = no]
+	-t     : toggle minimizing average (not maximum) level [default = no]
+	-m     : toggle using "mfs2" in the script [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &flow3 [-KC num] [-btmlvh]
+	         integration optimization and mapping flow
+	-K num : the number of LUT inputs (LUT size) [default = 6]
+	-C num : the number of cuts at a node [default = 8]
+	-b     : toggle using SOP balancing during synthesis [default = no]
+	-t     : toggle minimizing average (not maximum) level [default = no]
+	-m     : toggle using "mfs2" in the script [default = yes]
+	-l     : toggle using previously entered LUT library [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &force [-I <num>] [-cvh]
+	         one-dimensional placement algorithm FORCE introduced by
+	         F. A. Aloul, I. L. Markov, and K. A. Sakallah (GLSVLSI�03).
+	-I num : the number of refinement iterations [default = 20]
+	-c     : toggle clustered representation [default = yes]
+	-v     : toggle verbose output [default = yes]
+	-h     : print the command usage
+
+usage: &fraig [-JWRILDCNPM <num>] [-F filename] [-rmdckngxysopwvh]
+	         performs combinational SAT sweeping
+	-J num : the solver type [default = 2]
+	-W num : the number of simulation words [default = 4]
+	-R num : the number of simulation rounds [default = 10]
+	-I num : the number of sweeping iterations [default = 2000]
+	-L num : the max number of levels of nodes to consider [default = 0]
+	-D num : the max number of steps of speculative reduction [default = 0]
+	-C num : the max number of conflicts at a node [default = 1000000]
+	-N num : the min number of calls to recycle the solver [default = 500]
+	-P num : the number of pattern generation iterations [default = 100]
+	-M num : the node count limit to call the old sweeper [default = 0]
+	-F file: the file name to dump primary output information [default = none]
+	-r     : toggle the use of AIG rewriting [default = no]
+	-m     : toggle miter vs. any circuit [default = circuit]
+	-d     : toggle using double output miters [default = no]
+	-c     : toggle using circuit-based solver [default = no]
+	-k     : toggle using logic cones in the SAT solver [default = no]
+	-n     : toggle using new implementation [default = no]
+	-g     : toggle using another new implementation [default = no]
+	-x     : toggle using another new implementation [default = no]
+	-y     : toggle using another new implementation [default = no]
+	-s     : toggle dumping equivalences into a file [default = no]
+	-o     : toggle using the old SAT sweeper [default = no]
+	-p     : toggle trying to prove when running the old SAT sweeper [default = no]
+	-w     : toggle printing even more verbose information [default = no]
+	-q     : toggle printing additional information for boundary miters [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &frames [-FL <num>] [-soibavh]
+	         unrolls the design for several timeframes
+	-F num : the number of frames to unroll [default = 32]
+	-L num : the limit on fanout count of resets/enables to cofactor [default = 0]
+	-s     : toggle disabling structural hashing [default = no]
+	-o     : toggle ORing corresponding POs [default = no]
+	-i     : toggle initializing registers [default = no]
+	-b     : toggle computing special AIG for BMC [default = no]
+	-a     : toggle using new algorithm [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &funabs [-KR num] [-epvh] <node1> <node2> ... <nodeN>
+	          generates an abstraction of the function
+	-K num  : the number of primary inputs [default = 6]
+	-R num  : the number of random K-set to try [default = 0]
+	-e      : toggles enumerating bound sets of the given size [default = no]
+	-p      : toggles printing statistics only [default = no]
+	-v      : toggles printing verbose information [default = no]
+	-h      : print the command usage
+	<nodes> : the index list of primary inputs to be abstrated
+
+usage: &funtrace [-C num] [-vh] <truth>
+	          traces the presence of the function in the current AIG
+	-C num  : the number of cuts to compute at each node [default = 8]
+	-v      : toggles printing verbose information [default = no]
+	-h      : print the command usage
+	<truth> : truth table in the hexadecimal notation
+
+usage: &fx [-NM <num>] [-vh]
+	           extract shared logic using the classical "fast_extract" algorithm
+	-N <num> : max number of divisors to extract during this run [default = 1000000]
+	-M <num> : upper bound on literal count of divisors to extract [default = 0]
+	-r       : reversing variable order during ISOP computation [default = no]
+	-v       : print verbose information [default = no]
+	-w       : toggle printing additional information [default = no]
+	-h       : print the command usage
+
+usage: &gen [-AKNDLBMxvh]
+	          generates network
+	-A num  : the generation algorithm [default = 0]
+	-K num  : the number of LUT inputs [default = 6]
+	-N num  : the number of LUTs on one level [default = 256]
+	-D num  : the number of LUT levels [default = 8]
+	-L num  : limit below which we randomize [default = 0]
+	-B num  : select best fanins among this many tries [default = 1]
+	-M num  : the multiplier type (1=array, 2=booth) [default = 0]
+	-x      : toggle using XOR gates [default = yes]
+	-v      : toggle printing verbose information [default = no]
+	-h      : print the command usage
+
+usage: &gen_hie [-F <file>] [-vh] <file[1]> <file[2]> ...  <file[N]>
+	            generates a hierarchical design in Verilog
+	-F <file> : the output file name (optional) [default = "sandwich.v"]
+	-v        : toggles printing verbose information [default = no]
+	-h        : print the command usage
+	<files>   : the AIG files for the instance modules
+	            (the PO count of <file[i]> should not be less than the PI count of <file[i+1]>)
+
+usage: &gencex [-CM num] [-F file] [-stcvh]
+	          generates satisfying assignments for each output of the miter
+	-C num  : the number of timeframes [default = 1]
+	-M num  : the max simulation runs before using SAT [default = 10]
+	-F file : the output file name [default = cexes.txt]
+	-s      : toggles using reverse simulation [default = 1640539552]
+	-t      : toggles using SAT solving [default = 1640539552]
+	-c      : toggles outputing care literals only [default = 1640429008]
+	-v      : toggles printing verbose information [default = 1640429008]
+	-h      : print the command usage
+
+usage: &genmux [-K <num>] [-vh] <string>
+	         generates the multiplexer
+	-K num : the number of control inputs [default = undefined]
+	-v     : toggles printing verbose information [default = no]
+	-h     : print the command usage
+	string : the sizes of control input groups
+
+usage: &genqbf [-FKN num] [-ovh]
+	         generates QBF miter for computing an inductive invariant
+	-F num : the number of time frames for induction [default = 1]
+	-K num : the LUT size [default = 6]
+	-N num : the number of LUTs [default = 1]
+	-o     : toggle using the last output [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: &genrel [-I n1,n2,...nN] [-O m1,m2,...,mM] [-vh] <filename>
+	          generates Boolean relation for the given logic window
+	-I list : comma-separated list of window inputs [default = undefined]
+	-O list : comma-separated list of window outputs [default = undefined]
+	-v      : toggles printing verbose information [default = 1640429008]
+	-h      : print the command usage
+	<file>  : the output file name (PLA format extended to represented Boolean relations)
+
+usage: &get [-cmnvh] <file>
+	         converts the current network into GIA and moves it to the &-space
+	         (if the network is a sequential logic network, normalizes the flops
+	         to have const-0 initial values, equivalent to "undc; st; zero")
+	-c     : toggles allowing simple GIA to be imported [default = no]
+	-m     : toggles preserving the current mapping [default = no]
+	-n     : toggles saving CI/CO names of the AIG [default = no]
+	-v     : toggles additional verbose output [default = no]
+	-h     : print the command usage
+	<file> : the file name
+
+usage: &glucose [-C num] [-pdvh] <file.cnf>
+	             run Glucose 3.0 by Gilles Audemard and Laurent Simon
+	-C num     : conflict limit [default = 0]
+	-p         : enable preprocessing [default = 1]
+	-d         : enable dumping CNF after proprocessing [default = 0]
+	-v         : verbosity [default = 0]
+	-h         : print the command usage
+	<file.cnf> : (optional) CNF file to solve
+
+usage: &glucose2 [-C num] [-pvh] <file.cnf>
+	             run Glucose 3.0 by Gilles Audemard and Laurent Simon
+	-C num     : conflict limit [default = 0]
+	-p         : enable preprocessing [default = 1]
+	-v         : verbosity [default = 0]
+	-h         : print the command usage
+	<file.cnf> : (optional) CNF file to solve
+
+usage: &gprove [-GS num] [-vh]
+	         proves multi-output testcase by splitting outputs into groups
+	         (currently, group size more than one works only for "bmc3" and "pdr")
+	-G num : the size of one group [default = 1]
+	-S str : the command line to be executed for each group [default = none]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &homoqbf [-KN num] [-vh]
+	         generates QBF miter for the encoding problem
+	-K num : the LUT size [default = 2]
+	-N num : the number of LUTs [default = 3]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: &icec [-CT num] [-axvwh]
+	         combinational equivalence checker for inverse circuits
+	-C num : the max number of conflicts at a node [default = 1000]
+	-T num : approximate runtime limit in seconds [default = 0]
+	-a     : toggle writing the miter [default = no]
+	-x     : toggle using new solver [default = no]
+	-v     : toggle verbose output [default = no]
+	-w     : toggle printing SAT solver statistics [default = no]
+	-h     : print the command usage
+
+usage: &icheck [-MT num] [-esrbdvh]
+	         performs specialized induction check
+	-M num : the number of timeframes used for induction [default = 1]
+	-T num : approximate global runtime limit in seconds [default = 0]
+	-e     : toggle using empty set of next-state functions [default = no]
+	-s     : toggle searching for a minimal subset [default = yes]
+	-r     : toggle searching in the reverse order [default = no]
+	-b     : toggle searching in backward order from POs [default = no]
+	-d     : toggle printing out the resulting set [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+Error: Empty GIA network.
+
+usage: &if2 [-KCD num] [-tmzrcuxvwh]
+	           performs technology mapping of the network
+	-K num   : sets the LUT size for the mapping [default = 6]
+	-C num   : the max number of priority cuts (0 < num < 2^12) [default = 8]
+	-D num   : sets the delay constraint for the mapping [default = best possible]
+	-t       : enables using AND/XOR/MUX nodes instead of simple AIG [default = no]
+	-m       : enables cut minimization by removing vacuous variables [default = no]
+	-z       : toggles deriving LUTs when mapping into LUT structures [default = no]
+	-r       : toggles using one round of mapping [default = no]
+	-c       : toggles mapping for CNF computation [default = no]
+	-u       : toggles mapping for AIG computation [default = no]
+	-x       : toggles mapping for standard cells [default = no]
+	-v       : toggles verbose output [default = no]
+	-w       : toggles very verbose output [default = no]
+	-h       : prints the command usage
+
+usage: &iff [-vh]
+	           performs structural mapping into LUT structures
+	-v       : toggle printing optimization summary [default = no]
+	-h       : print the command usage
+
+usage: &iiff [-KC num] [-gclvh] <file>
+	           performs techology mapping
+	-K num   : the maximum LUT size [default = 8]
+	-C num   : the maximum cut count [default = 12]
+	-g       : toggle using gates [default = no]
+	-c       : toggle using cells [default = no]
+	-l       : toggle using LUTs  [default = no]
+	-v       : toggle verbose output [default = no]
+	-h       : print the command usage
+	<file>   : (optional) output file name
+
+usage: &inse [-FWT num] [-svh]
+	         experimental procedure
+	-F num : the number of timeframes [default = 10]
+	-W num : the number of machine words [default = 1000]
+	-T num : approximate global runtime limit in seconds [default = 0]
+	-s     : toggles using ternary simulation [default = no]
+	-v     : toggles printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &iso [-neqdvwh]
+	         removes POs with isomorphic sequential COI
+	-n     : toggle using new fast algorithm [default = yes]
+	-e     : toggle computing lower bound on equivalence classes [default = no]
+	-q     : toggle improving quality at the expense of runtime [default = no]
+	-d     : toggle treating the current AIG as a dual-output miter [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing very verbose information [default = no]
+	-h     : print the command usage
+
+usage: &isonpn [-vh]
+	         removes POs with functionally isomorphic combinational COI
+	         (currently ignores POs whose structural support is more than 16)
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &isost [-vh]
+	         removes POs with functionally isomorphic combinational COI
+	         (this command relies exclusively on structural hashing)
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &iwls21test [-vh] [-D file] <file1> <file2>
+	          this command evaluates AIG for 2021 IWLS ML+LS Contest
+	-v      : toggle printing verbose information [default = no]
+	-h      : print the command usage
+	-D file : file name to dump statistics [default = none]
+	file1   : file with input AIG (or "&read <file1.aig>; &iwls21test <file2>" can be used)
+	file2   : file with CIFAR10 image data (https://www.cs.toronto.edu/~kriz/cifar.html)
+
+usage: &jf [-KCDW num] [-akmdcgvwh]
+	           performs technology mapping of the network
+	-K num   : LUT size for the mapping (2 <= K <= 8) [default = 6]
+	-C num   : the max number of priority cuts (1 <= C <= 16) [default = 8]
+	-D num   : sets the delay constraint for the mapping [default = best possible]
+	-W num   : min frequency when printing functions with "-w" [default = 5]
+	-a       : toggles area-oriented mapping [default = yes]
+	-e       : toggles edge vs node minimization [default = yes]
+	-k       : toggles coarsening the subject graph [default = no]
+	-m       : toggles cut minimization [default = no]
+	-d       : toggles using DSD to represent cut functions [default = no]
+	-c       : toggles mapping for CNF generation [default = no]
+	-g       : toggles generating AIG without mapping [default = no]
+	-v       : toggles verbose output [default = no]
+	-w       : toggles very verbose output [default = no]
+	-h       : prints the command usage
+
+usage: &kf [-KCPDW num] [-akmdcgtsvwh]
+	           performs technology mapping of the network
+	-K num   : LUT size for the mapping (2 <= K <= 16) [default = 6]
+	-C num   : the max number of priority cuts (1 <= C <= 32) [default = 8]
+	-P num   : the number of cut computation processes (0 <= P <= 32) [default = 0]
+	-D num   : sets the delay constraint for the mapping [default = best possible]
+	-W num   : min frequency when printing functions with "-w" [default = 5]
+	-a       : toggles area-oriented mapping [default = no]
+	-e       : toggles edge vs node minimization [default = yes]
+	-k       : toggles coarsening the subject graph [default = no]
+	-m       : toggles cut minimization [default = no]
+	-d       : toggles using DSD to represent cut functions [default = no]
+	-c       : toggles mapping for CNF generation [default = no]
+	-g       : toggles generating AIG without mapping [default = no]
+	-t       : toggles cut computation using hash table [default = no]
+	-s       : toggles cut computation using a simple method [default = no]
+	-v       : toggles verbose output [default = no]
+	-w       : toggles very verbose output [default = no]
+	-h       : prints the command usage
+
+usage: &lcorr [-FCPX num] [-rcvwh]
+	         performs latch correpondence computation
+	-C num : the max number of conflicts at a node [default = 100]
+	-F num : the number of timeframes in inductive case [default = 1]
+	-P num : the number of timeframes in the prefix [default = 0]
+	-X num : the number of iterations of little or no improvement [default = 0]
+	-r     : toggle using implication rings during refinement [default = yes]
+	-c     : toggle using circuit-based SAT solver [default = yes]
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing verbose info about equivalent flops [default = no]
+	-h     : print the command usage
+
+usage: &lf [-KCFARLEDM num] [-kmupstgvwh]
+	           performs technology mapping of the network
+	-K num   : LUT size for the mapping (2 <= K <= 13) [default = 6]
+	-C num   : the max number of priority cuts (1 <= C <= 32) [default = 8]
+	-F num   : the number of area flow rounds [default = 4]
+	-A num   : the number of exact area rounds [default = 1]
+	-R num   : the delay relaxation ratio (num >= 0) [default = 0]
+	-L num   : the fanout limit for coarsening XOR/MUX (num >= 2) [default = 3]
+	-E num   : the area/edge tradeoff parameter (0 <= num <= 100) [default = 1]
+	-D num   : sets the delay constraint for the mapping [default = best possible]
+	-M num   : LUT size when cofactoring is performed (0 <= num <= 100) [default = 0]
+	-e       : toggles edge vs node minimization [default = yes]
+	-k       : toggles coarsening the subject graph [default = yes]
+	-m       : toggles cut minimization [default = no]
+	-u       : toggles using additional MUXes [default = no]
+	-p       : toggles power-aware cut selection heuristics [default = no]
+	-s       : toggles generating AIG without mapping [default = no]
+	-t       : toggles optimizing average rather than maximum level [default = no]
+	-g       : toggles using cut splitting [default = no]
+	-v       : toggles verbose output [default = no]
+	-w       : toggles very verbose output [default = no]
+	-h       : prints the command usage
+
+usage: &lneteval [-O num] [-vh] <file> <file2>
+	           performs testing of the AIG on the simulation data
+	-O num   : the output group size [default = -1]
+	-v       : toggles verbose output [default = no]
+	-h       : prints the command usage
+	<file>   : file name with simulation information
+	<file2>  : file name with simulation information
+
+usage: &lnetmap [-IO num] [-fxvh] <file>
+	           performs specialized LUT mapping
+	-I num   : the input support size [default = 6]
+	-O num   : the output group size [default = 2]
+	-f       : toggles using fixed primitives [default = no]
+	-x       : toggles using another computation [default = yes]
+	-v       : toggles verbose output [default = no]
+	-h       : prints the command usage
+	<file>   : file name with simulation information
+
+usage: &lnetopt [-IORX num] [-vh] <file>
+	           performs specialized AIG optimization
+	-I num   : the input support size [default = 6]
+	-O num   : the output group size [default = 2]
+	-R num   : patterns are cares starting this value [default = 0]
+	-X num   : the number of optimization rounds [default = 20]
+	-v       : toggles verbose output [default = no]
+	-h       : prints the command usage
+	<file>   : file name with simulation information
+
+usage: &lnetread [-vh] <file> <file2>
+	           reads and converts the network or the simulation data
+	-v       : toggles verbose output [default = no]
+	-h       : prints the command usage
+	<file>   : input file name with simulation information
+	<file2>  : output file name with simulation information
+
+usage: &lnetsim [-vh] <file> <file2>
+	           performs specialized AIG simulation
+	-v       : toggles verbose output [default = no]
+	-h       : prints the command usage
+	<file>   : input file name with simulation information
+	<file2>  : output file name with simulation information
+
+usage: &load [-h]
+	        loads AIG with mapping previously saved by &save
+	        (after loading the previously saved AIG can be loaded again)
+	-h    : print the command usage
+
+usage: &load2 [-h]
+	        loads AIG with mapping previously saved by &save2
+	        (after loading the previously saved AIG cannot be loaded again)
+	-h    : print the command usage
+
+usage: &loadaig [-h]
+	        loads AIG previously saved by &saveaig
+	-h    : print the command usage
+
+usage: &maxi [-FWT num] [-svh]
+	         experimental procedure
+	-F num : the number of timeframes [default = 5]
+	-W num : the number of machine words [default = 1000]
+	-T num : approximate global runtime limit in seconds [default = 0]
+	-s     : toggles using ternary simulation [default = no]
+	-v     : toggles printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &mesh [-XYT num] [-sh]
+	         creates a mesh architecture for the given AIG
+	-X num : horizontal size of the mesh (X >= 3) [default = 4]
+	-Y num : vertical size of the mesh (Y >= 3) [default = 4]
+	-T num : the latency of the mesh (T >= 2) [default = 3]
+	-s     : toggle using new SAT solver Satoko [default = yes]
+	-v     : toggle printing verbose information [default = yes]
+	-h     : print the command usage
+
+usage: &mf [-KCFARLED num] [-akmcgvwh]
+	           performs technology mapping of the network
+	-K num   : LUT size for the mapping (2 <= K <= 10) [default = 6]
+	-C num   : the max number of priority cuts (1 <= C <= 16) [default = 8]
+	-F num   : the number of area flow rounds [default = 2]
+	-A num   : the number of exact area rounds [default = 1]
+	-R num   : the delay relaxation ratio (num >= 0) [default = 0]
+	-L num   : the fanout limit for coarsening XOR/MUX (num >= 2) [default = 3]
+	-E num   : the area/edge tradeoff parameter (0 <= num <= 100) [default = 1]
+	-D num   : sets the delay constraint for the mapping [default = best possible]
+	-a       : toggles area-oriented mapping [default = no]
+	-e       : toggles edge vs node minimization [default = yes]
+	-k       : toggles coarsening the subject graph [default = yes]
+	-m       : toggles cut minimization [default = no]
+	-c       : toggles mapping for CNF generation [default = no]
+	-l       : toggles mapping for literals [default = no]
+	-g       : toggles generating AIG without mapping [default = no]
+	-v       : toggles verbose output [default = no]
+	-w       : toggles very verbose output [default = no]
+	-h       : prints the command usage
+
+usage: &mfs [-WFDMLCN <num>] [-daeblvwh]
+	           performs don't-care-based optimization of logic networks
+	-W <num> : the number of levels in the TFO cone (0 <= num) [default = 5]
+	-F <num> : the max number of fanouts to skip (1 <= num) [default = 30]
+	-D <num> : the max depth nodes to try (0 = no limit) [default = 100]
+	-M <num> : the max node count of windows to consider (0 = no limit) [default = 2000]
+	-L <num> : the max increase in node level after resynthesis (0 <= num) [default = 0]
+	-C <num> : the max number of conflicts in one SAT run (0 = no limit) [default = 5000]
+	-N <num> : the max number of nodes to try (0 = all) [default = 0]
+	-d       : toggle performing redundancy removal [default = no]
+	-a       : toggle minimizing area or area+edges [default = area+edges]
+	-e       : toggle high-effort resubstitution [default = no]
+	-b       : toggle preserving all white boxes [default = no]
+	-l       : toggle deriving don't-cares [default = no]
+	-v       : toggle printing optimization summary [default = no]
+	-w       : toggle printing detailed stats for each node [default = no]
+	-r       : toggle testing re-importing the network unchanged [default = no]
+	-h       : print the command usage
+
+usage: &mfsd [-KSNPWFMC <num>] [-mcdpvwh]
+	           performs SAT-based delay-oriented AIG optimization
+	-K <num> : the LUT size for delay minimization (2 <= num <= 6) [default = 4]
+	-S <num> : the LUT structure size (1 <= num <= 2) [default = 3]
+	-N <num> : the cut size considered for optimization (2 <= num <= 10) [default = 10]
+	-P <num> : the number of cuts computed at a node (1 <= num <= 500) [default = 128]
+	-W <num> : the number of levels in the TFO cone (0 <= num) [default = 5]
+	-F <num> : the max number of fanouts to skip (1 <= num) [default = 4]
+	-M <num> : the max node count of windows to consider (0 = no limit) [default = 2000]
+	-C <num> : the max number of conflicts in one SAT run (0 = no limit) [default = 0]
+	-m       : toggle generating delay-oriented mapping [default = yes]
+	-c       : toggle using several cuts at each node [default = no]
+	-d       : toggle additional search for good divisors [default = no]
+	-p       : toggle optimizing critical path only [default = no]
+	-v       : toggle printing optimization summary [default = no]
+	-w       : toggle printing detailed stats for each node [default = no]
+	-h       : print the command usage
+
+usage: &miter [-I num] [-dsptxyzcvh] <file>
+	         creates miter of two designs (current AIG vs. <file>)
+	-I num : the number of last PIs to replicate [default = 0]
+	-d     : toggle creating dual-output miter [default = no]
+	-s     : toggle creating sequential miter [default = no]
+	-p     : toggle creating pair-wise miter [default = no]
+	-t     : toggle XORing POs of dual-output miter [default = no]
+	-x     : toggle XORing POs of two-word miter [default = no]
+	-y     : toggle convering two-word miter into dual-output miter [default = no]
+	-z     : toggle ordering sides of the dual-output miter [default = no]
+	-c     : toggle duplicating AIG with the care set [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+	<file> : AIGER file with the design to miter
+
+usage: &miter2 [-vh] <file>
+	         creates miter of two copies of the design
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+	<file> : file name with flop initial values (0/1/x/X) [default = required]
+
+usage: &mlgen [-WS num] [-bvh] <file>
+	         generates data files for machine learning
+	-W num : the number of words to simulate [default = 10]
+	-S num : the random seed for simulation data (num < 10000) [default = 0]
+	-b     : toggle using binary data files [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+	<file> : file to store the simulation info
+
+usage: &mltest [-vh] [-D file] <file>
+	          testing command for machine learning data
+	-v      : toggle printing verbose information [default = no]
+	-h      : print the command usage
+	-D file : file name to dump statistics [default = none]
+	file    : file with input simulation info
+
+usage: &move_names [-vh]
+	         move CI/CO names
+	-v     : toggles additional verbose output [default = no]
+	-h     : print the command usage
+	<file> : the file name
+
+usage: &mprove [-TLMGH num] [-sdvwh]
+	         proves multi-output testcase by applying several engines
+	-T num : approximate global runtime limit in seconds [default = 30]
+	-L num : approximate local runtime limit in seconds [default = 2]
+	-M num : percentage of local runtime limit increase [default = 100]
+	-G num : approximate gap runtime limit in seconds [default = 0]
+	-H num : timeout per output in milliseconds [default = 0]
+	-s     : toggle using combinational synthesis [default = no]
+	-d     : toggle dumping invariant into a file [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing additional verbose information [default = no]
+	-h     : print the command usage
+
+usage: &mulfind [-C num] [-vh]
+	          detects multipliers in the given AIG
+	-C num  : the number of cuts to compute at each node [default = 8]
+	-v      : toggles printing verbose information [default = no]
+	-h      : print the command usage
+
+usage: &muxdec [-vh]
+	         performs restructuring
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: &muxpos [-vh]
+	         create additional POs to preserve MUXes
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: &muxstr [-vh]
+	         performs restructuring
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: &nf [-KCFARLEDQ num] [-akpqfvwh]
+	           performs technology mapping of the network
+	-K num   : LUT size for the mapping (2 <= K <= 6) [default = 6]
+	-C num   : the max number of priority cuts (1 <= C <= 32) [default = 16]
+	-F num   : the number of area flow rounds [default = 4]
+	-A num   : the number of exact area rounds (when '-a' is used) [default = 2]
+	-R num   : the delay relaxation ratio (num >= 0) [default = 0]
+	-L num   : the fanout limit for coarsening XOR/MUX (num >= 2) [default = 3]
+	-E num   : the area/edge tradeoff parameter (0 <= num <= 100) [default = 0]
+	-D num   : sets the delay constraint for the mapping [default = best possible]
+	-Q num   : internal parameter impacting area of the mapping [default = 0]
+	-a       : toggles SAT-based area-oriented mapping (experimental) [default = no]
+	-k       : toggles coarsening the subject graph [default = no]
+	-p       : toggles pin permutation (more matches - better quality) [default = no]
+	-q       : toggles quick mapping (fewer matches - worse quality) [default = no]
+	-f       : toggles filtering matches (useful with unit delay model) [default = no]
+	-v       : toggles verbose output [default = no]
+	-w       : toggles very verbose output [default = no]
+	-h       : prints the command usage
+
+usage: &odc [-N num] [-vh]
+	          generates the complement of the ODC for the node
+	-N num  : the node ID [default = undefined]
+	-v      : toggles printing verbose information [default = 1640429008]
+	-h      : print the command usage
+
+usage: &of [-KCFARLEDNMQ num] [-kmpgtvwh]
+	           performs technology mapping of the network
+	-K num   : LUT size for the mapping (2 <= K <= 6) [default = 4]
+	-C num   : the max number of priority cuts (1 <= C <= 32) [default = 16]
+	-F num   : the number of area flow rounds [default = 3]
+	-A num   : the number of exact area rounds [default = 4]
+	-R num   : the delay relaxation ratio (num >= 0) [default = 0]
+	-L num   : the fanout limit for coarsening XOR/MUX (num >= 2) [default = 3]
+	-E num   : the area/edge tradeoff parameter (0 <= num <= 100) [default = 10]
+	-D num   : sets the delay constraint for the mapping [default = best possible]
+	-N num   : delay of the first LUT [default = 10]
+	-M num   : delay of the second LUT [default = 2]
+	-Q num   : the number of fast non-routable edges [default = 0]
+	-e       : toggles edge vs node minimization [default = yes]
+	-k       : toggles coarsening the subject graph [default = no]
+	-m       : toggles cut minimization [default = no]
+	-p       : toggles power-aware cut selection heuristics [default = no]
+	-g       : toggles generating AIG without mapping [default = no]
+	-t       : toggles optimizing average rather than maximum level [default = no]
+	-v       : toggles verbose output [default = no]
+	-w       : toggles very verbose output [default = no]
+	-h       : prints the command usage
+
+usage: &pack [-NRD num] [-vh]
+	           performs packing for the LUT mapped network
+	-N num   : the number of LUTs in the block [default = 2]
+	-R num   : the routable delay of a LUT [default = 10]
+	-D num   : the direct (non-routable) delay of a LUT [default = 2]
+	-v       : toggles verbose output [default = no]
+	-h       : prints the command usage
+
+usage: &permute [-S num] [-vh]
+	         generates a random NPNP transformation of the combinational AIG
+	-S num : the seed used to randomize the process [default = 0]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &pfan [-N num] [-h]
+	         prints fanin/fanout statistics
+	-N num : the number of high-fanout nodes to explore [default = 0]
+	-h     : print the command usage
+
+usage: &pms [-h]
+	         prints miter status after SAT sweeping
+	-h     : print the command usage
+
+usage: &polyn [-N num] [-oasvwh] [-S str]
+	         derives algebraic polynomial from AIG
+	-N num : the number of additional primary outputs (-1 = unused) [default = 0]
+	-o     : toggles old computation [default = no]
+	-a     : toggles simple computation [default = yes]
+	-s     : toggles signed computation [default = no]
+	-v     : toggles printing verbose information [default = no]
+	-w     : toggles printing very verbose information [default = no]
+	-h     : print the command usage
+	
+	-S str : (optional) the output signature as a character string
+	         The format used to represent the output signature is very restrictive.
+	         It should be a string without spaces containing monomials in terms of
+	         inputs (i<num>) and outputs (o<num>) where <num> is 0-based. Coefficients
+	         are degrees of two, represented by log2 of their value: for example, 
+	         "2" is 2^2 = 4, "-4" is -2^4=-16, "-0" is -2^0=-1, etc
+	         Two types of signature are accepted:
+	         (1) a sequence of monomials without parentheses (for example, "-2*o0+1*o1+0*o2")
+	         (2) a product of two sequences followed by a sum with a sequence
+	             (for example, "(4*o0+2*o1+1*o2)*(4*i3+2*i4+1*i5)+(4*o3+2*o4+1*o5)")
+	         Here is the signature of a signed 2-bit multiplier: "(0*o0+1*o1+2*o2-3*o3)"
+
+usage: &popart [-S num] [-imvh]
+	         partitioning of POs into equivalence classes
+	-S num : random seed to select the set of pivot nodes [default = 0]
+	       : (if the seed is 0, the nodes with max fanout counts are used)
+	-i     : toggle allowing only CIs to be the pivots [default = no]
+	-m     : toggle using the largest part as the current network [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &posplit [-N num] [-vh]
+	         cofactors the property output w.r.t. a support subset
+	         (the OR of new PO functions is equal to the original property)
+	-N num : the number of random cofactoring variables [default = 5]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &poxsim [-F num] [-vh]
+	         X-valued simulation of the multi-output sequential miter
+	-F num : the number of timeframes [default = 1000]
+	-v     : toggles printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &print_truth [-OR num] [-vh]
+	         prints truth tables of outputs in hex notation
+	-O num : the index of first PO to print [default = 0]
+	-R num : (optional) the number of outputs to extract [default = all]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &prodadd [-ABSscvh]
+	          generates partial products and adder trees
+	-A num  : the bit-width of the first arg [default = 4]
+	-B num  : the bit-width of the second arg [default = 4]
+	-S num  : random seed used the node ordering [default = 0]
+	-s      : toggle using signed operation [default = no]
+	-c      : toggle using CLA in the adder tree [default = no]
+	-v      : toggle printing verbose information [default = no]
+	-h      : print the command usage
+
+usage: &profile [-N num] [-nmavh]
+	         profile gate structures appearing in the AIG
+	-N num : limit on class size to show [default = 0]
+	-n     : toggle profiling NPN-classes (for 3-LUT mapped AIGs) [default = no]
+	-m     : toggle profiling MUX structures [default = no]
+	-a     : toggle profiling adder structures [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: &ps [-tpcnlmaszxbh] [-D file]
+	          prints stats of the current AIG
+	-t      : toggle printing BMC tents [default = no]
+	-p      : toggle printing switching activity [default = no]
+	-c      : toggle printing the size of frontier cut [default = no]
+	-n      : toggle printing NPN classes of functions [default = no]
+	-l      : toggle printing LUT size profile [default = no]
+	-m      : toggle printing MUX/XOR statistics [default = no]
+	-a      : toggle printing miter statistics [default = no]
+	-s      : toggle printing slack distribution [default = no]
+	-z      : skip mapping statistics even if mapped [default = no]
+	-x      : toggle using no color in the printout [default = no]
+	-b      : toggle printing saved AIG statistics [default = no]
+	-D file : file name to dump statistics [default = none]
+	-h      : print the command usage
+
+usage: &psig [-rh]
+	         prints enable/set/reset statistics
+	-r     : toggle printing set/reset signals [default = yes]
+	-h     : print the command usage
+
+usage: &put [-seovh]
+	         transfer the current network into the old ABC
+	-s     : toggle clearning verification status [default = yes]
+	-e     : toggle extracting MUXes for flop enables [default = no]
+	-o     : toggles using buffers to decouple combinational outputs [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: &putontop [-vh] <file[1]> <file[2]> ...  <file[N]>
+	            generates an AIG by stacking several AIGs on top of each other
+	-v        : toggles printing verbose information [default = no]
+	-h        : print the command usage
+	<files>   : the AIGER files containing the input AIGs
+	            the outputs of each AIG are connected to the inputs of the one on top of it
+	            if there are more outputs than inputs, new POs will be created
+	            if there are more inputs than outputs, new PIs are created
+
+usage: &qbf [-PICTK num] [-degvh]
+	         solves QBF problem EpVxM(p,x)
+	-P num : number of parameters p (should be the first PIs) [default = -1]
+	-I num : quit after the given iteration even if unsolved [default = 0]
+	-C num : conflict limit per problem [default = 0]
+	-T num : global timeout [default = 0]
+	-K num : the number of input bits (for encoding miters only) [default = 0]
+	-d     : toggle dumping QDIMACS file instead of solving (complemented QBF) [default = no]
+	-e     : toggle dumping QDIMACS file instead of solving (original QBF) [default = no]
+	-g     : toggle using Glucose 3.0 by Gilles Audemard and Laurent Simon [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+	         As an example of using this command, consider specification (the three-input AND-gate) and implementation
+	         (the circuit with function AND(XOR(x0, x1), x2)).  The problem is to check whether the output of the XOR (node n)
+	         can be implemented differently, so that these two circuits are equivalent.  Obviously this can be done!
+	         Simply replace XOR gate by AND gate.
+
+	         > # file s2.blif
+	         > .model and3
+	         > .inputs x0 x1 x2 n
+	         > .outputs F
+	         > .names m x2 F
+	         > 11 1
+	         > .names x0 x1 m
+	         > 11 1
+	         > .end
+
+	         > # file i2.blif
+	         > .model impl
+	         > .inputs x0 x1 x2 n
+	         > .outputs F
+	         > .names n x2 F
+	         > 11 1
+	         > #.names x0 x1 n
+	         > #01 1
+	         > #10 1
+	         > .end
+
+	         > abc 08> miter -n i2.blif s2.blif; ps
+	         > impl_and3_miter               : i/o =    4/    1  lat =    0  and =      6  lev =  4
+	         > abc 09> &get; &qbf -P 3
+	         > The problem is UNSAT after 1 iterations.  Time =     0.00 sec
+
+	         UNSAT here means that the ECO solution with the given rectification point *has* a solution.
+
+	         For more info, refer to Figure 1 in the following paper A. Q. Dao, N.-Z. Lee, L.-C. Chen, M. P.-H. Lin,
+	         J.-H. R. Jiang, A. Mishchenko, and R. Brayton, "Efficient computation of ECO patch functions", Proc. DAC'18.
+	         https://people.eecs.berkeley.edu/~alanmi/publications/2018/dac18_eco.pdf
+
+usage: &qvar [-P num] [-uevh]
+	         derives cofactors w.r.t. the last NumPi-<num> variables
+	-P num : number of parameters p (should be the first PIs) [default = -1]
+	-u     : toggle ANDing cofactors (universal quantification) [default = no]
+	-e     : toggle ORing cofactors (existential quantification) [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: &r [-csxmnlvh] <file>
+	         reads the current AIG from the AIGER file
+	-c     : toggles reading simple AIG [default = no]
+	-s     : toggles structural hashing while reading [default = yes]
+	-x     : toggles detecting XORs while reading [default = no]
+	-m     : toggles reading MiniAIG rather than AIGER file [default = no]
+	-n     : toggles reading MiniAIG as a set of supergates [default = no]
+	-l     : toggles reading MiniLUT rather than AIGER file [default = no]
+	-v     : toggles additional verbose output [default = no]
+	-h     : print the command usage
+	<file> : the file name
+
+usage: &reachm [-TBFCHS num] [-L file] [-ripcsyzvwh]
+	         model checking via BDD-based reachability (dependence-matrix-based)
+	-T num : approximate time limit in seconds (0=infinite) [default = 0]
+	-B num : max number of nodes in the intermediate BDDs [default = 10000000]
+	-F num : max number of reachability iterations [default = 10000000]
+	-C num : max number of variables in a cluster [default = 20]
+	-H num : max number of hints to use [default = 0]
+	-S num : the number of the starting hint [default = 0]
+	-L file: the log file name [default = no logging]
+	-r     : enable dynamic BDD variable reordering [default = yes]
+	-i     : enable extraction of inductive constraints [default = no]
+	-p     : enable partitions for internal cut-points [default = no]
+	-c     : enable clustering of partitions [default = no]
+	-s     : enable scheduling of clusters [default = no]
+	-y     : skip checking property outputs [default = no]
+	-z     : skip reachability (run preparation phase only) [default = no]
+	-v     : prints verbose information [default = no]
+	-w     : prints dependency matrix [default = no]
+	-h     : print the command usage
+
+usage: &reachn [-BFT num] [-L file] [-ryzvh]
+	         model checking via BDD-based reachability (non-linear-QS-based)
+	-B num : the BDD node increase when hints kick in [default = 10000000]
+	-F num : max number of reachability iterations [default = 10000000]
+	-T num : approximate time limit in seconds (0=infinite) [default = 0]
+	-L file: the log file name [default = no logging]
+	-r     : enable additional BDD var reordering before image [default = yes]
+	-y     : skip checking property outputs [default = no]
+	-z     : skip reachability (run preparation phase only) [default = no]
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+
+usage: &reachp [-NFT num] [-L file] [-rbyzdvwh]
+	         model checking via BDD-based reachability (partitioning-based)
+	-N num : partitioning value (MinVol=nANDs/N/2; MaxVol=nANDs/N) [default = 5]
+	-F num : max number of reachability iterations [default = 10000000]
+	-T num : approximate time limit in seconds (0=infinite) [default = 0]
+	-L file: the log file name [default = no logging]
+	-r     : enable additional BDD var reordering before image [default = yes]
+	-b     : perform backward reachability analysis [default = no]
+	-y     : skip checking property outputs [default = no]
+	-z     : skip reachability (run preparation phase only) [default = no]
+	-d     : dump BDD of reached states into file "reached.blif" [default = no]
+	-v     : prints verbose information [default = no]
+	-w     : prints additional information [default = no]
+	-h     : print the command usage
+
+usage: &reachy [-BCFT num] [-L file] [-bcryzvh]
+	         model checking via BDD-based reachability (non-linear-QS-based)
+	-B num : the max BDD size to introduce cut points [default = 100]
+	-C num : the max BDD size to reparameterize/cluster [default = 500]
+	-F num : max number of reachability iterations [default = 10000000]
+	-T num : approximate time limit in seconds (0=infinite) [default = 0]
+	-L file: the log file name [default = no logging]
+	-b     : enable using backward enumeration [default = no]
+	-c     : enable reparametrization clustering [default = no]
+	-r     : enable additional BDD var reordering before image [default = no]
+	-y     : skip checking property outputs [default = no]
+	-z     : skip reachability (run preparation phase only) [default = no]
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+
+usage: &r [-csxmnlvh] <file>
+	         reads the current AIG from the AIGER file
+	-c     : toggles reading simple AIG [default = no]
+	-s     : toggles structural hashing while reading [default = yes]
+	-x     : toggles detecting XORs while reading [default = no]
+	-m     : toggles reading MiniAIG rather than AIGER file [default = no]
+	-n     : toggles reading MiniAIG as a set of supergates [default = no]
+	-l     : toggles reading MiniLUT rather than AIGER file [default = no]
+	-v     : toggles additional verbose output [default = no]
+	-h     : print the command usage
+	<file> : the file name
+
+usage: &read_blif [-vh] <file>
+	         a specialized reader for hierarchical BLIF files
+	         (for general-purpose BLIFs, please use "read_blif")
+	-v     : toggles additional verbose output [default = no]
+	-h     : print the command usage
+	<file> : the file name
+
+usage: &read_cblif [-M name] [-vh] <file>
+	         reads CBLIF file and collapse it into an AIG
+	-M name: module name to collapse [default = <root_module>]
+	-v     : toggles additional verbose output [default = no]
+	-h     : print the command usage
+	<file> : the file name
+
+usage: &read_stg [-K <num>] [-vh] <file>
+	         reads STG file and generates K-hot-encoded AIG
+	-K num : the K parameter for hotness of the encoding (1 <= K <= 5) [default = 1]
+	-v     : toggles printing state codes [default = no]
+	-h     : print the command usage
+	<file> : the file name
+
+usage: &read_ver [-vh] <file>
+	         a specialized reader for hierarchical Verilog files
+	-v     : toggles additional verbose output [default = no]
+	-h     : print the command usage
+	<file> : the file name
+
+usage: &reduce [-advh]
+	         reduces the circuit using equivalence classes
+	-a     : toggle merging all equivalences [default = no]
+	-d     : toggle using dual-output merging [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &reshape [-asvwh]
+	           performs AIG resubstitution
+	-a       : toggles selecting the algorithm [default = no]
+	-s       : toggles using simple method [default = no]
+	-v       : toggles printing verbose information [default = no]
+	-w       : toggles printing additional information [default = no]
+	-h       : print the command usage
+
+usage: &resim [-F num] [-mvh]
+	         resimulates equivalence classes using counter-example
+	-F num : the number of additinal frames to simulate [default = 100]
+	-m     : toggle miter vs. any circuit [default = circuit]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &resub [-NSD num] [-vwh]
+	           performs AIG resubstitution
+	-N num   : the limit on added nodes (num >= 0) [default = 0]
+	-S num   : the limit on support size (num > 0) [default = 0]
+	-D num   : the limit on divisor count (num > 0) [default = 0]
+	-v       : toggles printing verbose information [default = no]
+	-w       : toggles printing additional information [default = no]
+	-h       : print the command usage
+
+usage: &retime [-N <num>] [-vh]
+	         performs most-forward retiming
+	-N num : the number of incremental iterations [default = 100]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &reveng [-W num] [-vh] <file>
+	         compares two AIGs for structural similarity
+	         the current AIG is expected to contain some hierarchy
+	         the given AIG from <file> is expected to be flat
+	-W num : the number of 64-bit words of simulation info [default = 4]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &rex2gia [-avh] [string]
+	         converts a regular expression into a sequential AIG
+	-a     : toggle ordering input symbols alphabetically [default = yes]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+	string : representation of a regular expression
+	         Special symbols: parentheses '(' and ')', Kleene closure '*', union '|'
+	         All other characters are treated as symbols of the input alphabet.
+	         For example, ((A*B|AC)D) is defined over the alphabet {A, B, C, D}
+	         and generates the following language: {BD, ABD, AABD, AAABD, ..., ACD}
+	         A known limitation:  For the command to work correctly, each two-input union
+	         should have a dedicated pair of parentheses: ((A|B)|C) rather than (A|B|C)
+
+usage: &rexwalk [-SR] [-vh]
+	         performs simulation of an AIG representing a regular expression
+	-S num : the number of steps to take [default = 50]
+	-R num : the number of walks to make [default = 5]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: &rpm [-C num] [-navwh]
+	         performs structural reparametrization
+	-C num : max cut size for testing range equivalence [default = 16]
+	-n     : toggle using naive reparametrization [default = no]
+	-a     : toggle using old algorithm [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing more verbose information [default = no]
+	-h     : print the command usage
+
+usage: &sat [-JCRSN <num>] [-anmctxzvh]
+	         performs SAT solving for the combinational outputs
+	-J num : the SAT solver type [default = -1]
+	-C num : the max number of conflicts at a node [default = 100]
+	-R num : the max number of restarts at a node [default = 1]
+	-S num : the min number of variables to recycle the solver [default = 2000]
+	-N num : the min number of calls to recycle the solver [default = 200]
+	-a     : toggle solving all outputs and saving counter-examples [default = no]
+	-n     : toggle using non-chronological backtracking [default = yes]
+	-m     : toggle miter vs. any circuit [default = circuit]
+	-c     : toggle using circuit-based SAT solver [default = no]
+	-t     : toggle using learning in curcuit-based solver [default = no]
+	-x     : toggle using new solver [default = no]
+	-y     : toggle using new solver [default = no]
+	-z     : toggle replacing proved cones by const0 [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &satclp [-CL num] [-cvh]
+	         performs SAT based collapsing
+	-C num : the limit on the SOP size of one output [default = 1000]
+	-L num : the limit on the number of conflicts in one SAT call [default = 1000000]
+	-c     : toggles using canonical ISOP computation [default = no]
+	-v     : toggles printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &satenum [-CT <num>] [-vh]
+	         enumerates solutions of the combinational miter
+	-C num : the max number of conflicts at a node [default = 0]
+	-T num : global timeout [default = 0]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &satfx [-ID num] [-dvh]
+	         performs SAT based shared logic extraction
+	-I num : the number of iterations of divisor extraction [default = 5]
+	-D num : the number of divisors to extract in each iteration [default = 10]
+	-d     : toggles decomposing the first output [default = yes]
+	-v     : toggles printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &satlut [-NICDQ num] [-drwvh]
+	           performs SAT-based remapping of the LUT-mapped network
+	-N num   : the limit on AIG nodes in the window (num <= 128) [default = 32]
+	-I num   : the limit on the number of improved windows [default = 0]
+	-C num   : the limit on the number of conflicts [default = 100]
+	-D num   : the user-specified required times at the outputs [default = 0]
+	-Q num   : the maximum number of edges [default = 0]
+	-d       : toggles delay optimization [default = no]
+	-r       : toggles using reverse search [default = no]
+	-v       : toggles verbose output [default = no]
+	-h       : prints the command usage
+
+usage: &satsyn [-NOT <num>] [-afvh]
+	           performs synthesis
+	-N <num> : the number of window nodes [default = 0]
+	-O <num> : the number of window outputs [default = 0]
+	-T <num> : the timeout in seconds (0 = no timeout) [default = 0]
+	-a       : toggle using xor-nodes [default = no]
+	-f       : toggle using additional feature [default = no]
+	-v       : toggle printing optimization summary [default = no]
+	-h       : print the command usage
+
+usage: &sattest [-cvh]
+	         performs testing of dynamic CNF loading
+	-c     : toggle dynamic CNF loading [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &save [-ah]
+	        compares and possibly saves AIG with mapping
+	-a    : toggle using area as the primary metric [default = no]
+	-h    : print the command usage
+
+usage: &save2 [-ah]
+	        compares and possibly saves AIG with mapping
+	-a    : toggle using area as the primary metric [default = no]
+	-h    : print the command usage
+
+usage: &saveaig [-cah]
+	        saves the current AIG into the internal storage
+	-c    : toggle clearing the saved AIG [default = no]
+	-a    : toggle saving AIG with the smaller area [default = no]
+	-h    : print the command usage
+
+usage: &scl [-cevwh]
+	         performs structural sequential cleanup
+	-c     : toggle removing stuck-at constant registers [default = yes]
+	-e     : toggle removing equivalent-driver registers [default = yes]
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing verbose info about equivalent flops [default = no]
+	-h     : print the command usage
+
+usage: &scorr [-FCGXPSZ num] [-pkrecqowvh]
+	         performs signal correpondence computation
+	-C num : the max number of conflicts at a node [default = 100]
+	-F num : the number of timeframes in inductive case [default = 1]
+	-G num : the number of timeframes in the prefix [default = 0]
+	-X num : the number of iterations of little or no improvement [default = 0]
+	-P num : the number of concurrent processes [default = 1]
+	-S num : the number of flops in one partition [default = 0]
+	-Z num : the average flop include frequency [default = 0]
+	-p     : toggle using partitioning for the input AIG [default = no]
+	-k     : toggle using constant correspondence [default = no]
+	-r     : toggle using implication rings during refinement [default = yes]
+	-e     : toggle using equivalences as choices [default = no]
+	-c     : toggle using circuit-based SAT solver [default = yes]
+	-q     : toggle quitting when PO is not a constant candidate [default = no]
+	-o     : toggle calling old engine [default = no]
+	-w     : toggle printing verbose info about equivalent flops [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &semi [-WRFSMCT num] [-mdvh]
+	         performs semiformal refinement of equivalence classes
+	-W num : the number of words to simulate [default = 31]
+	-R num : the max number of rounds to simulate [default = 200]
+	-F num : the max number of frames to unroll [default = 200]
+	-S num : the max number of rounds w/o refinement to stop [default = 3]
+	-M num : the min number of outputs of bounded SRM [default = 0]
+	-C num : the max number of conflicts at a node [default = 100]
+	-T num : approximate runtime limit in seconds [default = 0]
+	-m     : toggle miter vs. any circuit [default = circuit]
+	-d     : toggle using two POs instead of XOR [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &setregnum [-N num] [-h]
+	         manually sets the number of registers to combine the last PI/PO pairs
+	-N num : set the number of registers to be the given number [default = 0]
+	-h     : print the command usage
+
+usage: &show [-afph]
+	        shows the current GIA using GSView
+	-a    : toggle visualazing adders [default = no]
+	-f    : toggle showing only full-adders with "-a" [default = no]
+	-p    : toggle showing the critical path of a LUT mapping [default = no]
+	-h    : print the command usage
+
+usage: &shrink [-N num] [-lvh]
+	         performs fast shrinking using current mapping
+	-N num : the max fanout count to skip a divisor [default = 50]
+	-l     : toggle level update during shrinking [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &sif [-K num] [-evh]
+	           performs technology mapping
+	-K num   : sets the LUT size for the mapping [default = 6]
+	-e       : toggles the evaluation mode [default = no]
+	-v       : toggles verbose output [default = no]
+	-h       : prints the command usage
+
+usage: &sim [-FWNT num] [-mvh] -I <file>
+	         performs random simulation of the sequential miter
+	         (if candidate equivalences are defined, performs refinement)
+	-F num : the number of frames to simulate [default = 32]
+	-W num : the number of words to simulate [default = 8]
+	-N num : random number seed (1 <= num <= 1000) [default = 0]
+	-T num : approximate runtime limit in seconds [default = 60]
+	-m     : toggle miter vs. any circuit [default = circuit]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+	-I file: (optional) file with input patterns (one line per frame, as many as PIs)
+
+usage: &sim2 [-WRNT num] [-vh] <file1.aig> <file2.aig>
+	         performs random of two circuits
+	-W num : the number of words to simulate [default = 16]
+	-R num : the number of simulation rounds [default = 10]
+	-N num : random number seed (1 <= num <= 1000) [default = 1]
+	-T num : approximate runtime limit in seconds [default = 0]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &sim3 [-FWBRNT num] [-gvh]
+	         performs random simulation of the sequential miter
+	-F num : the number of frames to simulate [default = 20]
+	-W num : the number of words to simulate [default = 50]
+	-B num : the number of flops in one bin [default = 8]
+	-R num : the number of simulation rounds [default = 0]
+	-S num : the number of rounds before a restart [default = 0]
+	-N num : random number seed (1 <= num <= 1000) [default = 0]
+	-T num : approximate runtime limit in seconds [default = 0]
+	-g     : toggle heuristic flop grouping [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &sim_gen [-WR num] [-sdvh]
+	         generates random simulation patterns
+	-W num : the number of 64-bit words of simulation info [default = 4]
+	-R num : the rarity parameter used to define scope [default = -1]
+	-s     : toggle using SAT-based improvement of available patterns [default = no]
+	-d     : toggle using one improvement of available patterns [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &sim_print [-vh]
+	         writes simulation patterns into a file
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &sim_read [-W num] [-trovh] <file>
+	         reads simulation patterns from file
+	-W num : the number of words to simulate [default = 4]
+	-t     : toggle creating exhaustive simulation info [default = no]
+	-r     : toggle reversing MSB and LSB input variables [default = no]
+	-o     : toggle reading output information [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+	<file> : file to store the simulation info
+
+usage: &sim_write [-otbvh] <file>
+	         writes simulation patterns into a file
+	-o     : toggle writing output information [default = no]
+	-t     : toggle transposing the simulation information [default = no]
+	-b     : toggle dumping in boolean vs hexadecimal notation [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+	<file> : file to store the simulation info
+
+usage: &simrsb [-N num] [-vh]
+	         performs resubstitution
+	-C num : the number of candidates to try [default = 32]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &slice [-S num] [-vh]
+	         cuts the lower part of the AIG with nodes using their support
+	-S num : the largest support size to keep in the slide [default = 6]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &sopb [-LWCR num] [-vh]
+	         performs SOP balancing
+	-L num : optimize paths above this level [default = 0]
+	-W num : optimize paths falling into this window [default = 0]
+	-C num : the number of cuts at a node [default = 8]
+	-R num : the delay relaxation ratio (num >= 0) [default = 0]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &speci [-FC num] [-fmvh]
+	         refines equivalence classes using speculative reduction
+	-F num : the max number of time frames [default = 100]
+	-C num : the max number of conflicts at a node [default = 25000]
+	-f     : toggle starting BMC from a later frame [default = yes]
+	-m     : toggle miter vs. any circuit [default = miter]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &speedup [-P num] [-N num] [-lvwh]
+	           transforms LUT-mapped network into an AIG with choices;
+	           the choices are added to speedup the next round of mapping
+	-P <num> : delay delta defining critical path for library model [default = 5%]
+	-N <num> : the max critical path degree for resynthesis (0 < num < 6) [default = 2]
+	-l       : toggle using unit- or LUT-library-delay model [default = unit]
+	-v       : toggle printing optimization summary [default = no]
+	-w       : toggle printing detailed stats for each node [default = no]
+	-h       : print the command usage
+
+usage: &splitprove [-PTIL num] [-svwh]
+	         proves CEC problem by case-splitting
+	-P num : the number of concurrent processes [default = 1]
+	-T num : runtime limit in seconds per subproblem [default = 10]
+	-I num : the max number of iterations (0 = infinity) [default = 0]
+	-L num : maximum look-ahead during cofactoring [default = 1]
+	-s     : enable silent computation (no reporting) [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing more verbose information [default = no]
+	-h     : print the command usage
+
+usage: &splitsat [-BENVTPIS num] [-pvh]
+	         solves CNF-based SAT problem by randomized case-splitting
+	-B num : the first CNF variable to use for splitting [default = 0]
+	-E num : the last CNF variable to use for splitting [default = 1000000000]
+	-N num : the number of CNF variables to use for splitting [default = 10]
+	-V num : the variable values to use (0, 1, or 2 for "any") [default = 2]
+	-T num : the runtime limit in seconds per subproblem [default = 5]
+	-P num : the number of concurrent processes [default = 1]
+	-I num : the max number of iterations (0 = infinity) [default = 1]
+	-S num : the random seed used to generate cofactors [default = 0]
+	-p     : toggle using SatELIte (http://minisat.se/SatELite.html) [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &sprove [-PTUW num] [-svwh]
+	         proves CEC problem by case-splitting
+	-P num : the number of concurrent processes [default = 5]
+	-T num : runtime limit in seconds per subproblem [default = 3]
+	-U num : runtime limit in seconds per subproblem [default = 10]
+	-W num : runtime limit in seconds per subproblem [default = 100]
+	-s     : enable silent computation (no reporting) [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing more verbose information [default = no]
+	-h     : print the command usage
+
+usage: &srm [-A file] [-drsfcvh]
+	          derives or writes speculatively reduced model into file "gsrm.aig"
+	-A file : file name for dumping speculative-reduced model [default = "gsrm.aig"]
+	-d      : toggle creating dual-output miter [default = no]
+	-r      : toggle writing reduced network for synthesis [default = no]
+	-s      : toggle using speculation at the internal nodes [default = yes]
+	-f      : toggle filtering to remove redundant equivalences [default = no]
+	-c      : toggle using combinational speculation [default = no]
+	-v      : toggle printing verbose information [default = no]
+	-h      : print the command usage
+
+usage: &srm2 [-abvh] <PartA_FileName> <PartB_FileName>
+	         writes speculatively reduced model into file "l,ˆÿ"
+	         only preserves equivalences across PartA and PartB
+	-a     : toggle using latches only in PartA [default = no]
+	-b     : toggle using latches only in PartB [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &st [-LM num] [-bacmrsh]
+	         performs structural hashing
+	-b     : toggle adding buffers at the inputs and outputs [default = no]
+	-a     : toggle additional hashing [default = no]
+	-c     : toggle collapsing hierarchical AIG [default = no]
+	-m     : toggle converting to larger gates [default = no]
+	-L num : create MUX when sum of refs does not exceed this limit [default = 2]
+	         (use L = 1 to create AIG with XORs but without MUXes)
+	-M num : create an AIG with additional primary inputs [default = 0]
+	-r     : toggle rehashing AIG while preserving mapping [default = no]
+	-s     : toggle using MUX restructuring [default = no]
+	-h     : print the command usage
+
+usage: &status [-h]
+	         prints status of the miter
+	-h     : print the command usage
+
+usage: &stochsyn [-NITSP <num>] [-tvh] <script>
+	           performs stochastic synthesis
+	-N <num> : the max partition size (in AIG nodes or LUTs) [default = 1000]
+	-I <num> : the number of iterations [default = 10]
+	-T <num> : the timeout in seconds (0 = no timeout) [default = 0]
+	-S <num> : user-specified random seed (0 <= num <= 100) [default = 0]
+	-P <num> : the number of concurrent processes (1 <= num <= 100) [default = 1]
+	-v       : toggle printing optimization summary [default = no]
+	-h       : print the command usage
+	<script> : synthesis script to use for each partition
+
+usage: &str_eco -I <biNum> [-vh] <impl> <patch>
+	         SAT-sweeping-based ECO
+	-v     : toggles printing verbose information [default = no]
+	-s     : toggles skipping structural hash [default = no]
+	-h     : print the command usage
+	<impl> : the implementation aig. (should be equivalent to spec)
+	<patch> : the modified spec. (should be a hierarchical AIG)
+
+usage: &struct [-vh]
+	           checks decomposition structures of the current mapping
+	-v       : toggle printing optimization summary [default = no]
+	-h       : print the command usage
+
+usage: &sweep [-WCS num] [-tvh]
+	         performs SAT sweeping for AIG with boxes
+	-W num : the max number of simulation words [default = 8]
+	-C num : the max number of conflicts at a node [default = 1000]
+	-S num : the max number of SAT variables [default = 5000]
+	-t     : toggle simulation of the TFO classes [default = yes]
+	-v     : toggle verbose printout [default = no]
+	-h     : print the command usage
+
+usage: &syn2 [-R num] [-akmdvh]
+	           performs AIG optimization
+	-R num   : the delay relaxation ratio (num >= 0) [default = 20]
+	-a       : toggles using the old algorithm [default = no]
+	-k       : toggles coarsening the subject graph [default = yes]
+	-m       : toggles cut minimization [default = no]
+	-d       : toggles additional delay optimization [default = no]
+	-v       : toggles printing verbose information [default = no]
+	-w       : toggles printing additional information [default = no]
+	-h       : print the command usage
+
+usage: &syn3 [-lvh]
+	         performs AIG optimization
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing additional information [default = no]
+	-h     : print the command usage
+
+usage: &syn4 [-lvh]
+	         performs AIG optimization
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing additional information [default = no]
+	-h     : print the command usage
+
+usage: &synch2 [-WCSKR num] [-frvh]
+	         computes structural choices using a new approach
+	-W num : the max number of simulation words [default = 8]
+	-C num : the max number of conflicts at a node [default = 100]
+	-S num : the max number of SAT variables [default = 5000]
+	-K num : the target LUT size for downstream mapping [default = 6]
+	-R num : the delay relaxation ratio (num >= 0) [default = 20]
+	-f     : toggle using lighter logic synthesis [default = no]
+	-r     : toggle skipping choices with redundant support [default = no]
+	-v     : toggle verbose printout [default = no]
+	-h     : print the command usage
+
+usage: &test [-FW num] [-svh]
+	        testing various procedures
+	-F num: the number of timeframes [default = 5]
+	-W num: the number of machine words [default = 1000]
+	-s    : toggle enable (yes) vs. disable (no) [default = no]
+	-v    : toggle printing verbose information [default = no]
+	-h    : print the command usage
+
+usage: &times [-N <num>] [-vh]
+	         creates several "parallel" copies of the design
+	-N num : number of copies to create [default = 2]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &topand [-vh]
+	        performs AND decomposition for combinational miter
+	-v    : toggle printing verbose information [default = yes]
+	-h    : print the command usage
+
+usage: &trace [-lvh]
+	           performs delay trace of LUT-mapped network
+	-l       : toggle using unit- or LUT-library-delay model [default = unit]
+	-v       : toggle printing optimization summary [default = no]
+	-h       : print the command usage
+
+usage: &transduction [-TSIPRV num] [-bmlh] <file>
+	           performs transduction-based AIG optimization
+	-T num   : transduction type [default = 1]
+	                0: remove simply redundant nodes
+	                1: Resub
+	                2: ResubMono
+	                3: ResubShared
+	                4: repeat Resub
+	                5: repeat ResubMono
+	                6: script RepeatInner
+	                7: script RepeatOuter
+	                8: script RepeatAll
+	-S num   : fanin sort type [default = 0]
+	                0: topological order
+	                1: number of ones
+	                2: number of ones before complemented edges
+	                3: pseudo random
+	                4: no sorting
+	-I num   : random seed to shuffle PIs (0 = no shuffle) [default = 0]
+	-P num   : parameters for scripts [default = 0]
+	-R num   : random seed to set all parameters (0 = no random) ([default = 0]
+	-V num   : verbosity level [default = 2]
+	-t       : toggles using truth table instead of BDD [default = no]
+	-m       : toggles using MSPF instead of CSPF [default = no]
+	-n       : toggles printing with a new line [default = no]
+	-l       : toggles level preserving optimization [default = no]
+	-h       : prints the command usage
+	<file>   : AIGER specifying external don't-cares
+	
+	           This command was contributed by Yukio Miyasaka.
+
+usage: &transtoch [-NMRPV num] [-mgrzftsonh] <file>
+	           iterates transduction with randomized parameters
+	-N num   : number of restarts [default = 0]
+	-M num   : number of hops (if; mfs2; strash) [default = 10]
+	-R num   : random seed [default = 0]
+	-P num   : number of threads [default = 1]
+	-V num   : verbosity level [default = 1]
+	-m       : toggles using MSPF instead of CSPF [default = yes]
+	-g       : toggles using ResubShared [default = yes]
+	-r       : toggles resetting hop count when new minimum is found [default = yes]
+	-z       : toggles using "drf -z" instead of "if;mfs2;st" for hop [default = no]
+	-f       : toggles using "drf -z" instead of "&dc2" for ite [default = no]
+	-t       : toggles using truth table instead of BDD [default = no]
+	-s       : toggles starting from the smallest starting point [default = no]
+	-o       : toggles starting from the given AIG [default = no]
+	-n       : toggles printing with a new line [default = no]
+	-h       : prints the command usage
+	<file>   : AIGER specifying external don't-cares
+	
+	           This command was contributed by Yukio Miyasaka.
+
+usage: &trim [-V num] [-iocpdh]
+	         removes PIs without fanout and PO driven by constants
+	-V num : the value (0 or 1) of POs to remove [default = both]
+	-i     : toggle removing PIs [default = yes]
+	-o     : toggle removing POs [default = yes]
+	-c     : toggle additionally removing POs fed by PIs [default = no]
+	-p     : toggle additionally removing duplicated POs [default = no]
+	-d     : toggle using dual-output miter [default = no]
+	-h     : print the command usage
+
+usage: &ttopt [-IORX num] [-vh] <file>
+	           performs specialized AIG optimization
+	-I num   : the input support size [default = 6]
+	-O num   : the output group size [default = 2]
+	-R num   : patterns are cares starting this value [default = 0]
+	-X num   : the number of optimization rounds [default = 20]
+	-v       : toggles verbose output [default = no]
+	-h       : prints the command usage
+	<file>   : file name with simulation information
+	
+	           This command was contributed by Yukio Miyasaka.
+	           The paper describing the method: Y. Miyasaka et al. "Synthesizing
+	           a class of practical Boolean functions using truth tables". Proc. IWLS 2022.
+	           https://people.eecs.berkeley.edu/~alanmi/publications/2022/iwls22_reo.pdf
+
+usage: &uif [-bvh]
+	         eagerly adds UIF constraints when hierarchy is present
+	-b     : toggle blackboxing while adding constraints [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &unate [-avh]
+	         prints info about unatements of CO funcs in terms of CI vars
+	-a     : toggle using efficient computation for all pairs [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: &undo [-h]
+	        reverses the previous AIG transformation
+	-h    : print the command usage
+
+usage: &unmap [-cvh]
+	           removes mapping from the current network
+	-c       : toggle converting cell mapping into LUT mapping [default = no]
+	-v       : toggle printing optimization summary [default = no]
+	-h       : print the command usage
+
+usage: &verify [-CT num] [-sdvh] <file>
+	         performs verification of combinational design
+	-C num : the max number of conflicts at a node [default = 1000]
+	-T num : approximate runtime limit in seconds [default = 0]
+	-s     : toggle using sequential verification [default = no]
+	-d     : toggle dumping AIGs to be compared [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+	<file> : optional file name with the spec [default = not used]
+
+usage: &w [-upqicabmlnsvh] <file>
+	         writes the current AIG into the AIGER file
+	-u     : toggle writing canonical AIG structure [default = no]
+	-p     : toggle writing Verilog with 'and' and 'not' [default = no]
+	-q     : toggle writing Verilog with NAND-gates [default = no]
+	-i     : toggle writing the interface module in Verilog [default = no]
+	-c     : toggle writing the interface module in Verilog [default = no]
+	-a     : toggle writing the interface module with assign-statements [default = no]
+	-b     : toggle writing additional buffers in Verilog [default = no]
+	-m     : toggle writing MiniAIG rather than AIGER [default = no]
+	-l     : toggle writing MiniLUT rather than AIGER [default = no]
+	-n     : toggle writing '\n' after 'c' in the AIGER file [default = no]
+	-s     : toggle skipping the timestamp in the output file [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+	<file> : the file name
+
+usage: &window [-vh] <node1> <node2> ... <nodeN>
+	          generates a logic window supported by the given nodes
+	-v      : toggles printing verbose information [default = no]
+	-h      : print the command usage
+	<nodes> : the list of window inputs
+
+usage: &wlut [-umvh] <file>
+	         writes the the current LUT mapping into a binary file
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+	<file> : the file name
+
+usage: &w [-upqicabmlnsvh] <file>
+	         writes the current AIG into the AIGER file
+	-u     : toggle writing canonical AIG structure [default = no]
+	-p     : toggle writing Verilog with 'and' and 'not' [default = no]
+	-q     : toggle writing Verilog with NAND-gates [default = no]
+	-i     : toggle writing the interface module in Verilog [default = no]
+	-c     : toggle writing the interface module in Verilog [default = no]
+	-a     : toggle writing the interface module with assign-statements [default = no]
+	-b     : toggle writing additional buffers in Verilog [default = no]
+	-m     : toggle writing MiniAIG rather than AIGER [default = no]
+	-l     : toggle writing MiniLUT rather than AIGER [default = no]
+	-n     : toggle writing '\n' after 'c' in the AIGER file [default = no]
+	-s     : toggle skipping the timestamp in the output file [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+	<file> : the file name
+
+usage: &write_ver [-S <file>] [-vh] <file>
+	          writes hierarchical Verilog after mapping
+	-S file : file name for the original hierarchical design (required)
+	-v      : toggle verbose output [default = no]
+	-h      : print the command usage
+	<file>  : the file name
+
+   ----------------------------------------------------------------------
+
+Abstraction commands:
+ &abs_create      &abs_derive      &abs_refine      &fla_gla        
+ &gla             &gla_derive      &gla_fla         &gla_refine     
+ &gla_shrink      &gla_vta         &vta             &vta_gla        
+
+usage: &abs_create [-vh] <comma-separated_list_of_zero-based_flop_ids>
+	        creates new flop map by reading user's input
+	-v    : toggle printing verbose information [default = no]
+	-h    : print the command usage
+
+usage: &abs_derive [-vh]
+	        derives abstracted model using the pre-computed flop map
+	-v    : toggle printing verbose information [default = no]
+	-h    : print the command usage
+
+usage: &abs_refine [-M <num>] [-tsvh]
+	         refines the pre-computed flop map using the counter-example
+	-M num : the max number of flops to add (0 = not used) [default = 0]
+	-t     : toggle trying four abstractions instead of one [default = yes]
+	-s     : toggle using the path sensitization algorithm [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &fla_gla [-vh]
+	          maps flop-level into gate-level abstraction
+	-v      : toggle printing verbose information [default = no]
+	-h      : print the command usage
+
+usage: &gla [-FSCMDETRQPB num] [-AL file] [-fardmnscbpquwvh]
+	          fixed-time-frame gate-level proof- and cex-based abstraction
+	-F num  : the max number of timeframes to unroll [default = 0]
+	-S num  : the starting time frame (0=unused) [default = 0]
+	-C num  : the max number of SAT solver conflicts (0=unused) [default = 0]
+	-M num  : the max number of learned clauses to keep (0=unused) [default = 1000]
+	-D num  : delta value for learned clause removal [default = 200]
+	-E num  : ratio percentage for learned clause removal [default = 70]
+	-T num  : an approximate timeout, in seconds [default = 0]
+	-R num  : stop when abstraction size exceeds num % (0<=num<=100) [default = 0]
+	-Q num  : stop when abstraction size exceeds num % during refinement (0<=num<=100) [default = 0]
+	-P num  : maximum percentage of added objects before a restart (0<=num<=100) [default = 30]
+	-B num  : the number of stable frames to call prover or dump abstraction [default = 2]
+	-A file : file name for dumping abstrated model (&gla -d) or abstraction map (&gla -m)
+	-L file : the log file name [default = no logging]
+	-f      : toggle propagating fanout implications [default = yes]
+	-a      : toggle refinement by adding one layers of gates [default = no]
+	-r      : toggle using improved refinement heuristics [default = no]
+	-d      : toggle dumping abstracted model into a file [default = no]
+	-m      : toggle dumping abstraction map into a file [default = no]
+	-n      : toggle using new algorithms [default = yes]
+	-s      : toggle skipping previously proved timeframes [default = no]
+	-c      : toggle using naive (2-input AND node) CNF encoding [default = no]
+	-b      : toggle CNF construction without hashing [default = no]
+	-p      : toggle using full-proof for UNSAT cores [default = no]
+	-q      : toggle calling the prover [default = no]
+	-u      : toggle enabling simplifation before calling the prover [default = no]
+	-v      : toggle printing verbose information [default = no]
+	-w      : toggle printing more verbose information [default = no]
+	-h      : print the command usage
+
+usage: &gla_derive [-vh]
+	        derives abstracted model using the pre-computed gate map
+	-v    : toggle printing verbose information [default = no]
+	-h    : print the command usage
+
+usage: &gla_fla [-vh]
+	          maps gate-level into flop-level abstraction
+	-v      : toggle printing verbose information [default = no]
+	-h      : print the command usage
+
+usage: &gla_refine [-FG num] [-vh]
+	         refines the pre-computed gate map using the counter-example
+	-F num : starting timeframe for suffix refinement [default = 0]
+	-G num : the number of additional timeframes to try [default = 0]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &gla_shrink [-FT num] [-psbvh]
+	         shrinks the abstraction by removing redundant objects
+	-F num : the maximum timeframe to check to [default = 0]
+	-T num : the timeout per call, in seconds [default = 0]
+	-p     : toggle using PDR for checking [default = no]
+	-s     : toggle using BMC for checking [default = yes]
+	-b     : toggle using BDDs for checking [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: &gla_vta [-F num] [-vh]
+	          maps fixed- into variable-time-frame gate-level abstraction
+	-F num  : timeframes in the resulting variable-time-frame abstraction [default = -1]
+	-v      : toggle printing verbose information [default = no]
+	-h      : print the command usage
+
+usage: &vta [-FSPCLDETR num] [-A file] [-tradvh]
+	          variable-time-frame gate-level proof- and cex-based abstraction
+	-F num  : the max number of timeframes to unroll [default = 0]
+	-S num  : the starting time frame (0=unused) [default = 0]
+	-P num  : the number of previous frames for UNSAT core [default = 4]
+	-C num  : the max number of SAT solver conflicts (0=unused) [default = 0]
+	-L num  : the max number of learned clauses to keep (0=unused) [default = 1000]
+	-D num  : delta value for learned clause removal [default = 200]
+	-E num  : ratio percentage for learned clause removal [default = 70]
+	-T num  : an approximate timeout, in seconds [default = 0]
+	-R num  : minimum percentage of abstracted objects (0<=num<=100) [default = 0]
+	-A file : file name for dumping abstrated model [default = "vabs.aig"]
+	-t      : toggle using terminal variables [default = no]
+	-r      : toggle using rollback after the starting frames [default = no]
+	-a      : toggle refinement by adding one layers of gates [default = no]
+	-d      : toggle dumping abstracted model into a file [default = no]
+	-v      : toggle printing verbose information [default = no]
+	-h      : print the command usage
+
+usage: &vta_gla [-vh]
+	        maps variable- into fixed-time-frame gate-level abstraction
+	-v    : toggle printing verbose information [default = no]
+	-h    : print the command usage
+
+   ----------------------------------------------------------------------
+
+Basic commands:
+ abcrc            alias            echo             empty           
+ help             history          quit             recall          
+ scrgen           set              sgen             sleep           
+ source           time             unalias          undo            
+ unset            version         
+
+usage: abcrc [-h]
+   -h  sources "abc.rc" from the current/parent/grandparent directory
+
+usage: alias [-h] [command [string]]
+   -h 		print the command usage
+
+usage: echo [-h] string 
+   -n 		suppress newline at the end
+   -h 		print the command usage
+
+usage: empty [-h]
+         removes all the currently stored networks
+   -h :  print the command usage
+
+usage: help [-a] [-d] [-h]
+       prints the list of available commands by group
+ -a       toggle printing hidden commands [default = no]
+ -d       print usage details to all commands [default = no]
+ -h       print the command usage
+
+usage: history [-h] <num>
+	        lists the last commands entered on the command line
+	-h    : print the command usage
+	<num> : the maximum number of entries to show [default = 20]
+
+usage: quit [-sh]
+   -h  print the command usage
+   -s  frees all the memory before quitting
+
+usage: recall -h <num>
+         set the current network to be one of the previous networks
+<num> :  level to return to [default = previous]
+   -h :  print the command usage
+
+usage: scrgen -F <str> -R <str> -C <str> -W <str> -E <str> -bh
+	          generates script for running ABC
+	-F str  : the name of the script file [default = "test.s"]
+	-R str  : the directory to read files from [default = current]
+	-C str  : the sequence of commands to run [default = "ps"]
+	-W str  : the directory to write the resulting files [default = no writing]
+	-E str  : the output files extension (with ".") [default = the same as input files]
+	-b      : toggles adding batch mode support [default = no]
+	-h      : print the command usage
+
+	Example : scrgen -F test1.s -R a/in -C "ps; st; ps" -W a/out -E .blif
+
+usage: set [-h] <name> <value>
+	        sets the value of parameter <name>
+	-h    : print the command usage
+
+usage: sgen [-N num] [-I num] [-vh]
+	         experiment with script generation
+	-N num : the number of commands to use [default = 10]
+	-I num : the number of iterations to perform [default = 10]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: sleep [-N <num>] [-h] <file_name>
+	              puts ABC to sleep for some time
+	-N num      : time duration in seconds [default = 1]
+	-h          : toggle printing the command usage
+	<file_name> : (optional) waiting begins after the file is created
+
+usage: source [-psxh] <file_name>
+	-p     supply prompt before reading each line [default = no]
+	-s     silently ignore nonexistent file [default = no]
+	-x     echo each line as it is executed [default = no]
+	-h     print the command usage
+
+usage: time [-ch]
+      		print the runtime since the last call
+   -c 		clears the elapsed time without printing it
+   -h 		print the command usage
+
+usage: unalias [-h] alias_names
+   -h 		print the command usage
+
+usage: undo
+         sets the current network to be the previously saved network
+
+usage: unset [-h] <name> 
+	        removes the value of parameter <name>
+	-h    : print the command usage
+
+usage: version [-h]
+         print the version string
+   -h :  print the command usage
+
+   ----------------------------------------------------------------------
+
+Choicing commands:
+ rec_add3         rec_dump3        rec_merge3       rec_ps3         
+ rec_start3       rec_stop3       
+
+usage: rec_add3 [-h]
+	        adds subgraphs from the current network to the set
+	-h    : print the command usage
+
+usage: rec_dump3 [-abh] <file>
+	-h     : print the command usage
+	-a     : toggles dumping TTs into an ASCII file [default = no]
+	-b     : toggles dumping TTs into a binary file [default = no]
+	<file> : AIGER file to write the library
+
+usage: rec_merge3 [-h] <file>
+	         merge libraries
+	-h     : print the command usage
+	<file> : AIGER file with the library
+
+usage: rec_ps3 [-h]
+	        prints statistics about the recorded AIG subgraphs
+	-h    : print the command usage
+
+usage: rec_start3 [-K num] [-C num] [-fvh] <file>
+	         starts recording AIG subgraphs (should be called for
+	         an empty network or after reading in a previous record)
+	-K num : the largest number of inputs [default = 6]
+	-C num : the max number of cuts used at a node (0 < num < 2^12) [default = 32]
+	-f     : toggles recording functions without AIG subgraphs [default = no]
+	-v     : toggles additional verbose output [default = no]
+	-h     : print the command usage
+	<file> : AIGER file with the library
+
+usage: rec_stop3 [-h]
+	        cleans the internal storage for AIG subgraphs
+	-h    : print the command usage
+
+   ----------------------------------------------------------------------
+
+DSD manager commands:
+ dsd_filter       dsd_free         dsd_load         dsd_match       
+ dsd_merge        dsd_ps           dsd_save        
+
+usage: dsd_filter [-LK num] [-omiutsvh]
+	         filtering structured and modifying parameters of DSD manager
+	-L num : remove structures with fewer occurrences that this [default = 0]
+	-K num : new LUT size to set for the DSD manager [default = -1]
+	-o     : toggles cleaning occurrence counters [default = no]
+	-m     : toggles cleaning matching marks [default = no]
+	-i     : toggles inverting matching marks [default = no]
+	-u     : toggles marking unate functions [default = no]
+	-t     : toggles marking threshold functions [default = no]
+	-s     : toggles marking threshold functions heuristically [default = no]
+	-v     : toggles verbose output [default = no]
+	-h     : print the command usage
+	        
+	         Option "dsd_filter -s" was contributed by Augusto Neutzling and Jody Matos from
+	         Federal University of Rio Grande do Sul, Brazil. The paper describing the method:
+	         A. Neutzling, J. M. Matos, A. Mishchenko, R. Ribas, and A. Reis,
+	         "Threshold logic synthesis based on cut pruning". Proc. ICCAD 2015.
+
+usage: dsd_free [-bh]
+	         deletes DSD manager
+	-b     : toggles processing second manager [default = no]
+	-h     : print the command usage
+
+usage: dsd_load [-bh] <file>
+	         loads DSD manager from file
+	-b     : toggles processing second manager [default = no]
+	-h     : print the command usage
+	<file> : file name to read
+
+usage: dsd_match [-KCPI num] [-fasvh] [-S str]
+	         matches DSD structures with the given cell
+	-K num : LUT size used for tuning [default = 0]
+	-C num : the maximum number of conflicts [default = 10000]
+	-P num : the maximum number of processes [default = 1]
+	-I num : skip checking if support is less than this [default = 0]
+	-f     : toggles using fast check [default = no]
+	-a     : toggles adding tuning to the current one [default = no]
+	-s     : toggles using specialized check [default = no]
+	-v     : toggles verbose output [default = no]
+	-S str : string representing programmable cell [default = not used]
+	-h     : print the command usage
+
+usage: dsd_merge [-h] <file>
+	         merges DSD manager from file with the current one
+	-h     : print the command usage
+	<file> : file name to read
+
+usage: dsd_ps [-NS num] [-obvh]
+	         prints statistics of the DSD manager
+	-N num : show structures whose ID divides by N [default = 0]
+	-S num : show structures whose support size is S [default = 0]
+	-o     : toggles printing occurrence distribution [default = no]
+	-t     : toggles dumping truth tables [default = no]
+	-b     : toggles processing second manager [default = no]
+	-v     : toggles verbose output [default = no]
+	-h     : print the command usage
+
+usage: dsd_save [-bh] <file>
+	         saves DSD manager into a file
+	-b     : toggles processing second manager [default = no]
+	-h     : print the command usage
+	<file> : (optional) file name to write
+
+   ----------------------------------------------------------------------
+
+Exact synthesis commands:
+ allexact         bms_ps           bms_start        bms_stop        
+ lutexact         majexact         majgen           testexact       
+ twoexact        
+
+usage: allexact [-MIKN <num>] [-ianevh] <hex>
+	           exact synthesis of I-input function using N K-input gates
+	-M <num> : the majority support size (overrides -I and -K) [default = 0]
+	-I <num> : the number of input variables [default = 0]
+	-K <num> : the number of node fanins [default = 2]
+	-N <num> : the number of K-input nodes [default = 0]
+	-i       : toggle using incremental solving [default = no]
+	-a       : toggle using only AND-gates when K = 2 [default = no]
+	-n       : toggle using node ordering by fanins [default = no]
+	-e       : toggle enumerating all solutions [default = no]
+	-v       : toggle verbose printout [default = yes]
+	-h       : print the command usage
+	<hex>    : truth table in hex notation
+
+usage: bms_ps [-h]
+	           shows statistics about BMS manager
+	-h       : print the command usage
+	
+	           This command was contributed by Mathias Soeken from EPFL in July 2016.
+	           The author can be contacted as mathias.soeken at epfl.ch
+
+usage: bms_start [-C <num>] [-avwh] [<file>]
+	           starts BMS manager for recording optimum networks
+	           if <file> is specified, store entries are read from that file
+	-C <num> : the limit on the number of conflicts [default = 100]
+	-a       : toggle create AIG [default = no]
+	-v       : toggle verbose printout [default = no]
+	-w       : toggle very verbose printout [default = no]
+	-h       : print the command usage
+	
+	           This command was contributed by Mathias Soeken from EPFL in July 2016.
+	           The author can be contacted as mathias.soeken at epfl.ch
+
+usage: bms_stop [-C <num>] [-vh] [<file>]
+	           stops BMS manager for recording optimum networks
+	           if <file> is specified, store entries are written to that file
+	-h       : print the command usage
+	
+	           This command was contributed by Mathias Soeken from EPFL in July 2016.
+	           The author can be contacted as mathias.soeken at epfl.ch
+
+usage: lutexact [-INKT <num>] [-iaogvh] <hex>
+	           exact synthesis of I-input function using N K-input gates
+	-I <num> : the number of input variables [default = 0]
+	-N <num> : the number of K-input nodes [default = 0]
+	-K <num> : the number of node fanins [default = 2]
+	-T <num> : the runtime limit in seconds [default = 0]
+	-i       : toggle using incremental solving [default = no]
+	-a       : toggle using only AND-gates when K = 2 [default = no]
+	-o       : toggle using additional optimizations [default = no]
+	-g       : toggle using Glucose 3.0 by Gilles Audemard and Laurent Simon [default = no]
+	-v       : toggle verbose printout [default = yes]
+	-h       : print the command usage
+	<hex>    : truth table in hex notation
+
+usage: majexact [-INR <num>] [-fcrgvh]
+	           exact synthesis of multi-input MAJ using MAJ3 gates
+	-I <num> : the number of input variables [default = 3]
+	-N <num> : the number of MAJ3 nodes [default = 1]
+	-R <num> : the number of additional connections [default = 0]
+	-f       : toggle using constant fanins [default = no]
+	-c       : toggle using cascade topology [default = no]
+	-r       : toggle using random topology [default = no]
+	-g       : toggle using Glucose 3.0 by Gilles Audemard and Laurent Simon [default = no]
+	-v       : toggle verbose printout [default = yes]
+	-h       : print the command usage
+
+usage: majgen [-N <num>] [-dvh]>
+	           generates networks for majority gates
+	-N <num> : the maximum number of variables [default = 8]
+	-d       : toggle dumping functions into a file [default = no]
+	-v       : toggle verbose printout [default = no]
+	-h       : print the command usage
+
+usage: testexact <file>
+	           tests solution of the exact synthesis problem
+	-v       : toggle verbose printout [default = no]
+	-h       : print the command usage
+	<file>   : file name in the specified format
+
+usage: twoexact [-INTG <num>] [-abdconugklvh] <hex>
+	           exact synthesis of multi-input function using two-input gates
+	-I <num> : the number of input variables [default = 0]
+	-N <num> : the number of two-input nodes [default = 0]
+	-T <num> : the runtime limit in seconds [default = 0]
+	-G <num> : the largest allowed gate size (NANDs only) [default = 0]
+	-a       : toggle using only AND-gates (without XOR-gates) [default = no]
+	-b       : toggle using only NAND-gates [default = no]
+	-d       : toggle using dynamic constraint addition [default = no]
+	-c       : toggle dumping CNF into a file [default = no]
+	-o       : toggle using additional optimizations [default = no]
+	-n       : toggle ordering internal nodes [default = no]
+	-u       : toggle using unique fanouts [default = no]
+	-g       : toggle using Glucose 3.0 by Gilles Audemard and Laurent Simon [default = no]
+	-k       : toggle using Kissat by Armin Biere [default = no]
+	-l       : toggle using Kissat by Armin Biere [default = no]
+	-v       : toggle verbose printout [default = yes]
+	-h       : print the command usage
+	<hex>    : truth table in hex notation
+	           
+	           For example, command line "twoexact -g -I 5 -N 12 169AE443"
+	           synthesizes the smallest circuit composed of two-input gates
+	           for the only NPN class of 5-input functions that requires 12 gates;
+	           all other functions can be realized with 11 two-input gates or less
+	           (see Section 7.1.2 "Boolean evaluation" in the book by Donald Knuth
+	           http://www.cs.utsa.edu/~wagner/knuth/fasc0c.pdf)
+
+   ----------------------------------------------------------------------
+
+FPGA mapping commands:
+ if               ifif             print_box        print_lut       
+ read_box         read_lut        
+
+usage: if [-KCFAGRNTXYUZ num] [-DEW float] [-SJ str] [-qarlepmsdbgxyuojiktnczvh]
+	           performs FPGA technology mapping of the network
+	-K num   : the number of LUT inputs (2 < num < 33) [default = library]
+	-C num   : the max number of priority cuts (0 < num < 2^12) [default = 8]
+	-F num   : the number of area flow recovery iterations (num >= 0) [default = 1]
+	-A num   : the number of exact area recovery iterations (num >= 0) [default = 2]
+	-G num   : the max AND/OR gate size for mapping (0 = unused) [default = 0]
+	-R num   : the delay relaxation ratio (num >= 0) [default = 0]
+	-N num   : the max size of non-decomposable nodes [default = unused]
+	-T num   : the type of LUT structures [default = any]
+	-X num   : delay of AND-gate in LUT library units [default = 0]
+	-Y num   : area of AND-gate in LUT library units [default = 0]
+	-U num   : the number of LUT inputs for delay-driven LUT decomposition [default = not used]
+	-Z num   : the number of LUT inputs for delay-driven LUT decomposition [default = not used]
+	-D float : sets the delay constraint for the mapping [default = best possible]
+	-E float : sets epsilon used for tie-breaking [default = 0.005000]
+	-W float : sets wire delay between adjects LUTs [default = 0.000000]
+	-S str   : string representing the LUT structure [default = not used]
+	-J str   : string representing the LUT structure (new method) [default = not used]
+	-q       : toggles preprocessing using several starting points [default = yes]
+	-a       : toggles area-oriented mapping [default = no]
+	-r       : enables expansion/reduction of the best cuts [default = yes]
+	-l       : optimizes latch paths for delay, other paths for area [default = no]
+	-e       : uses edge-based cut selection heuristics [default = yes]
+	-p       : uses power-aware cut selection heuristics [default = no]
+	-m       : enables cut minimization by removing vacuous variables [default = no]
+	-s       : toggles delay-oriented mapping used with -S <NN> [default = no]
+	-d       : toggles deriving local AIGs using bi-decomposition [default = no]
+	-b       : toggles the use of one special feature [default = no]
+	-g       : toggles delay optimization by SOP balancing [default = no]
+	-x       : toggles delay optimization by DSD balancing [default = no]
+	-y       : toggles delay optimization with recorded library [default = no]
+	-u       : toggles delay optimization with SAT-based library [default = no]
+	-o       : toggles using buffers to decouple combinational outputs [default = no]
+	-j       : toggles enabling additional check [default = no]
+	-i       : toggles using cofactoring variables [default = no]
+	-k       : toggles matching based on precomputed DSD manager [default = no]
+	-t       : toggles optimizing average rather than maximum level [default = no]
+	-n       : toggles computing DSDs of the cut functions [default = no]
+	-c       : toggles computing truth tables in a new way [default = no]
+	-z       : toggles deriving LUTs when mapping into LUT structures [default = no]
+	-v       : toggles verbose output [default = no]
+	-h       : prints the command usage
+
+usage: ifif [-DNcvwh]
+	           technology mapper into N-node K-LUT structures
+	           (takes a LUT network and maps it into a delay-optimal network
+	            of N-node K-LUT structures using the current LUT library)
+	-D float : wire delay (should be less than the LUT delay) [default = 0.50]
+	-N num   : degree of the LUT structure [default = 0]
+	-c       : toggles using LUT cascade vs LUT cluster [default = cluster]
+	-v       : toggles verbose output [default = no]
+	-w       : toggles very verbose output [default = no]
+	-h       : print the command usage
+
+
+usage: print_box [-vh]
+	          print the current box library
+	-v      : toggles enabling of verbose output [default = yes]
+	-h      : print the command usage
+
+
+usage: print_lut [-vh]
+	          print the current LUT library
+	-v      : toggles enabling of verbose output [default = yes]
+	-h      : print the command usage
+
+
+usage: read_box [-evh]
+	          read the box library from the file
+	-e      : toggles reading extended format [default = no]
+	-v      : toggles enabling of verbose output [default = yes]
+	-h      : print the command usage
+
+
+usage: read_lut [-vh]
+	          read the LUT library from the file
+	-v      : toggles enabling of verbose output [default = yes]
+	-h      : print the command usage
+	                                        
+	          File format for a LUT library:
+	          (the default library is shown)
+	                                        
+	          # The area/delay of k-variable LUTs:
+	          # k  area   delay
+	          1      1      1
+	          2      2      2
+	          3      4      3
+	          4      8      4
+	          5     16      5
+	          6     32      6
+
+   ----------------------------------------------------------------------
+
+Fraiging commands:
+ dress            dump_equiv       fraig            fraig_clean     
+ fraig_restore    fraig_store      fraig_sweep      fraig_trust     
+
+usage: dress [-C num] [-vh] <file>
+	         transfers internal node names from file to the current network
+	<file> : network with names (if not given, the current network spec is used)
+	-C num : the maximum number of conflicts at each node [default = 1000]
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+
+usage: dump_equiv [-C num] [-nvh] <file1.blif> <file2.blif> <file_dump_equiv.txt>
+	          computes equivalence classes of nodes in <file1> and <file2>
+	          By default this procedure performs matching of primary inputs by name.
+	          Those inputs that cannot be matched are treated as free variables.
+	          There is no effort to match primary outputs. Indeed, if two outputs
+	          are equivalent, they will belong to the same equivalence class in the end.
+	-C num  : the maximum number of conflicts at each node [default = 1000]
+	-n      : enable matching of primary inputs by name [default = yes]
+	-v      : prints verbose information [default = no]
+	-h      : print the command usage
+	<file1> : first network whose nodes are considered
+	<file2> : second network whose nodes are considered
+	<file_dump_equiv> : text file with node equivalence classes
+
+usage: fraig [-R num] [-D num] [-C num] [-rscpvtah]
+	         transforms a logic network into a functionally reduced AIG
+	         (known bugs: takes an UNSAT miter and returns a SAT one)
+	         (there are newer fraiging commands, "ifraig" and "dfraig")
+	-R num : number of random patterns (127 < num < 32769) [default = 2048]
+	-D num : number of systematic patterns (127 < num < 32769) [default = 2048]
+	-C num : number of backtracks for one SAT problem [default = 100]
+	-r     : toggle functional reduction [default = yes]
+	-s     : toggle considering sparse functions [default = yes]
+	-c     : toggle accumulation of choices [default = no]
+	-p     : toggle proving the miter outputs [default = no]
+	-v     : toggle verbose output [default = no]
+	-e     : toggle functional sweeping using EXDC [default = no]
+	-a     : toggle between all nodes and DFS nodes [default = dfs]
+	-t     : toggle using partitioned representation [default = no]
+	-h     : print the command usage
+
+usage: fraig_clean [-h]
+	        cleans the internal FRAIG storage
+	-h    : print the command usage
+
+usage: fraig_restore [-RDC num] [-h]
+	         makes the current network by fraiging the AIG database
+	-R num : number of random patterns (127 < num < 32769) [default = design-dependent]
+	-D num : number of systematic patterns (127 < num < 32769) [default = design-dependent]
+	-C num : number of backtracks for one SAT problem [default = 1000]
+	-h     : print the command usage
+
+usage: fraig_store [-h]
+	        saves the current network in the AIG database
+	-h    : print the command usage
+
+usage: fraig_sweep [-evwh]
+	        performs technology-dependent sweep
+	-e    : toggle functional sweeping using EXDC [default = no]
+	-v    : prints verbose information [default = no]
+	-w    : prints equivalence class information [default = no]
+	-h    : print the command usage
+
+usage: fraig_trust [-h]
+	        transforms the current network into an AIG assuming it is FRAIG with choices
+	-h    : print the command usage
+
+   ----------------------------------------------------------------------
+
+I/O commands:
+ &read_gig        &write_cnf       &write_resub     &write_truths   
+ read             read_aiger       read_baf         read_bblif      
+ read_bench       read_blif        read_blif_mv     read_cex        
+ read_cnf         read_dsd         read_eqn         read_fins       
+ read_formula     read_init        read_json        read_pla        
+ read_plamo       read_sf          read_status      read_truth      
+ read_verilog     write            write_aiger      write_aiger_cex 
+ write_baf        write_bblif      write_bench      write_blif      
+ write_blif_mv    write_book       write_cellnet    write_cex       
+ write_cnf        write_dot        write_edgelist   write_eqn       
+ write_gml        write_hie        write_json       write_pla       
+ write_smv        write_sorter_cnf write_status     write_truth     
+ write_verilog   
+
+usage: &read_gig [-h] <file>
+	         reads design in GIG format
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+usage: &write_cnf [-Kaiovh] <file>
+	           writes CNF produced by a new generator
+	-K <num> : the LUT size (3 <= num <= 8) [default = 8]
+	-a       : toggle using new algorithm [default = yes]
+	-i       : toggle using AIG object IDs as CNF variables [default = no]
+	-o       : toggle adding OR clause for the outputs [default = yes]
+	-v       : toggle printing verbose information [default = no]
+	-h       : print the help massage
+	file     : the name of the file to write
+
+	           CNF variable mapping rules:
+
+	           Assume CNF has N variables, with variable IDs running from 0 to N-1.
+	           Variable number 0 is not used in the CNF.
+	           Variables 1, 2, 3,... <nPOs> represent POs in their natural order.
+	           Variables N-<nPIs>, N-<nPIs>+1, N-<nPIs>+2, ... N-1, represent PIs in their natural order.
+	           The internal variables are ordered in a reverse topological order from outputs to inputs.
+	           That is, smaller variable IDs tend to be closer to the outputs, while larger
+	           variable IDs tend to be closer to the inputs. It was found that this ordering
+	           leads to faster SAT solving for hard UNSAT CEC problems.
+
+usage: &write_resub [-ch] <file>
+	         write the network in resub format
+	-h     : print the help message
+	file   : the name of the file to write (extension .json)
+
+usage: &write_truths [-rxbh] <file>
+	         writes truth tables of each PO of GIA manager into a file
+	-r     : toggle reversing bits in the truth table [default = no]
+	-x     : toggle writing in the hex notation [default = yes]
+	-b     : toggle using binary file format [default = no]
+	-h     : print the help massage
+	file   : the name of the file to write
+
+usage: read [-mcbgh] <file>
+	         replaces the current network by the network read from <file>
+	         by calling the parser that matches the extension of <file>
+	         (to read a hierarchical design, use "read_hie")
+	-m     : toggle reading mapped Verilog [default = no]
+	-c     : toggle network check after reading [default = yes]
+	-b     : toggle reading barrier buffers [default = no]
+	-g     : toggle reading and flattening into &-space [default = no]
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+usage: read_aiger [-ch] <file>
+	         reads the network in the AIGER format (http://fmv.jku.at/aiger)
+	-c     : toggle network check after reading [default = yes]
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+usage: read_baf [-ch] <file>
+	         reads the network in Binary Aig Format (BAF)
+	-c     : toggle network check after reading [default = yes]
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+usage: read_bblif [-ch] <file>
+	         reads the network in a binary BLIF format
+	-c     : toggle network check after reading [default = yes]
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+usage: read_bench [-ch] <file>
+	         reads the network in BENCH format
+	-c     : toggle network check after reading [default = yes]
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+usage: read_blif [-nmach] <file>
+	         reads the network in binary BLIF format
+	         (if this command does not work, try "read")
+	-n     : toggle using old BLIF parser without hierarchy support [default = no]
+	-m     : toggle saving original circuit names into a file [default = no]
+	-a     : toggle creating AIG while reading the file [default = no]
+	-c     : toggle network check after reading [default = yes]
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+usage: read_blif_mv [-ch] <file>
+	         reads the network in BLIF-MV format
+	         (if this command does not work, try "read")
+	-c     : toggle network check after reading [default = yes]
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+usage: read_cex [-ch] <file>
+	         reads the witness cex
+	-c     : toggle check after reading [default = yes]
+	-x     : read x bits for verification [default = no]
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+usage: read_cnf [-mh] <file>
+	         creates network with one node
+	-m     : toggles generating multi-output network [default = no]
+	-h     : prints the command summary
+	file   : file name with the truth table
+
+usage: read_dsd [-h] <formula>
+	          parses a formula representing DSD of a function
+	-h      : prints the command summary
+	formula : the formula representing disjoint-support decomposition (DSD)
+	          Example of a formula: !(a*(b+CA(!d,e*f,c))*79B3(g,h,i,k))
+	          where '!' is an INV, '*' is an AND, '+' is an XOR, 
+	          CA and 79B3 are hexadecimal representations of truth tables
+	          (in this case CA=11001010 is truth table of MUX(Data0,Data1,Ctrl))
+	          The lower chars (a,b,c,etc) are reserved for elementary variables.
+	          The upper chars (A,B,C,etc) are reserved for hexadecimal digits.
+	          No spaces are allowed in formulas. In parentheses, LSB goes first.
+
+usage: read_eqn [-ch] <file>
+	         reads the network in equation format
+	-c     : toggle network check after reading [default = yes]
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+usage: read_fins [-vh] <file>
+	         reads the network in equation format
+	-v     : enable verbose output [default = no].
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+usage: read_dsd [-h] <formula>
+	          parses a formula representing DSD of a function
+	-h      : prints the command summary
+	formula : the formula representing disjoint-support decomposition (DSD)
+	          Example of a formula: !(a*(b+CA(!d,e*f,c))*79B3(g,h,i,k))
+	          where '!' is an INV, '*' is an AND, '+' is an XOR, 
+	          CA and 79B3 are hexadecimal representations of truth tables
+	          (in this case CA=11001010 is truth table of MUX(Data0,Data1,Ctrl))
+	          The lower chars (a,b,c,etc) are reserved for elementary variables.
+	          The upper chars (A,B,C,etc) are reserved for hexadecimal digits.
+	          No spaces are allowed in formulas. In parentheses, LSB goes first.
+
+usage: read_init [-h] <file>
+	         reads initial state of the network in BENCH format
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+usage: read_json [-h] <file>
+	         reads file in JSON format
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+usage: read_pla [-zbdxch] <file>
+	         reads the network in PLA
+	-z     : toggle reading on-set and off-set [default = on-set]
+	-b     : toggle reading both on-set and off-set as on-set [default = on-set]
+	-d     : toggle reading both on-set and dc-set as on-set [default = on-set]
+	-x     : toggle reading Exclusive SOP rather than SOP [default = no]
+	-c     : toggle network check after reading [default = yes]
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+	         Please note that the PLA parser is somewhat slow for large SOPs.
+	         On the other hand, BLIF parser reads a 3M SOP and converts it into a 7.5K AIG in 1 sec:
+	         abc 16> read test.blif; ps; bdd -s; ps; muxes; strash; ps
+	         test                      : i/o =   25/    1  lat =    0  nd =     1  edge =     25  cube = 2910537  lev = 1
+	         test                      : i/o =   25/    1  lat =    0  nd =     1  edge =     25  bdd  =    2937  lev = 1
+	         test                      : i/o =   25/    1  lat =    0  and =     7514  lev = 48
+	         abc 19> time
+	         elapse: 1.05 seconds, total: 1.05 seconds
+
+usage: read_plamo [-mvh] <file>
+	         reads the network in multi-output PLA
+	-m     : toggle dist-1 merge for cubes with identical outputs [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+usage: read_sf [-h] <file>
+	         reads file in SF format
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+usage: read_status [-ch] <file>
+	         reads verification log file
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+usage: read_truth [-xfh] <truth> <file>
+	         creates network with node(s) having given truth table(s)
+	-x     : toggles between bin and hex notation [default = hex]
+	-f     : toggles reading truth table(s) from file [default = no]
+	-h     : prints the command summary
+	truth  : truth table with most significant bit first (e.g. 1000 for AND(a,b))
+	file   : file name with the truth table
+
+usage: read_verilog [-mcbh] <file>
+	         reads the network in Verilog (IWLS 2002/2005 subset)
+	-m     : toggle reading mapped Verilog [default = no]
+	-c     : toggle network check after reading [default = yes]
+	-b     : toggle reading barrier buffers [default = no]
+	-h     : prints the command summary
+	file   : the name of a file to read
+
+usage: write [-h] <file>
+	         writes the current network into <file> by calling
+	         the writer that matches the extension of <file>
+	-h     : print the help massage
+	file   : the name of the file to write
+
+usage: write_aiger [-scuvh] <file>
+	         writes the network in the AIGER format (http://fmv.jku.at/aiger)
+	-s     : toggle saving I/O names [default = no]
+	-c     : toggle writing more compactly [default = no]
+	-u     : toggle writing canonical AIG structure [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the help massage
+	file   : the name of the file to write (extension .aig)
+
+usage: write_aiger_cex [-h] <file>
+	         writes the current CEX in the AIGER format (http://fmv.jku.at/aiger)
+	-h     : print the help massage
+	file   : the name of the file to write
+
+usage: write_baf [-h] <file>
+	         writes the network into a BLIF file
+	-h     : print the help massage
+	file   : the name of the file to write (extension .baf)
+
+usage: write_bblif [-h] <file>
+	         writes the network into a binary BLIF file
+	-h     : print the help massage
+	file   : the name of the file to write (extension .bblif)
+
+usage: write_bench [-lh] <file>
+	         writes the network in BENCH format
+	-l     : toggle using LUTs in the output [default = yes]
+	-h     : print the help massage
+	file   : the name of the file to write (extension .bench)
+
+usage: write_blif [-S str] [-jah] <file>
+	         writes the network into a BLIF file
+	-S str : string representing the LUT structure [default = not used]
+	-j     : enables special BLIF writing [default = no]
+	-a     : enables hierarchical BLIF writing for LUT structures [default = no]
+	-h     : print the help massage
+	file   : the name of the file to write (extension .blif)
+
+usage: write_blif_mv [-h] <file>
+	         writes the network into a BLIF-MV file
+	-h     : print the help massage
+	file   : the name of the file to write (extension .mv)
+
+usage: write_book [-h] <file> [-options]
+	-h     : prints the help massage
+	file   : the name of the file to write (extension .aux, .nodes, .nets)
+	
+	This command is developed by Myungchul Kim (University of Michigan).
+
+usage: write_cellnet [-h] <file>
+	         writes the network is the cellnet format
+	-h     : print the help massage
+	file   : the name of the file to write
+
+usage: write_cex [-snmueocfzvh] <file>
+	         saves counter-example (CEX) derived by "sat", "iprove", "dprove", etc
+	         the output file <file> contains values for each PI in natural order
+	-s     : always report a sequential CEX (cycle 0 for comb) [default = no]
+	-n     : write input names into the file [default = no]
+	-m     : minimize CEX by dropping don't-care values [default = no]
+	-u     : use fast SAT-based CEX minimization [default = no]
+	-e     : use high-effort SAT-based CEX minimization [default = no]
+	-o     : use old CEX minimization algorithm [default = no]
+	-x     : minimize using algorithm from cexinfo command [default = no]
+	-c     : check generated CEX using ternary simulation [default = no]
+	-a     : print cex in AIGER 1.9 format [default = no]
+	-t     : extended header info when cex in AIGER 1.9 format [default = no]
+	-f     : enable printing flop values in each timeframe [default = no]
+	-z     : toggle using saved flop names [default = no]
+	-v     : enable verbose output [default = no]
+	-h     : print the help massage
+	<file> : the name of the file to write
+
+usage: write_cnf [-nfpcvh] <file>
+	         generates CNF for the miter (see also "&write_cnf")
+	-n     : toggle using new algorithm [default = yes]
+	-f     : toggle using fast algorithm [default = no]
+	-p     : toggle using all primes to enhance implicativity [default = no]
+	-c     : toggle adjasting polarity of internal variables [default = yes]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the help massage
+	file   : the name of the file to write
+
+usage: write_dot [-h] <file>
+	         writes the current network into a DOT file
+	-h     : print the help massage
+	file   : the name of the file to write
+
+usage: write_edgelist [-N] <file>
+	         writes the network into edgelist file
+	         part of Verilog-2-PyG (PyTorch Geometric). more details https://github.com/ycunxi/Verilog-to-PyG 
+	-N     : toggle keeping original naming of the netlist in edgelist (default=False)
+	-h     : print the help massage
+	file   : the name of the file to write (extension .el)
+
+usage: write_eqn [-h] <file>
+	         writes the current network in the equation format
+	-h     : print the help massage
+	file   : the name of the file to write
+
+usage: write_gml [-h] <file>
+	         writes network using graph representation formal GML
+	-h     : print the help massage
+	file   : the name of the file to write
+
+usage: write_hie [-h] <orig> <file>
+	         writes the current network into <file> by calling
+	         the hierarchical writer that matches the extension of <file>
+	-m     : toggle reading mapped Verilog for <orig> [default = no]
+	-h     : print the help massage
+	orig   : the name of the original file with the hierarchical design
+	file   : the name of the file to write
+
+usage: write_json [-ch] <file>
+	         write the network in JSON format
+	-c     : output extracted version
+	-h     : print the help message
+	file   : the name of the file to write (extension .json)
+
+usage: write_pla [-M <num>] [-mh] <file>
+	           writes the collapsed network into a PLA file
+	-M <num> : the number of on-set minterms to write [default = 0]
+	-m       : toggle writing multi-output PLA [default = no]
+	-h       : print the help massage
+	file     : the name of the file to write
+
+usage: write_smv [-h] <file>
+	         write the network in SMV format
+	-h     : print the help message
+	file   : the name of the file to write (extension .smv)
+
+usage: write_sorter_cnf [-N <num>] [-Q <num>] <file>
+	         writes CNF for the sorter
+	-N num : the number of sorter bits [default = 16]
+	-Q num : the number of bits to be asserted to 1 [default = 4]
+	-h     : print the help massage
+	file   : the name of the file to write
+
+usage: write_status [-h] <file>
+	         writes verification log file
+	-h     : print the help massage
+	file   : the name of the file to write
+
+usage: write_truth [-xrh] <file>
+	         writes truth table into a file
+	-x     : toggles between bin and hex representation [default = hex]
+	-r     : toggle reversing bits in the truth table [default = no]
+	-h     : print the help massage
+	file   : the name of the file to write
+
+usage: write_verilog [-K num] [-famh] <file>
+	         writes the current network in Verilog format
+	-K num : write the network using instances of K-LUTs (2 <= K <= 6) [default = not used]
+	-f     : toggle using fixed format [default = no]
+	-a     : toggle writing expressions with only ANDs (without XORs and MUXes) [default = no]
+	-m     : toggle writing additional modules [default = yes]
+	-h     : print the help massage
+	file   : the name of the file to write
+
+   ----------------------------------------------------------------------
+
+Liveness commands:
+ kcs              l2s              l2ssim           l3s             
+ nck             
+
+usage: kcs [-cmgCh]
+	implements Claessen-Sorensson's k-Liveness algorithm
+	-c : verification with constraints, looks for POs prefixed with csSafetyInvar_
+	-m : discovers monotone signals
+	-g : verification with user-supplied barriers, looks for POs prefixed with csLevel1Stabil_
+	-C : verification with discovered monotone signals
+	-h : print usage
+
+usage: l2s [-1lsh]
+	         performs Armin Biere's live-to-safe transformation
+	-1 : no shadow logic, presume all loops are self loops
+	-l : ignore liveness and fairness outputs
+	-s : ignore safety assertions and assumptions
+	-h : print command usage
+
+Empty network.
+
+usage: l3s [-1lsh]
+	         performs Armin Biere's live-to-safe transformation
+	-1 : no shadow logic, presume all loops are self loops
+	-l : ignore liveness and fairness outputs
+	-s : ignore safety assertions and assumptions
+	-h : print command usage
+
+usage: nck [-cmgCh]
+	generates combinatorial signals for stabilization
+	-h : print usage
+
+   ----------------------------------------------------------------------
+
+LogiCS commands:
+ testrpo         
+
+usage: testrpo [-NT <num>] [-vh] <file>
+	           RPO algorithm developed and implemented by Mayler G. A. Martins,
+	           Vinicius Callegaro, Renato P. Ribas and Andre' I. Reis
+	           at Federal University of Rio Grande do Sul, Porto Alegre, Brazil
+	-N <num> : the number of support variables (binary files only) [default = unused]
+	-T <num> : the number of recursions accepted before abort [default = INFINITE]
+	-v       : toggle verbose printout [default = no]
+	-h       : print the command usage
+	<file>   : a text file with truth tables in hexadecimal, listed one per line,
+	           or a binary file with an array of truth tables (in this case,
+	           -N <num> is required to determine how many functions are stored)
+
+   ----------------------------------------------------------------------
+
+New AIG commands:
+ csweep           dc2              dch              dchoice         
+ dfraig           drf              drw              drwsat          
+ icut             ifraig           iresyn           irw             
+ irws             isat             istrash          qbf             
+
+usage: csweep [-C num] [-K num] [-vh]
+	         performs cut sweeping using a new method
+	-C num : limit on the number of cuts (C >= 2) [default = 8]
+	-K num : limit on the cut size (3 <= K <= 16) [default = 6]
+	-v     : toggle verbose printout [default = no]
+	-h     : print the command usage
+
+usage: dc2 [-blfpvh]
+	         performs combinational AIG optimization
+	-b     : toggle internal balancing [default = no]
+	-l     : toggle updating level [default = no]
+	-f     : toggle representing fanouts [default = yes]
+	-p     : toggle power-aware rewriting [default = no]
+	-v     : toggle verbose printout [default = no]
+	-h     : print the command usage
+
+usage: dch [-WCS num] [-sptgcfrxvh]
+	         computes structural choices using a new approach
+	-W num : the max number of simulation words [default = 8]
+	-C num : the max number of conflicts at a node [default = 1000]
+	-S num : the max number of SAT variables [default = 5000]
+	-s     : toggle synthesizing three snapshots [default = yes]
+	-p     : toggle power-aware rewriting [default = no]
+	-t     : toggle simulation of the TFO classes [default = yes]
+	-g     : toggle using GIA to prove equivalences [default = no]
+	-c     : toggle using circuit-based SAT vs. MiniSat [default = no]
+	-f     : toggle using faster logic synthesis [default = no]
+	-r     : toggle skipping choices with redundant support [default = no]
+	-x     : toggle using new choice computation [default = no]
+	-v     : toggle verbose printout [default = no]
+	-h     : print the command usage
+
+usage: dchoice [-C num] [-L num] [-blcvh]
+	         performs partitioned choicing using new AIG package
+	-C num : the max number of conflicts at a node [default = 1000]
+	-L num : the max level of nodes to consider (0 = not used) [default = 0]
+	-b     : toggle internal balancing [default = yes]
+	-l     : toggle updating level [default = yes]
+	-c     : toggle constructive computation of choices [default = no]
+	-v     : toggle verbose printout [default = no]
+	-h     : print the command usage
+
+usage: dfraig [-C num] [-sprcvh]
+	         performs fraiging using a new method
+	-C num : limit on the number of conflicts [default = 100]
+	-s     : toggle considering sparse functions [default = yes]
+	-p     : toggle proving the miter outputs [default = no]
+	-r     : toggle speculative reduction [default = no]
+	-c     : toggle accumulation of choices [default = no]
+	-v     : toggle verbose printout [default = no]
+	-h     : print the command usage
+
+usage: drf [-M num] [-K num] [-C num] [-elzvwh]
+	         performs combinational AIG refactoring
+	-M num : the min MFFC size to attempt refactoring [default = 2]
+	-K num : the max number of cuts leaves [default = 12]
+	-C num : the max number of cuts to try at a node [default = 5]
+	-e     : toggle extending tbe cut below MFFC [default = no]
+	-l     : toggle preserving the number of levels [default = no]
+	-z     : toggle using zero-cost replacements [default = no]
+	-v     : toggle verbose printout [default = no]
+	-w     : toggle very verbose printout [default = no]
+	-h     : print the command usage
+
+usage: drw [-C num] [-NM num] [-lfzrvwh]
+	         performs combinational AIG rewriting
+	-C num : the max number of cuts at a node [default = 8]
+	-N num : the max number of subgraphs tried [default = 5]
+	-M num : the min number of nodes saved after one step (0 <= num) [default = 1]
+	-l     : toggle preserving the number of levels [default = no]
+	-f     : toggle representing fanouts [default = yes]
+	-z     : toggle using zero-cost replacements [default = no]
+	-r     : toggle using cut recycling [default = yes]
+	-v     : toggle verbose printout [default = no]
+	-w     : toggle very verbose printout [default = no]
+	-h     : print the command usage
+
+usage: drwsat [-bvh]
+	         performs combinational AIG optimization for SAT
+	-b     : toggle internal balancing [default = no]
+	-v     : toggle verbose printout [default = no]
+	-h     : print the command usage
+
+usage: icut [-K num] [-h]
+	         computes sequential cuts of the given size
+	-K num : the number of cut inputs (2 <= num <= 6) [default = 5]
+	-h     : print the command usage
+
+usage: ifraig [-P num] [-C num] [-L num] [-spvh]
+	         performs fraiging using a new method
+	-P num : partition size (0 = partitioning is not used) [default = 0]
+	-C num : limit on the number of conflicts [default = 100]
+	-L num : limit on node level to fraig (0 = fraig all nodes) [default = 0]
+	-s     : toggle considering sparse functions [default = yes]
+	-p     : toggle proving the miter outputs [default = no]
+	-v     : toggle verbose printout [default = no]
+	-h     : print the command usage
+
+usage: iresyn [-lvh]
+	         performs combinational resynthesis
+	-l     : toggle preserving the number of levels [default = yes]
+	-v     : toggle verbose printout [default = no]
+	-h     : print the command usage
+
+usage: irw [-lzvh]
+	         perform combinational AIG rewriting
+	-l     : toggle preserving the number of levels [default = yes]
+	-z     : toggle using zero-cost replacements [default = no]
+	-v     : toggle verbose printout [default = no]
+	-h     : print the command usage
+
+usage: irws [-zvh]
+	         perform sequential AIG rewriting
+	-z     : toggle using zero-cost replacements [default = no]
+	-v     : toggle verbose printout [default = no]
+	-h     : print the command usage
+
+usage: isat [-C num] [-vh]
+	         tries to prove the miter constant 0
+	-C num : limit on the number of conflicts [default = 100000]
+	-v     : toggle verbose printout [default = no]
+	-h     : print the command usage
+
+usage: istrash [-h]
+	         perform sequential structural hashing
+	-h     : print the command usage
+
+usage: qbf [-PI num] [-dvh]
+	         solves QBF problem EpVxM(p,x)
+	-P num : number of parameters p (should be the first PIs) [default = -1]
+	-I num : quit after the given iteration even if unsolved [default = 500]
+	-d     : toggle dumping QDIMACS file instead of solving [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+	
+	         Consider specification of the two-input XOR and its implementation in the form of a 4:1 MUX:
+
+	         > # file s.blif
+	         > .model xor2
+	         > .inputs d0 d1 d2 d3 a b
+	         > .outputs F
+	         > .names a b F
+	         > 01 1
+	         > 10 1
+	         > .end
+
+	         > # file i.blif
+	         > .model mux21
+	         > .inputs d0 d1 d2 d3 a b
+	         > .outputs F
+	         > .names d0 d1 d2 d3 a b F
+	         > 1---00 1
+	         > -1--10 1
+	         > --1-01 1
+	         > ---111 1
+	         > .end
+
+	         The following run shows how to assign data inputs to the MUX (the first 4 inputs of the miter) to get the XOR:
+
+	         > abc 51> miter -n i.blif s.blif; st -i; ps
+	         > i_s_miter: i/o =    6/    1  lat =    0  and =     15  lev =  6
+
+	         > abc 53> qbf -P 4
+	         > Parameters: 0110  Statistics: 0=2 1=2
+	         > Solved after 1 iterations.  Total runtime =     0.00 sec
+
+	         > abc 53> &get; &qbf -P 4
+	         > Parameters: 0110  Statistics: 0=2 1=2
+	         > The problem is SAT after 2 iterations.  Time =     0.00 sec
+
+	         What we synthesized is the truth table of the XOR gate!
+
+   ----------------------------------------------------------------------
+
+New word level commands:
+ :blast           :cec             :clp             :get            
+ :ps              :put             :read            :test           
+ :write           @_cec            @_clp            @_get           
+ @_ps             @_put            @_read           @_test          
+ @_write         
+
+usage: :blast [-svh]
+	         performs bit-blasting of the word-level design
+	-s     : toggle blasting sequential elements [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: :cec [-vh]
+	         combinational equivalence checking
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: :clp [-vh]
+	         collapses the current hierarchical design
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: :get [-mvh]
+	         extracts AIG or mapped network into the hierarchical design
+	-m     : toggle using mapped network from main-space [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: :ps [-M num] [-madvh]
+	         prints statistics
+	-M num : the number of first modules to report [default = 0]
+	-m     : toggle printing multipliers [default = no]
+	-a     : toggle printing adders [default = no]
+	-d     : toggle printing distrubition [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: :put [-bsvh]
+	         extracts AIG from the hierarchical design
+	-b     : toggle using barrier buffers [default = yes]
+	-s     : toggle blasting sequential elements [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: :read [-tdvh] <file_name>
+	         reads hierarchical design
+	-t     : toggle testing the parser [default = no]
+	-d     : toggle computing DFS ordering [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: :test [-vh]
+	         experiments with word-level networks
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: :write [-cvh]
+	         writes the design into a file in BLIF or Verilog
+	-c     : toggle inlining input concatenations [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: @_cec [-vh]
+	         combinational equivalence checking
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: @_clp [-vh]
+	         collapses the current hierarchical design
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: @_get [-mvh]
+	         inserts AIG or mapped network into the hierarchical design
+	-m     : toggle using mapped network from main-space [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: @_ps [-M num] [-vh]
+	         prints statistics
+	-M num : the number of first modules to report [default = 0]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: @_put [-bvh]
+	         extracts AIG from the hierarchical design
+	-b     : toggle using barrier buffers [default = yes]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: @_read [-apvh] <file_name>
+	         reads hierarchical design in BLIF or Verilog
+	-a     : toggle using old ABC parser [default = no]
+	-p     : toggle using Ptr construction [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: @_test [-vh]
+	         experiments with word-level networks
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: @_write [-apvh]
+	         writes the design into a file in BLIF or Verilog
+	-a     : toggle using assign-statement for primitives [default = yes]
+	-p     : toggle using Ptr construction (mapped Verilog only) [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+   ----------------------------------------------------------------------
+
+Printing commands:
+ pf               pfan             pg               print_auto      
+ print_cone       print_delay      print_dsd        print_exdc      
+ print_factor     print_fanio      print_gates      print_io        
+ print_kmap       print_latch      print_level      print_mffc      
+ print_mint       print_miter      print_sharing    print_stats     
+ print_status     print_supp       print_symm       print_unate     
+ print_xcut       ps               psu              show            
+ show_bdd         show_cut        
+
+usage: print_factor [-snh] <node>
+	        prints the factored forms (FFs) of nodes
+	-s    : toggles printing SOP instead of FF [default = FF]
+	-n    : toggles real/dummy fanin names [default = real]
+	-h    : print the command usage
+	node  : (optional) one node to consider
+
+usage: print_fanio [-fiscmvh]
+	        prints the statistics about different objects in the network
+	-f    : toggles considering fanins/fanouts of all nodes [default = no]
+	-i    : toggles considering fanins/fanouts of CI/CO [default = no]
+	-s    : toggles considering TFO/TFI support sizes of CI/CO [default = no]
+	-c    : toggles considering TFO/TFI cone sizes of CI/CO [default = no]
+	-m    : toggles printing MFFC sizes instead of fanouts [default = no]
+	-v    : toggles verbose way of printing the stats [default = no]
+	-h    : print the command usage
+
+usage: print_gates [-luh]
+	        prints statistics about gates used in the network
+	-l    : used library gate names (if mapped) [default = yes]
+	-u    : update profile before printing it[default = no]
+	-h    : print the command usage
+
+usage: print_auto [-O <num>] [-nvh]
+	           computes autosymmetries of the PO functions
+	-O <num> : (optional) the 0-based number of the output [default = all]
+	-n       : enable naive BDD-based computation [default = no].
+	-v       : enable verbose output [default = no].
+	-h       : print the command usage
+
+usage: print_cone [-h]
+	        prints cones of influence info for each primary output
+	-h    : print the command usage
+
+usage: print_delay [-h] <CO_name> <CI_name>
+	            prints one critical path of the mapped network
+	-h        : print the command usage
+	<CO_name> : (optional) the sink of the critical path (primary output or flop input)
+	<CI_name> : (optional) the source of the critical path (primary input or flop output)
+	            (if CO and/or CI are not given, uses the most critical ones)
+
+usage: print_dsd [-pcdh] [-N <num>]
+	           print DSD formula for a single-output function with less than 16 variables
+	-p       : toggle printing profile [default = no]
+	-c       : toggle recursive cofactoring [default = no]
+	-d       : toggle printing decompositions [default = no]
+	-N <num> : the number of levels to cofactor [default = 1]
+	-h       : print the command usage
+
+usage: print_exdc [-dh]
+	        prints the EXDC network statistics
+	-d    : toggles printing don't-care percentage [default = no]
+	-h    : print the command usage
+
+usage: print_factor [-snh] <node>
+	        prints the factored forms (FFs) of nodes
+	-s    : toggles printing SOP instead of FF [default = FF]
+	-n    : toggles real/dummy fanin names [default = real]
+	-h    : print the command usage
+	node  : (optional) one node to consider
+
+usage: print_fanio [-fiscmvh]
+	        prints the statistics about different objects in the network
+	-f    : toggles considering fanins/fanouts of all nodes [default = no]
+	-i    : toggles considering fanins/fanouts of CI/CO [default = no]
+	-s    : toggles considering TFO/TFI support sizes of CI/CO [default = no]
+	-c    : toggles considering TFO/TFI cone sizes of CI/CO [default = no]
+	-m    : toggles printing MFFC sizes instead of fanouts [default = no]
+	-v    : toggles verbose way of printing the stats [default = no]
+	-h    : print the command usage
+
+usage: print_gates [-luh]
+	        prints statistics about gates used in the network
+	-l    : used library gate names (if mapped) [default = yes]
+	-u    : update profile before printing it[default = no]
+	-h    : print the command usage
+
+usage: print_io [-fh] <node>
+	        prints the PIs/POs/flops or fanins/fanouts of a node
+	-f    : toggles printing flops [default = yes]
+	-h    : print the command usage
+	node  : the node to print fanins/fanouts
+
+usage: print_kmap [-nh] <node>
+	        shows the truth table of the node
+	-n    : toggles real/dummy fanin names [default = real]
+	-h    : print the command usage
+	<node>: the node to consider (default = the driver of the first PO)
+
+usage: print_latch [-sh]
+	        prints information about latches
+	-s    : toggles printing SCCs of registers [default = no]
+	-h    : print the command usage
+
+usage: print_level [-npovh] <node>
+	        prints information about node level and cone size
+	-n    : toggles printing nodes by levels [default = no]
+	-p    : toggles printing level profile [default = yes]
+	-o    : toggles printing output levels [default = no]
+	-v    : enable verbose output [default = no].
+	-h    : print the command usage
+	node  : (optional) one node to consider
+
+usage: print_mffc [-h]
+	        prints the MFFC of each node in the network
+	-h    : print the command usage
+
+usage: print_mint [-svwh]
+	        prints the number of on-set minterms in the PO functions
+	-v    : enable verbose output [default = no].
+	-h    : print the command usage
+
+usage: print_miter [-h]
+	        prints the status of the miter
+	-h    : print the command usage
+
+usage: print_sharing [-h]
+	        prints the number of shared nodes in the TFI cones of the COs
+	-h    : print the command usage
+
+usage: print_stats [-fbdltmpgscuh]
+	        prints the network statistics
+	-f    : toggles printing the literal count in the factored forms [default = no]
+	-b    : toggles saving the best logic network in "best.blif" [default = no]
+	-d    : toggles dumping statistics about the network into file [default = no]
+	-l    : toggles printing delay of LUT mapping using LUT library [default = no]
+	-t    : toggles printing runtime statistics [default = no]
+	-m    : toggles printing MUX statistics [default = no]
+	-p    : toggles printing power dissipation due to switching [default = no]
+	-g    : toggles printing percentage of increased power due to glitching [default = no]
+	-s    : toggles not counting single-output nodes as nodes [default = no]
+	-c    : toggles not counting constants and single-output nodes as nodes [default = no]
+	-u    : toggles printing memory usage [default = no]
+	-h    : print the command usage
+
+usage: print_status [-L file] [-osh]
+	          prints verification status
+	-L file : the log file name [default = no logging]
+	-o      : toggle printing output status [default = no]
+	-s      : toggle using short print-out [default = yes]
+	-h      : print the command usage
+
+usage: print_supp [-svwh]
+	        prints the supports of the CO nodes
+	-s    : toggle printing structural support only [default = yes].
+	-v    : enable verbose output [default = no].
+	-w    : enable printing CI/CO dependency matrix [default = no].
+	-h    : print the command usage
+
+usage: print_symm [-bnrvh]
+	         computes symmetries of the PO functions
+	-b     : toggle BDD-based or SAT-based computations [default = SAT].
+	-n     : enable naive BDD-based computation [default = no].
+	-r     : enable dynamic BDD variable reordering [default = yes].
+	-v     : enable verbose output [default = no].
+	-h     : print the command usage
+
+usage: print_unate [-bnvh]
+	         computes unate variables of the PO functions
+	-b     : toggle BDD-based or SAT-based computations [default = BDD].
+	-n     : toggle naive BDD-based computation [default = no].
+	-v     : enable verbose output [default = no].
+	-h     : print the command usage
+
+usage: print_xcut [-h]
+	        prints the size of the cross cut of the current network
+	-h    : print the command usage
+
+usage: print_stats [-fbdltmpgscuh]
+	        prints the network statistics
+	-f    : toggles printing the literal count in the factored forms [default = no]
+	-b    : toggles saving the best logic network in "best.blif" [default = no]
+	-d    : toggles dumping statistics about the network into file [default = no]
+	-l    : toggles printing delay of LUT mapping using LUT library [default = no]
+	-t    : toggles printing runtime statistics [default = no]
+	-m    : toggles printing MUX statistics [default = no]
+	-p    : toggles printing power dissipation due to switching [default = no]
+	-g    : toggles printing percentage of increased power due to glitching [default = no]
+	-s    : toggles not counting single-output nodes as nodes [default = no]
+	-c    : toggles not counting constants and single-output nodes as nodes [default = no]
+	-u    : toggles printing memory usage [default = no]
+	-h    : print the command usage
+
+usage: print_supp [-svwh]
+	        prints the supports of the CO nodes
+	-s    : toggle printing structural support only [default = yes].
+	-v    : enable verbose output [default = no].
+	-w    : enable printing CI/CO dependency matrix [default = no].
+	-h    : print the command usage
+
+usage: show [-srgfdih]
+       visualizes the network structure using DOT and GSVIEW
+	-s    : toggles visualization of sequential networks [default = no].
+	-r    : toggles ordering nodes in reverse order [default = yes].
+	-g    : toggles printing gate names for mapped network [default = no].
+	-f    : toggles visualizing flop dependency graph [default = no].
+	-d    : toggles keeping the .dot file used to produce the .ps file [default = no].
+	-i    : toggles using original AIG object IDs as node labels [default = no].
+	-h    : print the command usage
+
+usage: show_bdd [-cgrwh] <node>
+       uses DOT and GSVIEW to visualize the global BDDs of primary outputs
+       in terms of primary inputs or the local BDD of a node in terms of its fanins
+	<node>: (optional) the node to consider [default = the driver of the first PO]
+	-c    : toggle visualizing BDD with complemented edges [default = no].
+	-g    : toggle visualizing the global BDDs of primary outputs [default = no].
+	-r    : toggles dynamic variable reordering [default = yes]
+	-w    : toggles printing width profile of the node's BDD [default = no]
+	-h    : print the command usage
+
+usage: show_cut [-N <num>] [-C <num>] [-h] <node>
+             visualizes the cut of a node using DOT and GSVIEW
+	-N <num> : the max size of the cut to be computed [default = 10]
+	-C <num> : the max support of the containing cone [default = 1000000000]
+	<node>   : the node to consider
+	-h       : print the command usage
+
+   ----------------------------------------------------------------------
+
+SC mapping commands:
+ amap             attach           map              phase_map       
+ print_genlib     print_library    print_profile    read_genlib     
+ read_library     read_profile     read_super       super           
+ super2           superc           supercl          timescale       
+ unmap            write_genlib     write_library    write_profile   
+
+usage: amap [-FAC <num>] [-EQ <float>] [-mxisvh]
+	           performs standard cell mapping of the current network
+	-F num   : the number of iterations of area flow [default = 1]
+	-A num   : the number of iterations of exact area [default = 4]
+	-C num   : the maximum number of cuts at a node [default = 500]
+	-E float : sets epsilon used for tie-breaking [default = 0.001000]
+	-Q float : area/delay preference ratio [default = 0.00 (area-only)] 
+	-m       : toggles using MUX matching [default = no]
+	-x       : toggles using XOR matching [default = yes]
+	-i       : toggles assuming inverters are free [default = no]
+	-s       : toggles sweep after mapping [default = no]
+	-v       : toggles verbose output [default = no]
+	-h       : print the command usage
+
+usage: attach [-h]
+	        replaces the SOP functions by the gates from the library
+	-h    : print the command usage
+
+usage: map [-DABFSG float] [-M num] [-arspfuovh]
+	           performs standard cell mapping of the current network
+	-D float : sets the global required times [default = not used]
+	-A float : "area multiplier" to bias gate selection [default = 0.00]
+	-B float : "delay multiplier" to bias gate selection [default = 0.00]
+	-F float : the logarithmic fanout delay parameter [default = 0.00]
+	-S float : the slew parameter used to generate the library [default = 0.00]
+	-G float : the gain parameter used to generate the library [default = 250.00]
+	-M num   : skip gate classes whose size is less than this [default = 0]
+	-a       : toggles area-only mapping [default = no]
+	-r       : toggles area recovery [default = yes]
+	-s       : toggles sweep after mapping [default = no]
+	-p       : optimizes power by minimizing switching [default = no]
+	-f       : do not use large gates to map high-fanout nodes [default = no]
+	-u       : use standard-cell profile [default = no]
+	-o       : toggles using buffers to decouple combinational outputs [default = no]
+	-v       : toggles verbose output [default = no]
+	-h       : print the command usage
+
+usage: phase_map [-vh]
+	        tries to replace each gate by its complement (area-only)
+	-v    : toggles verbose output [default = no]
+	-h    : print the command usage
+
+
+usage: print_genlib [-savh]
+	          print the current genlib library
+	-s      : toggles writing short form [default = no]
+	-a      : toggles writing min-area gates [default = no]
+	-v      : toggles enabling of verbose output [default = no]
+	-h      : print the command usage
+
+
+usage: print_genlib [-savh]
+	          print the current genlib library
+	-s      : toggles writing short form [default = no]
+	-a      : toggles writing min-area gates [default = no]
+	-v      : toggles enabling of verbose output [default = no]
+	-h      : print the command usage
+
+
+usage: print_profile [-h]
+	          print the current gate profile
+	-h      : print the command usage
+
+usage: read_genlib [-W float] [-E filename] [-K num] [-nvh]
+	           read the library from a genlib file
+	           (if the library contains more than one gate
+	           with the same Boolean function, only the gate
+	           with the smallest area will be used)
+	-W float : wire delay (added to pin-to-pin gate delays) [default = 0]
+	-E file  : the file name with gates to be excluded [default = none]
+	-K num   : the max number of gate fanins (0 = no limit) [default = 0]
+	-n       : toggle replacing gate/pin names by short strings [default = no]
+	-v       : toggle verbose printout [default = yes]
+	-h       : enable verbose output
+
+usage: read_genlib [-W float] [-E filename] [-K num] [-nvh]
+	           read the library from a genlib file
+	           (if the library contains more than one gate
+	           with the same Boolean function, only the gate
+	           with the smallest area will be used)
+	-W float : wire delay (added to pin-to-pin gate delays) [default = 0]
+	-E file  : the file name with gates to be excluded [default = none]
+	-K num   : the max number of gate fanins (0 = no limit) [default = 0]
+	-n       : toggle replacing gate/pin names by short strings [default = no]
+	-v       : toggle verbose printout [default = yes]
+	-h       : enable verbose output
+
+usage: read_profile [-h] <file>
+	          read a gate profile from a profile file
+	-h      : enable verbose output
+	<file>  : file name to read the profile
+
+
+usage: read_super [-ovh]
+	         read the supergate library from the file
+	-e file : file contains list of genlib gates to exclude
+	-o      : toggles the use of old file format [default = new]
+	-v      : toggles enabling of verbose output [default = yes]
+	-h      : print the command usage
+
+usage: super [-ILNT num] [-DA float] [-E file] [-sovh] <genlib_file>
+	         precomputes the supergates for the given genlib library
+	-I num   : the max number of supergate inputs [default = 5]
+	-L num   : the max number of levels of gates [default = 2]
+	-N num   : the limit on the number of considered supergates [default = 0]
+	-T num   : the approximate runtime limit in seconds [default = 0]
+	-D float : the max delay of the supergates [default = 0.00]
+	-A float : the max area of the supergates [default = 0.00]
+	-E file  : file contains list of genlib gates to exclude
+	-s       : toggle the use of inverters at the inputs [default = no]
+	-o       : toggle dumping the supergate library in old format [default = no]
+	-v       : enable verbose output [default = no]
+	-h       : print the help message
+
+	Here is a piece of advice on precomputing supergate libraries:
+	
+	Start with the number of inputs equal to 5 (-I 5), the number of 
+	levels equal to 2 (-L 2), the delay equal to 2-3 delays of inverter, 
+	the area equal to 2-3 areas of two input NAND, and runtime limit equal 
+	to 10 seconds (-T 10). Run precomputation and learn from the result.
+	Determine what parameter is most constraining and try to increase 
+	the value of that parameter. The goal is to have a well-balanced
+	set of constraints and the resulting supergate library containing
+	approximately 5K-20K supergates. Typically, it is better to increase
+	delay limit rather than area limit, because having large-area supergates
+	may result in a considerable increase in area.
+	
+	Note that a good supergate library for experiments typically can be 
+	precomputed in 30 sec or less. Increasing runtime limit makes sense when
+	other parameters are well-balanced and it is needed to enumerate more
+	choices to have a good result. In the end, to compute the final library
+	the runtime can be set to 300 sec to ensure the ultimate quality.
+	In some cases, the runtime has to be reduced if the supergate library
+	contains too many supergates (> 500K).
+	
+	When precomputing libraries of 6 inputs (-i 6), start with even more 
+	restricted parameters and gradually increase them until the goal is met.
+	
+
+usage: super2 [-IL num] [-vh]
+	         precomputes the supergates composed of AND2s and INVs
+	-I num : the max number of inputs to the supergate [default = 4]
+	-L num : the max number of logic levels of gates [default = 3]
+	-v     : enable verbose output
+	-h     : print the help message
+
+usage: superc [-h]
+	      performs superchoicing
+	      (accumulate: "r file.blif; rsup; b; sc; f -ac; wb file_sc.blif")
+	      (map without supergate library: "r file_sc.blif; ft; map")
+	-h  : print the command usage
+
+usage: supercl [-K num] [-N num] [-vh]
+	        performs superchoicing for K-LUTs
+	        (accumulate: "r file.blif; b; scl; f -ac; wb file_sc.blif")
+	        (FPGA map: "r file_sc.blif; ft; read_lut lutlibK; fpga")
+	-K num : the number of LUT inputs [default = 4]
+	-N num : the max size of the cut [default = 10]
+	-v     : toggles verbose output [default = yes]
+	-h     : print the command usage
+
+usage: timescale [-T float] [-vh]
+	           scales timing information of the current network
+	-T float : multiplicative factor [default = 0.010000]
+	-v       : toggles verbose output [default = no]
+	-h       : print the command usage
+
+usage: unmap [-h]
+	        replaces the library gates by the logic nodes represented using SOPs
+	-h    : print the command usage
+
+
+usage: write_genlib [-agvh] <file>
+	          writes the current genlib library into a file
+	-a      : toggles writing min-area gates [default = no]
+	-g      : toggles writing the library in Verilog [default = no]
+	-v      : toggles enabling of verbose output [default = no]
+	-h      : print the command usage
+	<file>  : optional file name to write the library
+
+
+usage: write_genlib [-agvh] <file>
+	          writes the current genlib library into a file
+	-a      : toggles writing min-area gates [default = no]
+	-g      : toggles writing the library in Verilog [default = no]
+	-v      : toggles enabling of verbose output [default = no]
+	-h      : print the command usage
+	<file>  : optional file name to write the library
+
+
+usage: write_profile [-h] <file>
+	          writes the current profile into a file
+	-h      : print the command usage
+	<file>  : file name to write the profile
+
+   ----------------------------------------------------------------------
+
+SCL mapping commands:
+ buffer           dnsize           dump_genlib      leak2area       
+ maxsize          minsize          print_buf        print_constr    
+ print_gs         print_lib        read_constr      read_lib        
+ read_scl         reset_constr     stime            topo            
+ unbuffer         upsize           write_constr     write_lib       
+ write_scl       
+
+usage: buffer [-GSN num] [-sbpcvwh]
+	           performs buffering and sizing on mapped network
+	-G <num> : target gain percentage [default = 300]
+	-S <num> : target slew in picoseconds [default = 100]
+	-N <num> : the maximum fanout count [default = 10]
+	-s       : toggle performing only sizing [default = no]
+	-b       : toggle using buffers instead of inverters [default = yes]
+	-p       : toggle buffering primary inputs [default = no]
+	-c       : toggle using wire-loads if specified [default = no]
+	-v       : toggle printing verbose information [default = no]
+	-w       : toggle printing more verbose information [default = no]
+	-h       : print the command usage
+
+usage: dnsize [-IJNDGTX num] [-csdvwh]
+	           selectively decreases gate sizes while maintaining delay
+	-I <num> : the number of downsizing iterations to perform [default = 5]
+	-J <num> : the number of iterations without improvement to stop [default = 50]
+	-N <num> : limit on discrete downsizing steps at a node [default = 1000]
+	-D <num> : delay target set by the user, in picoseconds [default = 0]
+	-G <num> : delay gap during updating, in picoseconds [default = 1000]
+	-T <num> : approximate timeout in seconds [default = 0]
+	-X <num> : ratio for buffer tree estimation [default = 0]
+	-c       : toggle using wire-loads if specified [default = no]
+	-s       : toggle using slack based on departure times [default = yes]
+	-d       : toggle dumping statistics into a file [default = no]
+	-v       : toggle printing verbose information [default = no]
+	-w       : toggle printing more verbose information [default = no]
+	-h       : print the command usage
+
+usage: dump_genlib [-SG float] [-M num] [-vh] <file>
+	           writes GENLIB file for SCL library
+	-S float : the slew parameter used to generate the library [default = 0.00]
+	-G float : the gain parameter used to generate the library [default = 200.00]
+	-M num   : skip gate classes whose size is less than this [default = 4]
+	-v       : toggle printing verbose information [default = no]
+	-h       : print the command usage
+	<file>   : optional GENLIB file name
+
+usage: leak2area [-AB float] [-v]
+	           converts leakage into area: Area = A * Area + B * Leakage
+	-A float : the multiplicative coefficient to transform area [default = 1.00]
+	-B float : the multiplicative coefficient to transform leakage [default = 1.00]
+	-v       : toggle printing verbose information [default = no]
+	-h       : print the help massage
+
+usage: maxsize [-vh]
+	           upsizes all gates to their maximum size
+	-v       : toggle printing verbose information [default = no]
+	-h       : print the command usage
+
+usage: minsize [-vh]
+	           downsizes all gates to their minimum size
+	-v       : toggle printing verbose information [default = no]
+	-h       : print the command usage
+
+usage: print_buf [-vh]
+	           prints buffers trees of the current design
+	-v       : toggle printing verbose information [default = no]
+	-h       : print the command usage
+
+usage: print_constr [-vh] <file>
+	         prints current timing constraints
+	-v     : toggle printing verbose information [default = no]
+	-h     : prints the command summary
+	<file> : the name of a file to read
+
+usage: print_gs [-h]
+	         prints gate sizes in the current mapping
+	-h     : print the help massage
+
+usage: print_lib [-SG float] [-ish]
+	           prints statistics of Liberty library
+	-S float : the slew parameter used to generate the library [default = 0.00]
+	-G float : the gain parameter used to generate the library [default = 100.00]
+	-i       : toggle printing invs/bufs only [default = no]
+	-s       : toggle printing in short format [default = no]
+	-h       : print the help massage
+
+usage: read_constr [-nvh] <file>
+	         read file with timing constraints for standard-cell designs
+	-n     : toggle using new constraint file format [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : prints the command summary
+	<file> : the name of a file to read
+
+usage: read_lib [-SG float] [-M num] [-dnuvwmph] [-X cell_name] <file> <file2>
+	           reads Liberty library from file
+	-S float : the slew parameter used to generate the library [default = 0.00]
+	-G float : the gain parameter used to generate the library [default = 0.00]
+	-M num   : skip gate classes whose size is less than this [default = 0]
+	-X name  : adds name to the list of cells ABC shouldn't use. Flag can be passed multiple times
+	-d       : toggle dumping the parsed library into file "*_temp.lib" [default = no]
+	-n       : toggle replacing gate/pin names by short strings [default = no]
+	-u       : toggle setting unit area for all cells [default = no]
+	-v       : toggle writing verbose information [default = yes]
+	-w       : toggle writing information about skipped gates [default = no]
+	-m       : toggle merging library with exisiting library [default = no]
+	-p       : toggle using prefix for the cell names [default = no]
+	-h       : prints the command summary
+	<file>   : the name of a file to read
+	<file2>  : the name of a file to read (optional)
+
+usage: read_scl [-dh] <file>
+	         reads extracted Liberty library from file
+	-d     : toggle dumping the parsed library into file "*_temp.lib" [default = no]
+	-h     : prints the command summary
+	<file> : the name of a file to read
+
+usage: reset_constr [-vh] <file>
+	         removes current timing constraints
+	-v     : toggle printing verbose information [default = no]
+	-h     : prints the command summary
+	<file> : the name of a file to read
+
+usage: stime [-X num] [-capdth]
+	         performs STA using Liberty library
+	-X     : min Cout/Cave ratio for tree estimations [default = 0]
+	-c     : toggle using wire-loads if specified [default = no]
+	-a     : display timing information for all nodes [default = no]
+	-p     : display timing information for critical path [default = no]
+	-d     : toggle dumping statistics into a file [default = no]
+	-h     : print the help massage
+
+usage: topo [-vh]
+	           rearranges nodes to be in a topological order
+	-v       : toggle printing verbose information [default = no]
+	-h       : print the command usage
+
+usage: unbuffer [-ivh]
+	           collapses buffer/inverter trees
+	-i       : toggle removing interters [default = no]
+	-v       : toggle printing verbose information [default = no]
+	-h       : print the command usage
+
+usage: upsize [-IJWRNDGTXB num] [-csdvwh]
+	           selectively increases gate sizes on the critical path
+	-I <num> : the number of upsizing iterations to perform [default = 1000]
+	-J <num> : the number of iterations without improvement to stop [default = 50]
+	-W <num> : delay window (in percent) of near-critical COs [default = 1]
+	-R <num> : ratio of critical nodes (in percent) to update [default = 10]
+	-N <num> : limit on discrete upsizing steps at a node [default = 1000]
+	-D <num> : delay target set by the user, in picoseconds [default = 0]
+	-G <num> : delay gap during updating, in picoseconds [default = 0]
+	-T <num> : approximate timeout in seconds [default = 0]
+	-X <num> : ratio for buffer tree estimation [default = 0]
+	-B <num> : frequency of bypass transforms [default = 0]
+	-c       : toggle using wire-loads if specified [default = no]
+	-s       : toggle using slack based on departure times [default = yes]
+	-d       : toggle dumping statistics into a file [default = no]
+	-v       : toggle printing verbose information [default = no]
+	-w       : toggle printing more verbose information [default = no]
+	-h       : print the command usage
+
+usage: write_constr [-vh] <file>
+	         writes current timing constraints into a file
+	-v     : toggle printing verbose information [default = no]
+	-h     : prints the command summary
+	<file> : the name of a file to read
+
+usage: write_lib [-h] <file>
+	         write current Liberty library into file
+	-h     : print the help massage
+	<file> : the name of the file to write
+
+usage: write_scl [-h] <file>
+	         write extracted Liberty library into file
+	-h     : print the help massage
+	<file> : the name of the file to write
+
+   ----------------------------------------------------------------------
+
+Sequential commands:
+ clockgate        cretime          cubeenum         cycle           
+ dretime          extwin           fretime          funenum         
+ init             inswin           lcorr            onehot          
+ pathenum         permute          phase            pipe            
+ retime           scleanup         scorr            sim             
+ sim3             ssweep           symfun           synch           
+ testscorr        testssw          undc             unpermute       
+ xsim             zero            
+
+usage: clockgate [-LNDCVK <num>] [-avwh] <file>
+	         sequential clock gating with observability don't-cares
+	-L num : max level number of a clock gate [default = 25]
+	-N num : max number of candidates for a flop [default = 1000]
+	-D num : max number of ODC levels to consider [default = 0]
+	-C num : max number of conflicts at a node [default = 10]
+	-V num : min number of vars to recycle SAT solver [default = 1000]
+	-K num : min number of flops to recycle SAT solver [default = 10]
+	-a     : toggle minimizing area-only [default = no]
+	-v     : toggle verbose output [default = no]
+	-w     : toggle even more detailed output [default = no]
+	-h     : print the command usage
+	file   : (optional) constraints for primary inputs and register outputs
+
+usage: cretime [-vh]
+	         performs most-forward retiming with equiv classes
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: cubeenum [-vh]
+	         enumerates reachable states of 2x2x2 cube
+	         (http://en.wikipedia.org/wiki/Pocket_Cube)
+	-z     : toggle using ZDD-based algorithm [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: cycle [-F num] [-xvh]
+	         cycles sequential circuit for the given number of timeframes
+	         to derive a new initial state (which may be on the envelope)
+	-F num : the number of frames to simulate [default = 100]
+	-x     : use x-valued primary inputs [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: dretime [-NS num] [-mfbiavh]
+	         new implementation of min-area (or most-forward) retiming
+	-m     : toggle min-area retiming and most-forward retiming [default = min-area]
+	-f     : enables forward-only retiming [default = no]
+	-b     : enables backward-only retiming [default = no]
+	-i     : enables init state computation [default = yes]
+	-N num : the max number of one-frame iterations to perform [default = 20]
+	-S num : the max number of forward retiming steps to perform [default = 100000]
+	-a     : enables a fast most-forward algorithm [default = no]
+	-v     : enables verbose output [default = no]
+	-h     : print the command usage
+
+usage: extwin [-ND <num>] [-vh]
+	         extracts sequential window from the AIG
+	-N num : the ID of the object to use as the center [default = -1]
+	-D num : the "radius" of the window [default = 5]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: fretime [-M num] [-D num] [-fbvih]
+	         retimes the current network using flow-based algorithm
+	-M num : the maximum number of iterations [default = 999]
+	-D num : the maximum delay [default = none]
+	-i     : enables init state computation [default = yes]
+	-k     : blocks retiming over const nodes [default = no]
+	-g     : guarantees init state computation [default = no]
+	-c     : very fast (but conserv.) delay constraints [default = no]
+	-f     : enables forward-only retiming  [default = no]
+	-b     : enables backward-only retiming [default = no]
+	-v     : enables verbose output [default = no]
+	-h     : print the command usage
+
+usage: funenum [-SIM num] [-trldmvph]
+	         enumerates minimum 2-input-gate implementations
+	-S num : the maximum intermediate support size [default = 4]
+	-I num : the number of inputs of Boolean functions [default = 4]
+	-M num : the maximum number of 2-input gates [default = 32]
+	-t     : toggle adding combination of two gates [default = no]
+	-r     : toggle reducing the last level [default = no]
+	-l     : toggle generating L(f) rather than C(f) [default = no]
+	-d     : toggle generating D(f) rather than C(f) [default = no]
+	-m     : toggle generating multiplicity statistics [default = no]
+	-v     : toggle verbose output [default = no]
+	-p     : toggle dumping result library (formula and AIG) [default = no]
+	-h     : print the command usage
+
+usage: init [-zordcnh] [-S <init_string>]
+	         resets initial states of all latches
+	-z     : set zeros initial states [default = no]
+	-o     : set ones initial states [default = no]
+	-d     : set don't-care initial states [default = no]
+	-r     : set random initial states [default = no]
+	-c     : set failure current state from the CEX (and run "zero") [default = no]
+	-n     : set next state after failure from the CEX (and run "zero") [default = no]
+	-h     : print the command usage
+	-S str : (optional) initial state  [default = unused]
+
+usage: inswin [-ND <num>] [-vh] <file>
+	         inserts sequential window into the AIG
+	-N num : the ID of the object to use as the center [default = -1]
+	-D num : the "radius" of the window [default = 5]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+	file   : file with the AIG to be inserted
+
+usage: lcorr [-PCSX num] [-nvh]
+	         computes latch correspondence using 1-step induction
+	-P num : number of time frames to use as the prefix [default = 0]
+	-C num : limit on the number of conflicts [default = 1000]
+	-S num : the max number of SAT variables [default = 1000]
+	-X num : the number of iterations of little or no improvement [default = 0]
+	-n     : toggle using new algorithm [default = yes]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: onehot [-h]
+	        converts natural encoding into one-hot encoding
+	-h    : print the command usage
+
+usage: pathenum [-N num] [-vh]
+	         enumerates self-avoiding paths on the NxN grid
+	-N num : the size of the grid to consider [default = 4]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: permute [-S num] [-iofnxh] [-F filename]
+	                performs random permutation of inputs/outputs/flops
+	-S num        : the random seed to generate permutations (0 <= num < INT_MAX) [default = -1]
+	-i            : toggle permuting primary inputs [default = yes]
+	-o            : toggle permuting primary outputs [default = yes]
+	-f            : toggle permuting flip-flops [default = yes]
+	-n            : toggle deriving new topological ordering of nodes [default = yes]
+	-x            : toggle permuting inputs based on their fanout count [default = no]
+	-h            : print the command usage
+	-F <filename> : (optional) file with the flop permutation
+
+usage: phase [-FP <num>] [-ipcvh]
+	         performs sequential cleanup of the current network
+	         by removing nodes and latches that do not feed into POs
+	-F num : the number of frames to abstract [default = 0]
+	-P num : the number of prefix frames to skip [default = 0]
+	-i     : toggle ignoring the initial state [default = no]
+	-p     : toggle printing statistics about generators [default = no]
+	-c     : update the current CEX derived for a new AIG after "phase"
+	         to match the current AIG (the one before "phase") [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: pipe [-L num] [-h]
+	         inserts the given number of latches at each PI for pipelining
+	-L num : the number of latches to insert [default = 5]
+	-h     : print the command usage
+
+usage: retime [-MD num] [-fbsovh]
+	         retimes the current network using one of the algorithms:
+	             1: most forward retiming
+	             2: most backward retiming
+	             3: forward and backward min-area retiming
+	             4: forward and backward min-delay retiming
+	             5: mode 3 followed by mode 4
+	             6: Pan's optimum-delay retiming using binary search
+	-M num : the retiming algorithm to use [default = 5]
+	-D num : the minimum delay target (0=unused) [default = 0]
+	-f     : enables forward-only retiming in modes 3,4,5 [default = no]
+	-b     : enables backward-only retiming in modes 3,4,5 [default = no]
+	-s     : enables retiming one step only in mode 4 [default = no]
+	-o     : enables usind old flop naming conventions [default = no]
+	-v     : enables verbose output [default = no]
+	-h     : print the command usage
+
+usage: scleanup [-cenmFSvwh]
+	         performs sequential cleanup of the current network
+	         by removing nodes and latches that do not feed into POs
+	-c     : sweep stuck-at latches detected by ternary simulation [default = yes]
+	-e     : merge equal latches (same data inputs and init states) [default = yes]
+	-n     : toggle preserving latch names [default = yes]
+	-m     : toggle using hybrid ternary/symbolic simulation [default = no]
+	-F num : the number of first frames simulated symbolically [default = 1]
+	-S num : the number of frames when symbolic saturation begins [default = 512]
+	-v     : toggle verbose output [default = no]
+	-w     : toggle very verbose output [default = no]
+	-h     : print the command usage
+
+usage: scorr [-PQFCLSIVMNX <num>] [-cmplkodsefqvwh]
+	         performs sequential sweep using K-step induction
+	-P num : max partition size (0 = no partitioning) [default = 0]
+	-Q num : partition overlap (0 = no overlap) [default = 0]
+	-F num : number of time frames for induction (1=simple) [default = 1]
+	-C num : max number of conflicts at a node (0=inifinite) [default = 1000]
+	-L num : max number of levels to consider (0=all) [default = 0]
+	-N num : number of last POs treated as constraints (0=none) [default = 0]
+	-S num : additional simulation frames for c-examples (0=none) [default = 2]
+	-I num : iteration number to stop and output SR-model (-1=none) [default = -1]
+	-V num : min var num needed to recycle the SAT solver [default = 5000]
+	-M num : min call num needed to recycle the SAT solver [default = 250]
+	-N num : set last <num> POs to be constraints (use with -c) [default = 0]
+	-X num : the number of iterations of little or no improvement [default = 0]
+	-c     : toggle using explicit constraints [default = no]
+	-m     : toggle full merge if constraints are present [default = no]
+	-p     : toggle aligning polarity of SAT variables [default = no]
+	-l     : toggle doing latch correspondence [default = no]
+	-k     : toggle doing constant correspondence [default = no]
+	-o     : toggle doing 'PO correspondence' [default = no]
+	-d     : toggle dynamic addition of constraints [default = no]
+	-s     : toggle local simulation in the cone of influence [default = no]
+	-e     : toggle dumping disproved internal equivalences [default = no]
+	-f     : toggle dumping proved internal equivalences [default = no]
+	-q     : toggle quitting when PO is not a constant candidate [default = no]
+	-w     : toggle printout of flop equivalences [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: sim [-FWT num] [-AL file] [-nmvh]
+	          performs random simulation of the sequential miter
+	-F num  : the number of frames to simulate [default = 32]
+	-W num  : the number of words to simulate [default = 8]
+	-T num  : approximate runtime limit in seconds [default = 30]
+	-A file : text file name with user's patterns [default = random simulation]
+	          (patterns are listed, one per line, as sequences of 0s and 1s)
+	-L file : the log file name [default = no logging]
+	-n      : toggle new vs. old implementation [default = old]
+	-m      : toggle miter vs. any circuit [default = miter]
+	-v      : toggle printing verbose information [default = no]
+	-h      : print the command usage
+
+usage: sim3 [-FWBRSNTG num] [-L file] [-advzh]
+	         performs random simulation of the sequential miter
+	-F num : the number of frames to simulate [default = 20]
+	-W num : the number of words to simulate [default = 50]
+	-B num : the number of flops in one bin [default = 8]
+	-R num : the number of simulation rounds [default = 0]
+	-S num : the number of rounds before a restart [default = 0]
+	-N num : random number seed (1 <= num <= 1000) [default = 0]
+	-T num : approximate runtime limit in seconds [default = 0]
+	-G num : approximate runtime gap in seconds since the last CEX [default = 0]
+	-L file: the log file name [default = no logging]
+	-a     : toggle solving all outputs (do not stop when one is SAT) [default = no]
+	-d     : toggle dropping (replacing by 0) SAT outputs [default = no]
+	-i     : toggle changing init state to a last rare state [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-z     : toggle suppressing report about solved outputs [default = no]
+	-h     : print the command usage
+
+usage: ssweep [-PQNFL <num>] [-lrfetvh]
+	         performs sequential sweep using K-step induction
+	-P num : max partition size (0 = no partitioning) [default = 0]
+	-Q num : partition overlap (0 = no overlap) [default = 0]
+	-N num : number of time frames to use as the prefix [default = 0]
+	-F num : number of time frames for induction (1=simple) [default = 1]
+	-L num : max number of levels to consider (0=all) [default = 0]
+	-l     : toggle latch correspondence only [default = no]
+	-r     : toggle AIG rewriting [default = no]
+	-f     : toggle fraiging (combinational SAT sweeping) [default = no]
+	-e     : toggle writing implications as assertions [default = no]
+	-t     : toggle using one-hotness conditions [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: symfun [-N num] [-vh] <ones>
+	           generated a single-output symmetric function
+	-N <num> : prints truth tables of all N-var symmetric functions [default = not used]
+	-v       : toggle verbose output [default = no]
+	-h       : print the command usage
+	<ones>   : the string of N+1 zeros and ones, where N is the number of variables
+	           For example, to get 3-input NAND-gate, use "symfun 1000".
+	           To get 5-input majority gate, use "symfun 000111".
+
+usage: synch [-W <num>] [-vh] <file1> <file2>
+	         derives and applies synchronization sequence
+	-W num : the number of simulation words [default = 32]
+	-v     : toggle verbose output [default = yes]
+	-h     : print the command usage
+	file1  : (optional) the file with the first design
+	file2  : (optional) the file with the second design
+
+	         If no designs are given on the command line,
+	         assumes the current network has no initial state,
+	         derives synchronization sequence and applies it.
+
+	         If two designs are given on the command line
+	         assumes both of them have no initial state,
+	         derives sequences for both designs, synchorinizes
+	         them, and creates SEC miter comparing two designs.
+
+	         If only one design is given on the command line,
+	         considers the second design to be the current network,
+	         and derives SEC miter for them, as described above.
+
+usage: testscorr [-CS num] [-nfsvh] <file_in> <file_out>
+	             outputs the list of sequential equivalences into a file
+	             (if <file_in> is in BENCH, init state file should be the same directory)
+	-C num     : limit on the number of conflicts [default = 100]
+	-S num     : limit on refinement iterations (-1=no limit, 0=after BMC, etc) [default = -1]
+	-n         : toggle between "scorr" and "&scorr" [default = scorr]
+	-f         : toggle reporting only flop/flop equivs [default = no]
+	-s         : toggle reporting only flop/flop and flop/node equivs [default = no]
+	-v         : toggle verbose output [default = no]
+	-h         : print the command usage
+	<file_in>  : input file with design for sequential equivalence computation
+	<file_out> : output file with the list of pairs of equivalent signals
+
+usage: testssw [-PQNFL num] [-lrfetvh] <file>
+	         performs sequential sweep using K-step induction
+	         (outputs a file with a set of pairs of equivalent nodes)
+	-P num : max partition size (0 = no partitioning) [default = 0]
+	-Q num : partition overlap (0 = no overlap) [default = 0]
+	-N num : number of time frames to use as the prefix [default = 0]
+	-F num : number of time frames for induction (1=simple) [default = 1]
+	-L num : max number of levels to consider (0=all) [default = 0]
+	-l     : toggle latch correspondence only [default = no]
+	-r     : toggle AIG rewriting [default = no]
+	-f     : toggle fraiging (combinational SAT sweeping) [default = no]
+	-e     : toggle writing implications as assertions [default = no]
+	-t     : toggle using one-hotness conditions [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: undc [-ch]
+	        converts latches with DC init values into free PIs
+	-c    : toggles transforming CEX after "logic;undc;st;zero" [default = no]
+	-h    : print the command usage
+
+usage: unpermute [-h]
+	        restores inputs/outputs/flops before the last permutation
+	-h    : print the command usage
+
+usage: xsim [-F num] [-isvh]
+	         performs X-valued simulation of the AIG
+	-F num : the number of frames to simulate [default = 10]
+	-i     : toggle X-valued representation of inputs [default = no]
+	-s     : toggle X-valued representation of state [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: zero [-h]
+	        converts latches to have const-0 initial value
+	-h    : print the command usage
+
+   ----------------------------------------------------------------------
+
+Synthesis commands:
+ addbuffs         aigaug           b                balance         
+ cascade          cleanup          clp              collapse        
+ dsd              eliminate        exact            extract         
+ faultclasses     fx               fxch             glitch          
+ logicpush        lutcas           lutmin           lutpack         
+ merge            mfs              mfs2             mfs3            
+ mfse             multi            mux_struct       orchestrate     
+ powerdown        refactor         renode           resub           
+ resub_check      resub_core       resub_unate      rewrite         
+ runeco           rungen           runsat           satclp          
+ sparsify         speedup          st               strash          
+ sweep            testdec          testnpn          testtruth       
+ trace            varmin           xec             
+
+usage: addbuffs [-I num] [-drvh]
+	           adds buffers to create balanced CI/CO paths
+	-I <num> : the number of refinement iterations [default = 1000]
+	-d       : toggle using only CI-to-CO levelized order [default = no]
+	-r       : toggle using only CO-to-C1 levelized order [default = no]
+	-v       : toggle printing optimization summary [default = no]
+	-h       : print the command usage
+
+usage: aigaug [-s <num>] [-d <file>][-zZdsh]
+	           performs technology-independent AIG random synthesis (node level) for RTL augmentation
+	-z       : toggle using zero-cost replacements for rwr for aigaug [default = no]
+	-Z       : toggle using zero-cost replacements for ref for aigaug [default = no]
+	-d       : record random synthesis decision made during augmentation [required filename; e.g., test.csv]
+	-s       : set the random seed for random augmentation
+	-v       : toggle verbose printout [default = no]
+	-h       : print the command usage
+	Example       : read i10.aig;st;aigaug -s 1 -d test.csv;write i10_arg_1.aig;cec i10.aig i10_arg_1.aig
+
+usage: balance [-ldsxvh]
+	        transforms the current network into a well-balanced AIG
+	-l    : toggle minimizing the number of levels [default = yes]
+	-d    : toggle duplication of logic [default = no]
+	-s    : toggle duplication on the critical paths [default = no]
+	-x    : toggle balancing multi-input EXORs [default = no]
+	-v    : print verbose information [default = no]
+	-h    : print the command usage
+
+usage: balance [-ldsxvh]
+	        transforms the current network into a well-balanced AIG
+	-l    : toggle minimizing the number of levels [default = yes]
+	-d    : toggle duplication of logic [default = no]
+	-s    : toggle duplication on the critical paths [default = no]
+	-x    : toggle balancing multi-input EXORs [default = no]
+	-v    : print verbose information [default = no]
+	-h    : print the command usage
+
+usage: cascade [-K <num>] [-cvh]
+	           performs LUT cascade synthesis for the current network
+	-K <num> : the number of LUT inputs [default = 12]
+	-c       : check equivalence after synthesis [default = no]
+	-v       : toggle verbose printout [default = no]
+	-h       : print the command usage
+	           
+  A lookup-table cascade is a programmable architecture developed by
+  Professor Tsutomu Sasao (sasao@cse.kyutech.ac.jp) at Kyushu Institute
+  of Technology. This work received Takeda Techno-Entrepreneurship Award:
+  http://www.lsi-cad.com/sasao/photo/takeda.html
+
+usage: cleanup [-iovh]
+	        for logic networks, removes dangling combinatinal logic
+	        for AIGs, removes PIs w/o fanout and POs driven by const-0
+	-i    : toggles removing PIs without fanout [default = yes]
+	-o    : toggles removing POs with const-0 drivers [default = yes]
+	-v    : print verbose information [default = yes]
+	-h    : print the command usage
+
+usage: collapse [-B <num>] [-L file] [-rodxvh]
+	          collapses the network by constructing global BDDs
+	-B <num>: limit on live BDD nodes during collapsing [default = 1000000000]
+	-L file : the log file name [default = no logging]
+	-r      : toggles dynamic variable reordering [default = yes]
+	-o      : toggles reverse variable ordering [default = no]
+	-d      : toggles dual-rail collapsing mode [default = no]
+	-x      : toggles dumping file "order.txt" with variable order [default = no]
+	-v      : print verbose information [default = no]
+	-h      : print the command usage
+
+usage: collapse [-B <num>] [-L file] [-rodxvh]
+	          collapses the network by constructing global BDDs
+	-B <num>: limit on live BDD nodes during collapsing [default = 1000000000]
+	-L file : the log file name [default = no logging]
+	-r      : toggles dynamic variable reordering [default = yes]
+	-o      : toggles reverse variable ordering [default = no]
+	-d      : toggles dual-rail collapsing mode [default = no]
+	-x      : toggles dumping file "order.txt" with variable order [default = no]
+	-v      : print verbose information [default = no]
+	-h      : print the command usage
+
+usage: dsd [-grvpsh]
+	     decomposes the network using disjoint-support decomposition
+	-g     : toggle DSD of global and local functions [default = global]
+	-r     : toggle recursive DSD/MUX and simple DSD [default = simple DSD]
+	-v     : prints DSD statistics and runtime [default = no]
+	-p     : prints DSD structure to the standard output [default = no]
+	-s     : use short PI names when printing DSD structure [default = no]
+	-h     : print the command usage
+
+usage: eliminate [-VNI <num>] [-grsvh]
+	           traditional "eliminate -1", which collapses the node into its fanout
+	           if the node's variable appears in the fanout's factored form only once
+	-V <num> : the "value" parameter used by "eliminate" in SIS [default = -1]
+	-N <num> : the maximum node support after collapsing [default = 12]
+	-I <num> : the maximum number of iterations [default = 1]
+	-g       : toggle using greedy eliminate (without "value") [default = no]
+	-r       : use the reverse topological order [default = no]
+	-s       : toggle eliminating similar nodes [default = no]
+	-v       : print verbose information [default = no]
+	-h       : print the command usage
+
+usage: exact [-DSC <num>] [-A <list>] [-atvh] <truth1> <truth2> ...
+	           finds optimum networks using SAT-based exact synthesis for hex truth tables <truth1> <truth2> ...
+	-D <num>  : constrain maximum depth (if too low, algorithm may not terminate)
+	-A <list> : input arrival times (comma separated list)
+	-S <num>  : number of start gates in search [default = 1]
+	-C <num>  : the limit on the number of conflicts; turn off with 0 [default = 400000]
+	-a        : toggle create AIG [default = no]
+	-t        : run test suite
+	-v        : toggle verbose printout [default = no]
+	-h        : print the command usage
+	
+	            This command was contributed by Mathias Soeken from EPFL in July 2016.
+	            The author can be contacted as mathias.soeken at epfl.ch
+
+usage: extract [-K <num>] [-avh]
+	           extracts shared logic from multi-input gates
+	-K <num> : the minimum gate size to consider for extraction [default = 3]
+	-a       : toggle multi-input XOR vs multi-input AND [default = XOR]
+	-v       : toggle verbose printout [default = no]
+	-h       : print the command usage
+
+usage: faultclasses [-gcsvwh]
+	           computes equivalence classes of faults in the given mapped netlist;
+	           the fault list with faults in the format: <fault_id> <node_name> <fault_name>
+	           should be read by command "read_fins" before calling this command
+	-g       : toggle generating a fault list for the current mapped network [default = no]
+	-c       : toggle using only stuck-at faults in the generated fault list [default = no]
+	-s       : toggle detecting sequential equivalence classes [default = no]
+	-v       : toggle verbose printout during computation [default = no]
+	-w       : toggle printing of resulting fault equivalence classes [default = no]
+	-h       : print the command usage
+
+usage: fx [-SDNWMP <num>] [-sdzcnxvwh]
+	           performs unate fast extract on the current network
+	-S <num> : max number of single-cube divisors to consider [default = 20000]
+	-D <num> : max number of double-cube divisors to consider [default = 30000]
+	-N <num> : max number of divisors to extract during this run [default = 1000000]
+	-W <num> : lower bound on the weight of divisors to extract [default = 0]
+	-M <num> : upper bound on literal count of divisors to extract [default = 4]
+	-P <num> : skip "fx" if cube pair count exceeds this limit [default = 1000000000]
+	-s       : use only single-cube divisors [default = no]
+	-d       : use only double-cube divisors [default = no]
+	-z       : use zero-weight divisors [default = no]
+	-c       : use complement in the binary case [default = yes]
+	-n       : use new implementation of fast extract [default = yes]
+	-x       : use only canonical divisors (AND, XOR, MUX) [default = no]
+	-v       : print verbose information [default = no]
+	-w       : print additional information [default = no]
+	-h       : print the command usage
+
+usage: fxch [-N <num>] [-svwh]
+	           performs fast extract with cube hashing on the current network
+	-N <num> : max number of divisors to extract during this run [default = unused]
+	-v       : print verbose information [default = no]
+	-w       : print additional information [default = no]
+	-h       : print the command usage
+	
+	           This command was contributed by Bruno Schmitt from UFRGS in May 2016.
+	           The author can be contacted as boschmitt at inf.ufrgs.br
+
+usage: glitch [-NP <num>] [-vh]
+	           comparing glitching activity to switching activity
+	-N <num> : the number of random patterns to use (0 < num < 1000000) [default = 4000]
+	-P <num> : once in how many cycles an input changes its value [default = 8]
+	-v       : toggle printing optimization summary [default = yes]
+	-h       : print the command usage
+
+usage: logicpush [-K num] [-vh]
+	           performs logic pushing to reduce structural bias
+	-K <num> : the LUT size used in the mapping [default = 4]
+	-v       : toggle printing optimization summary [default = no]
+	-h       : print the command usage
+
+usage: lutcas [-K <num>] [-vh]
+	           derives single-rail LUT cascade for the primary output function
+	-K <num> : the number of LUT inputs [default = 6]
+	-v       : toggle verbose printout [default = no]
+	-h       : print the command usage
+
+usage: lutmin [-K <num>] [-rvh]
+	           perform FPGA mapping while minimizing the LUT count
+	           as described in the paper T. Sasao and A. Mishchenko:
+	           "On the number of LUTs to implement logic functions".
+	-K <num> : the LUT size to use for the mapping (2 <= num) [default = 4]
+	-r       : toggle using BDD variable reordering [default = yes]
+	-v       : toggle verbose printout [default = no]
+	-h       : print the command usage
+
+usage: lutpack [-NQSL <num>] [-szfovwh]
+	           performs "rewriting" for LUT network;
+	           determines LUT size as the max fanin count of a node;
+	           if the network is not LUT-mapped, packs it into 6-LUTs
+	           (there is another command for resynthesis after LUT mapping, "mfs2")
+	-N <num> : the max number of LUTs in the structure (2 <= num) [default = 4]
+	-Q <num> : the max number of LUTs not in MFFC (0 <= num) [default = 3]
+	-S <num> : the max number of LUT inputs shared (0 <= num <= 3) [default = 0]
+	-L <num> : max level increase after resynthesis (0 <= num) [default = 0]
+	-s       : toggle iteration till saturation [default = yes]
+	-z       : toggle zero-cost replacements [default = no]
+	-f       : toggle using only first node and first cut [default = no]
+	-o       : toggle using old implementation [default = no]
+	-v       : toggle verbose printout [default = no]
+	-w       : toggle detailed printout of decomposed functions [default = no]
+	-h       : print the command usage
+
+usage: merge [-NSDLF <num>] [-scwvh]
+	           creates pairs of topologically-related LUTs
+	-N <num> : the max LUT size for merging (1 < num) [default = 5]
+	-S <num> : the max total support size after merging (1 < num) [default = 5]
+	-D <num> : the max distance in terms of LUTs (0 < num) [default = 3]
+	-L <num> : the max difference in levels (0 <= num) [default = 2]
+	-F <num> : the max number of fanouts to stop traversal (0 < num) [default = 100]
+	-s       : toggle the use of nodes without support overlap [default = no]
+	-c       : toggle the use of TFI/TFO nodes as candidates [default = no]
+	-w       : toggle printing detailed stats for each node [default = no]
+	-v       : toggle printing optimization summary [default = yes]
+	-h       : print the command usage
+
+usage: mfs [-WFDMLC <num>] [-draestpgvh]
+	           performs don't-care-based optimization of logic networks
+	-W <num> : the number of levels in the TFO cone (0 <= num) [default = 2]
+	-F <num> : the max number of fanouts to skip (1 <= num) [default = 30]
+	-D <num> : the max depth nodes to try (0 = no limit) [default = 20]
+	-M <num> : the max node count of windows to consider (0 = no limit) [default = 300]
+	-L <num> : the max increase in node level after resynthesis (0 <= num) [default = 0]
+	-C <num> : the max number of conflicts in one SAT run (0 = no limit) [default = 5000]
+	-d       : toggle performing redundancy removal [default = no]
+	-r       : toggle resubstitution and dc-minimization [default = resub]
+	-a       : toggle minimizing area or area+edges [default = area+edges]
+	-e       : toggle high-effort resubstitution [default = no]
+	-s       : toggle evaluation of edge swapping [default = no]
+	-t       : toggle using artificial one-hotness conditions [default = no]
+	-p       : toggle power-aware optimization [default = no]
+	-g       : toggle using new SAT solver [default = no]
+	-v       : toggle printing optimization summary [default = no]
+	-w       : toggle printing detailed stats for each node [default = no]
+	-h       : print the command usage
+
+usage: mfs2 [-WFDMLCZNI <num>] [-daeijlvwh]
+	           performs don't-care-based optimization of logic networks
+	-W <num> : the number of levels in the TFO cone (0 <= num) [default = 2]
+	-F <num> : the max number of fanouts to skip (1 <= num) [default = 30]
+	-D <num> : the max depth nodes to try (0 = no limit) [default = 20]
+	-M <num> : the max node count of windows to consider (0 = no limit) [default = 300]
+	-L <num> : the max increase in node level after resynthesis (0 <= num) [default = 0]
+	-C <num> : the max number of conflicts in one SAT run (0 = no limit) [default = 5000]
+	-Z <num> : treat the first <num> logic nodes as fixed (0 = none) [default = 0]
+	-N <num> : the max number of nodes to try (0 = all) [default = 0]
+	-d       : toggle performing redundancy removal [default = no]
+	-a       : toggle minimizing area or area+edges [default = area+edges]
+	-e       : toggle high-effort resubstitution [default = no]
+	-i       : toggle using inductive don't-cares [default = no]
+	-j       : toggle using all flops when "-i" is enabled [default = no]
+	-I       : the number of additional frames inserted [default = 0]
+	-l       : toggle deriving don't-cares [default = no]
+	-v       : toggle printing optimization summary [default = no]
+	-w       : toggle printing detailed stats for each node [default = no]
+	-h       : print the command usage
+
+usage: mfs3 [-IOVFKLHRMCNPWDE <num>] [-armzespdlvwh]
+	           performs don't-care-based optimization of mapped networks
+	-I <num> : the number of levels in the TFI cone (1 <= num) [default = 100]
+	-O <num> : the number of levels in the TFO cone (0 <= num) [default = 100]
+	-V <num> : the number of levels in the TFI/TFO cone (1 <= num) [default = 100]
+	-F <num> : the max number of fanouts to skip (1 <= num) [default = 10]
+	-K <num> : the max number of variables (2 <= num <= 8 ) [default = 6]
+	-L <num> : the min size of max fanout-free cone (MFFC) (area-only) [default = 1]
+	-H <num> : the max size of max fanout-free cone (MFFC) (area-only) [default = 3]
+	-R <num> : the max number of decomposition rounds (1 <= num <= 4) [default = 1]
+	-M <num> : the max node count of windows to consider (0 = no limit) [default = 0]
+	-C <num> : the max number of conflicts in one SAT run (0 = no limit) [default = 0]
+	-N <num> : the max number of nodes to try (0 = all) [default = 0]
+	-P <num> : one particular node to try (0 = none) [default = 0]
+	-W <num> : size of timing window in percents (0 <= num <= 100) [default = 1]
+	-D <num> : size of critical-timing delay-delta (in picoseconds) [default = 0]
+	-E <num> : delay-area tradeoff (in picoseconds per area-unit) [default = 0]
+	-a       : toggle area minimization [default = no]
+	-r       : toggle using reverse topo order for area minimization [default = no]
+	-m       : toggle detecting multi-input AND/OR gates [default = no]
+	-z       : toggle zero-cost replacements [default = no]
+	-e       : toggle using more effort [default = no]
+	-s       : toggle using simulation [default = no]
+	-p       : toggle printing decompositions [default = no]
+	-d       : toggle printing delay profile statistics [default = no]
+	-l       : toggle printing library usage statistics [default = no]
+	-v       : toggle printing optimization summary [default = no]
+	-w       : toggle printing detailed stats for each node [default = no]
+	-h       : print the command usage
+
+usage: mfse [-IOWFLC <num>] [-advwh]
+	           performs don't-care-based optimization of logic networks
+	-I <num> : the number of levels in the TFI cone (2 <= num) [default = 3]
+	-O <num> : the number of levels in the TFO cone (0 <= num) [default = 2]
+	-W <num> : the max number of nodes in the window (1 <= num) [default = 100]
+	-F <num> : the max number of fanouts to skip (1 <= num) [default = 20]
+	-L <num> : the max increase in node level after resynthesis (0 <= num) [default = 0]
+	-C <num> : the max number of conflicts in one SAT run (0 = no limit) [default = 0]
+	-a       : toggle minimizing area [default = area]
+	-d       : toggle using Ashenhurst decomposition [default = no]
+	-v       : toggle printing optimization summary [default = no]
+	-w       : toggle printing detailed stats for each node [default = no]
+	-h       : print the command usage
+
+usage: multi [-TF <num>] [-msfch]
+	          transforms an AIG into a logic network by creating larger nodes
+	-F <num>: the maximum fanin size after renoding [default = 20]
+	-T <num>: the threshold for AIG node duplication [default = 1]
+	          (an AIG node is the root of a new node after renoding
+	          if this leads to duplication of no more than 1 AIG nodes,
+	          that is, if [(numFanouts(Node)-1) * size(MFFC(Node))] <= 1)
+	-m      : creates multi-input AND graph [default = yes]
+	-s      : creates a simple AIG (no renoding) [default = no]
+	-f      : creates a factor-cut network [default = no]
+	-c      : performs renoding to derive the CNF [default = no]
+	-h      : print the command usage
+
+usage: mux_struct [-vh]
+	        performs MUX restructuring of the current network
+	-v    : print verbose information [default = no]
+	-h    : print the command usage
+
+usage: orchestrate [-KNFZzlvwh]
+	           performs technology-independent AIG synthesis using orchestration method (currently orchestrating rw/rf/rs)
+	-K <num> : (resub)the max cut size (4 <= num <= 16) [default = 8]
+	-N <num> : (resub)the max number of nodes to add (0 <= num <= 3) [default = 1]
+	-F <num> : (resub)the number of fanout levels for ODC computation [default = 0]
+	-l       : (resub/rw/refactor)toggle preserving the number of levels [default = yes]
+	-z       : (rw)toggle using zero-cost replacements [default = yes]
+	-Z       : (refactor)toggle using zero-cost replacements [default = yes]
+	-v       : (resub/rw/refactor)toggle verbose printout [default = no]
+	-w       : (resub/rw/refactor)toggle detailed verbose printout [default = no]
+	-h       : print the command usage
+
+usage: powerdown [-PN <num>] [-vwh]
+	           transforms LUT-mapped network into an AIG with choices;
+	           the choices are added to power down the next round of mapping
+	-P <num> : switching propability delta defining power critical edges [default = 10%]
+	           (e.g. 5No such file or directoryeans hot wires switch with probability: 0.45 <= p <= 0.50 (max)
+	-N <num> : the max critical path degree for resynthesis (0 < num < 6) [default = 2]
+	-v       : toggle printing optimization summary [default = no]
+	-w       : toggle printing detailed stats for each node [default = no]
+	-h       : print the command usage
+
+usage: refactor [-NM <num>] [-lzvh]
+	           performs technology-independent refactoring of the AIG
+	-N <num> : the max support of the collapsed node [default = 10]
+	-M <num> : the min number of nodes saved after one step (0 <= num) [default = 1]
+	-l       : toggle preserving the number of levels [default = yes]
+	-z       : toggle using zero-cost replacements [default = no]
+	-v       : toggle verbose printout [default = no]
+	-h       : print the command usage
+
+usage: renode [-KCFA <num>] [-sbciav]
+	          transforms the AIG into a logic network with larger nodes
+	          while minimizing the number of FF literals of the node SOPs
+	-K <num>: the max cut size for renoding (2 < num < 16) [default = 8]
+	-C <num>: the max number of cuts used at a node (0 < num < 2^12) [default = 4]
+	-F <num>: the number of area flow recovery iterations (num >= 0) [default = 1]
+	-A <num>: the number of exact area recovery iterations (num >= 0) [default = 1]
+	-s      : toggles minimizing SOP cubes instead of FF lits [default = no]
+	-b      : toggles minimizing BDD nodes instead of FF lits [default = no]
+	-c      : toggles minimizing CNF clauses instead of FF lits [default = no]
+	-i      : toggles minimizing MV-SOP instead of FF lits [default = no]
+	-a      : toggles area-oriented mapping [default = no]
+	-v      : print verbose information [default = no]
+	-h      : print the command usage
+
+usage: resub [-KNMF <num>] [-lzvwh]
+	           performs technology-independent restructuring of the AIG
+	-K <num> : the max cut size (4 <= num <= 16) [default = 8]
+	-N <num> : the max number of nodes to add (0 <= num <= 3) [default = 1]
+	-M <num> : the min number of nodes saved after one step (0 <= num) [default = 1]
+	-F <num> : the number of fanout levels for ODC computation [default = 0]
+	-l       : toggle preserving the number of levels [default = yes]
+	-z       : toggle using zero-cost replacements [default = no]
+	-v       : toggle verbose printout [default = no]
+	-w       : toggle verbose printout of ODC computation [default = no]
+	-h       : print the command usage
+
+usage: resub_check [-vh] <file1> <file2>
+	           checks solution to a resub problem
+	-v       : toggle verbose printout [default = no]
+	<file1>  : resub problem file name
+	<file2>  : (optional) solution file name
+	-h       : print the command usage
+
+usage: resub_core [-IR <num>] [-svh] <file>
+	         solves one instance of the resub problem
+	-I num : the number of iterations [default = 1]
+	-R num : the number of rounds in each iteration [default = 1]
+	-s     : toggle saving the result in the input file [default = no]
+	-v     : toggle verbose printout [default = no]
+	-h     : print the command usage
+	<file> : resub problem file name
+
+usage: resub_unate [-LD <num>] [-svh] <file>
+	         solves one instance of the resub problem
+	-L num : the limit on the number of nodes [default = 16]
+	-D num : the maximum number of binate divisors to consider [default = 50]
+	-s     : toggle saving the result in the input file [default = no]
+	-v     : toggle verbose printout [default = no]
+	-h     : print the command usage
+	<file> : resub problem file name
+
+usage: rewrite [-lzvwh]
+	         performs technology-independent rewriting of the AIG
+	-l     : toggle preserving the number of levels [default = yes]
+	-z     : toggle using zero-cost replacements [default = no]
+	-v     : toggle verbose printout [default = no]
+	-w     : toggle printout subgraph statistics [default = no]
+	-h     : print the command usage
+
+usage: runeco [-T num] [-criuvwh] <implementation> <specification> <weights>
+	         performs computation of patch functions during ECO,
+	         as described in the following paper: A. Q. Dao et al
+	         "Efficient computation of ECO patch functions", Proc. DAC'18
+	         https://people.eecs.berkeley.edu/~alanmi/publications/2018/dac18_eco.pdf
+	         (currently only applicable to benchmarks from 2017 ICCAD CAD competition
+	         http://cad-contest-2017.el.cycu.edu.tw/Problem_A/default.html as follows:
+	         "runeco unit1/F.v unit1/G.v unit1/weight.txt; cec -n out.v unit1/G.v")
+	-T num : the timeout in seconds [default = 0]
+	-c     : toggle checking that the problem has a solution [default = no]
+	-r     : toggle using random permutation of support variables [default = no]
+	-i     : toggle using primary inputs as support variables [default = no]
+	-u     : toggle using unit weights [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing more verbose information [default = no]
+	-h     : print the command usage
+
+usage: rungen [-vh] <file1> <file2>
+	         experimental command
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: runsat [-I num] [-kwvh] <cnf_file>
+	         performs randomized iterations of SAT solving
+	-I num : the number of iterations [default = 10]
+	-k     : toggle using Kissat (binary name "kissat") [default = no]
+	-w     : toggle using WalkSat (binary name "walk") [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: satclp [-CLZ num] [-crsvh]
+	         performs SAT based collapsing
+	-C num : the limit on the SOP size of one output [default = 0]
+	-L num : the limit on the number of conflicts in one SAT call [default = 1000000]
+	-Z num : the limit on the cost of the largest output [default = 20000000]
+	-c     : toggles using canonical ISOP computation [default = no]
+	-r     : toggles using reverse veriable ordering [default = no]
+	-s     : toggles shared CNF computation (non-canonical only) [default = no]
+	-v     : toggles printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: sparsify [-N num] [-vh]
+	           creates incompletely-specified function
+	-N <num> : the percentage of on-set and off-set minterms (1 <= num <= 100) [default = 10]
+	-v       : prints verbose information [default = no]
+	-h       : print the command usage
+
+usage: speedup [-PN <num>] [-lvwh]
+	           transforms LUT-mapped network into an AIG with choices;
+	           the choices are added to speedup the next round of mapping
+	-P <num> : delay delta defining critical path for library model [default = 5%]
+	-N <num> : the max critical path degree for resynthesis (0 < num < 6) [default = 2]
+	-l       : toggle using unit- or LUT-library-delay model [default = unit]
+	-v       : toggle printing optimization summary [default = no]
+	-w       : toggle printing detailed stats for each node [default = no]
+	-h       : print the command usage
+
+usage: strash [-acrih]
+	        transforms combinational logic into an AIG
+	-a    : toggles between using all nodes and DFS nodes [default = DFS]
+	-c    : toggles cleanup to remove the dagling AIG nodes [default = all]
+	-r    : toggles using the record of AIG subgraphs [default = no]
+	-i    : toggles complementing the POs of the AIG [default = no]
+	-h    : print the command usage
+
+usage: strash [-acrih]
+	        transforms combinational logic into an AIG
+	-a    : toggles between using all nodes and DFS nodes [default = DFS]
+	-c    : toggles cleanup to remove the dagling AIG nodes [default = all]
+	-r    : toggles using the record of AIG subgraphs [default = no]
+	-i    : toggles complementing the POs of the AIG [default = no]
+	-h    : print the command usage
+
+usage: sweep [-svh]
+	        removes dangling nodes; propagates constant, buffers, inverters
+	-s    : toggle sweeping buffers/inverters only [default = no]
+	-v    : toggle printing verbose information [default = no]
+	-h    : print the command usage
+
+usage: testdec [-AN <num>] [-vh] <file>
+	           testbench for Boolean decomposition algorithms
+	-A <num> : decomposition algorithm [default = 0]
+	               0: none (reading and writing the file)
+	               1: algebraic factoring applied to ISOP
+	               2: bi-decomposition with cofactoring
+	               3: disjoint-support decomposition with cofactoring
+	               4: updated disjoint-support decomposition with cofactoring
+	               5: enumerating decomposable variable sets
+	               6: disjoint-support decomposition with cofactoring and boolean difference analysis
+	                  from V. Callegaro, F. S. Marranghello, M. G. A. Martins, R. P. Ribas and A. I. Reis,
+	                  "Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis," ICCD'15.
+	-N <num> : the number of support variables (binary files only) [default = unused]
+	-v       : toggle verbose printout [default = no]
+	-h       : print the command usage
+	<file>   : a text file with truth tables in hexadecimal, listed one per line,
+	           or a binary file with an array of truth tables (in this case,
+	           -N <num> is required to determine how many functions are stored)
+
+usage: testnpn [-AN <num>] [-dbvh] <file>
+	           testbench for computing (semi-)canonical forms
+	           of completely-specified Boolean functions up to 16 variables
+	-A <num> : semi-caninical form computation algorithm [default = 0]
+	               0: uniqifying truth tables
+	               1: exact NPN canonical form by brute-force enumeration
+	               2: semi-canonical form by counting 1s in cofactors
+	               3: Jake's hybrid semi-canonical form (fast)
+	               4: Jake's hybrid semi-canonical form (high-effort)
+	               5: new fast hybrid semi-canonical form
+	               6: new phase canonical form
+	               7: new hierarchical matching
+	               8: hierarchical matching            by XueGong Zhou at Fudan University, Shanghai
+	               9: adjustable algorithm (heuristic) by XueGong Zhou at Fudan University, Shanghai
+	              10: adjustable algorithm (exact)     by XueGong Zhou at Fudan University, Shanghai
+	              11: new cost-aware exact algorithm   by XueGong Zhou at Fudan University, Shanghai
+	              12: new fast hybrid semi-canonical form (permutation only)
+	-N <num> : the number of support variables (binary files only) [default = unused]
+	-d       : toggle dumping resulting functions into a file [default = no]
+	-b       : toggle dumping in binary format [default = no]
+	-v       : toggle verbose printout [default = no]
+	-h       : print the command usage
+	<file>   : a text file with truth tables in hexadecimal, listed one per line,
+	           or a binary file with an array of truth tables (in this case,
+	           -N <num> is required to determine how many functions are stored)
+
+usage: testtruth [-vh] <file>
+	           printing truth table stats
+	-v       : toggle verbose printout [default = no]
+	-h       : print the command usage
+
+usage: trace [-lvh]
+	           performs delay trace of LUT-mapped network
+	-l       : toggle using unit- or LUT-library-delay model [default = unit]
+	-v       : toggle printing optimization summary [default = no]
+	-h       : print the command usage
+
+usage: varmin [-MN <num>] [-ocvh]
+	           performs support minimization
+	-M <num> : the number of ones in the combination [default = 4]
+	-N <num> : the number of variables in the problem [default = 20]
+	-o       : toggle computing reduced difference matrix [default = no]
+	-c       : toggle verifying the final result [default = no]
+	-v       : toggle verbose printout [default = no]
+	-h       : print the command usage
+
+usage: xec [-fvh] <file1> <file2>
+	           combinational equivalence checking with x-values
+	-f       : toggle using experimental feature [default = no]
+	-v       : toggle printing verbose information [default = no]
+	-h       : print the command usage
+
+   ----------------------------------------------------------------------
+
+Two-level commands:
+ |gen             |merge           |ps              |read           
+ |test            |write          
+
+usage: |gen [-IOPS num] [-spvh]
+	         generate random or specialized SOP
+	-I num : the number of inputs [default = 8]
+	-O num : the number of outputs [default = 1]
+	-P num : the number of products [default = 20]
+	-S num : ramdom seed (0 <= num <= 1000) [default = 0]
+	-s     : toggle generating sorter as a PLA file [default = no]
+	-p     : toggle generating prime detector [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: |merge [-mvh]
+	         performs distance-1 merge using cube hashing
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: |ps [-madvh]
+	         prints statistics
+	-m     : toggle printing multipliers [default = no]
+	-a     : toggle printing adders [default = no]
+	-d     : toggle printing distrubition [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: |read [-vh] <file_name>
+	         reads the SOP from a PLA file
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: |test [-N num] [-vh]
+	         experiments with SOPs
+	-N num : the number of variables [default = 4]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: |write [-vh]
+	         writes the SOP into a PLA file
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+   ----------------------------------------------------------------------
+
+Various commands:
+ addpi            aig              andpos           append          
+ autotuner        backup           bb2wb            bdd             
+ bidec            bottommost       capo             care_set        
+ cof              comb             cone             cover           
+ cubes            cut              demiter          dframes         
+ double           dropsat          espresso         exdc_free       
+ exdc_get         exdc_set         expand           ext_seq_dcs     
+ frames           gen              genat            genfsm          
+ gentf            inter            load             load_plugin     
+ logic            minisat          minisimp         miter           
+ miter2           move_names       muxes            mvsis           
+ node             nodedup          npnload          npnsave         
+ order            orpos            outdec           putontop        
+ qreach           qrel             qvar             range           
+ reach            removepo         reorder          restore         
+ save             send_aig         send_status      senseinput      
+ short_names      sis              sop              splitsop        
+ starter          swappos          test             testcolor       
+ topand           topmost          trim             wrap            
+ zeropo          
+
+usage: addpi [-h]
+	         if the network has no PIs, add one dummy PI
+	-h     : print the command usage
+
+usage: aig [-h]
+	         converts node functions to AIG
+	-h     : print the command usage
+
+usage: andpos [-h]
+	        creates single-output miter by ANDing the POs of the current network
+	-h    : print the command usage
+
+usage: append [-h] <file>
+	         appends a combinational network on top of the current network
+	-h     : print the command usage
+	<file> : file name with the second network
+
+usage: autotuner [-N num] [-C file] [-F file] [-vh]
+	         performs autotuning
+	-N num : the number of concurrent jobs including the controller [default = 3]
+	-C cmd : configuration file with settings for autotuning
+	-F cmd : list of AIGER files to be used for autotuning
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: backup [-h]
+	        backs up the current network
+	-h    : print the command usage
+
+usage: bb2wb [-svh] <file_in> <file_out>
+	             replaces black boxes by white boxes with AND functions
+	             (file names should have standard extensions, e.g. "blif")
+	-s         : toggle using sequential white boxes [default = no]
+	-v         : toggle verbose output [default = no]
+	-h         : print the command usage
+	<file_in>  : input file with design containing black boxes
+	<file_out> : output file with design containing white boxes
+
+usage: bdd [-rsh]
+	         converts node functions to BDD
+	-r     : toggles enabling dynamic variable reordering [default = yes]
+	-s     : toggles constructing BDDs directly from SOPs [default = no]
+	-h     : print the command usage
+
+usage: bidec [-vh]
+	         applies bi-decomposition to local functions of the nodes
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+
+usage: bottommost [-N num] [-h]
+	         replaces the current network by several of its bottommost levels
+	-N num : max number of levels [default = 10]
+	-h     : print the command usage
+	name   : the node name
+
+Usage: capo [-h] <com>
+         peforms placement of the current network using Capo
+         a Capo binary should be present in the same directory
+         (if plotting, the Gnuplot binary should also be present)
+   -h  : print the command usage
+ <com> : a Capo command
+         Example 1: capo
+                    (performs placement with default options)
+         Example 2: capo -AR <aspec_ratio> -WS <whitespace_percentage> -save
+                    (specifies the aspect ratio [default = 1.0] and
+                    the whitespace percentage [0%; 100%) [default = 15%])
+         Example 3: capo -plot <base_fileName>
+                    (produces <base_fileName.plt> and visualize it using Gnuplot)
+         Example 4: capo -help
+                    (prints the default usage message of the Capo binary)
+         Please refer to the Capo webpage for additional information:
+         http://vlsicad.eecs.umich.edu/BK/PDtools/
+
+usage: care_set [-h] <file>
+	         sets the network from file as a care for the current network
+	-h     : print the command usage
+	<file> : file with the new care network
+
+usage: cof [-h] <node> <const>
+	          replaces one node in a logic network by constant 0 or 1
+	-h      : print the command usage
+	<node>  : the node to replace
+	<const> : the constant to replace the node with
+	name    : the node name
+
+usage: comb [-L <num>] [-lh]
+	           converts comb network into seq, and vice versa
+	-L <num> : number of latches to add to comb network (0 = do not add) [default = 0]
+	-l       : toggle converting latches to PIs/POs or removing them [default = convert]
+	-h       : print the command usage
+
+usage: cone [-OR num] [-amsh] <name>
+	         replaces the current network by one logic cone
+	-a     : toggle keeping all CIs or structral support only [default = structural]
+	-m     : toggle keeping only MFFC or complete TFI cone [default = TFI cone]
+	-s     : toggle comb or sequential cone (works with "-O num") [default = comb]
+	-h     : print the command usage
+	-O num : (optional) the 0-based number of the CO to extract
+	-R num : (optional) the number of outputs to extract
+	name   : (optional) the name of the node to extract
+
+usage: cover [-IP num] [-sxvh]
+	         decomposition into a network of SOP/ESOP PLAs
+	         (this command is known to have bugs)
+	-I num : maximum number of inputs [default = 8]
+	-P num : maximum number of products [default = 8]
+	-s     : toggle the use of SOPs [default = yes]
+	-x     : toggle the use of ESOPs [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: cubes [-xh]
+	        converts the current network into a network derived by creating
+	        a separate node for each product and sum in the local SOPs
+	-x    : toggle using XOR instead of OR [default = no]
+	-h    : print the command usage
+
+usage: cut [-K num] [-M num] [-tfdcovamjsvh]
+	         computes k-feasible cuts for the AIG
+	-K num : max number of leaves (3 <= num <= 12) [default = 5]
+	-M num : max number of cuts stored at a node [default = 1000]
+	-t     : toggle truth table computation [default = yes]
+	-f     : toggle filtering of duplicated/dominated [default = yes]
+	-d     : toggle dropping when fanouts are done [default = no]
+	-x     : toggle computing only DAG cuts [default = yes]
+	-y     : toggle computing only tree cuts [default = no]
+	-g     : toggle computing only global cuts [default = no]
+	-l     : toggle computing only local cuts [default = no]
+	-z     : toggle fancy computations [default = no]
+	-a     : toggle recording cut functions [default = yes]
+	-m     : toggle delay-oriented FPGA mapping [default = no]
+	-j     : toggle removing fanouts due to XOR/MUX [default = no]
+	-s     : toggle creating library of 6-var functions [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: demiter [-dvh]
+	        splits sequential miter into two circuits
+	-d    : expects a dual-output miter (without XORs) [default = no]
+	-v    : toggles outputting verbose information [default = yes]
+	-h    : print the command usage
+
+usage: dframes [-NF <num>] [-ivh]
+	         unrolls the network with simplification
+	-N num : the number of frames to use as prefix [default = 5]
+	-F num : the number of frames to unroll [default = 5]
+	-i     : toggles initializing the first frame [default = no]
+	-v     : toggles outputting verbose information [default = no]
+	-h     : print the command usage
+
+usage: double [-vh]
+	         puts together two parallel copies of the current network
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: dropsat [-sh]
+	         replaces satisfiable POs by constant 0 and cleans up the AIG
+	-s     : toggles skipping sequential sweep [default = no]
+	-v     : toggles verbose output [default = no]
+	-h     : print the command usage
+
+The espresso command is currently disabled.
+
+usage: exdc_free [-h]
+	         frees the EXDC network of the current network
+	-h     : print the command usage
+
+usage: exdc_get [-h]
+	         replaces the current network by the EXDC of the current network
+	-h     : print the command usage
+
+usage: exdc_set [-h] <file>
+	         sets the network from file as EXDC for the current network
+	-h     : print the command usage
+	<file> : file with the new EXDC network
+
+usage: expand [-vh] <file>
+	        expands cubes against the offset
+	-v    : toggle verbose output [default = no]
+	-h    : print the command usage
+	file  : (optional) representation of on-set plus dc-set
+
+usage: ext_seq_dcs [-vh]
+	         create EXDC network using unreachable states
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+
+usage: frames [-F <num>] [-ivh]
+	           unrolls the network for a number of time frames
+	-F <num> : the number of frames to unroll [default = 5]
+	-i       : toggles initializing the first frame [default = no]
+	-v       : toggles outputting verbose information [default = no]
+	-h       : print the command usage
+
+usage: gen [-NAKL num] [-atsembfnrgvh] <file>
+	         generates simple circuits
+	-N num : the number of variables [default = 8]
+	-A num : the number of arguments (for adder tree) [default = 8]
+	-K num : the LUT size (to be used with switch -f) [default = -1]
+	-L num : the LUT count (to be used with switch -f) [default = -1]
+	-a     : generate ripple-carry adder [default = no]
+	-t     : generate an adder tree [default = no]
+	-s     : generate a sorter [default = no]
+	-e     : generate a mesh [default = no]
+	-m     : generate a multiplier [default = no]
+	-b     : generate a signed Booth multiplier [default = no]
+	-f     : generate a LUT FPGA structure [default = no]
+	-g     : generate a graph structure [default = no]
+	-n     : generate one-hotness conditions [default = no]
+	-r     : generate random single-output function [default = no]
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+	<file> : output file name
+
+usage: genat [-dvh] <n1> <n2> ... <nn>
+	         generates the adder tree
+	-d     : toggle building dual tree [default = no]
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+	<nums> : input counts by rank
+
+usage: genfsm [-IOSLPQ num] [-vh] <file>
+	         generates random FSM in KISS format
+	-I num : the number of input variables [default = 30]
+	-O num : the number of output variables [default = 1]
+	-S num : the number of state variables [default = 20]
+	-L num : the number of lines (product terms) [default = 100]
+	-P num : percentage propability of a variable present in the input cube [default = 10]
+	-Q num : percentage propability of a variable present in the output cube [default = 100]
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+	<file> : output file name
+
+usage: gentf [-WK num] [-A str] [-vh] <w1> <w2> ... <wn> <thresh>
+	         generates threshold function
+	-W num : the bit-width [default = none]
+	-K num : the LUT size [default = none]
+	-A str : the circuit architecture [default = none]
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+	<nums> : weights and threshold
+
+usage: inter [-rvh] <onset.blif> <offset.blif>
+	         derives interpolant of two networks representing onset and offset;
+	-r     : toggle computing interpolant as a relation [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+	         
+	         Comments:
+	         
+	         The networks given on the command line should have the same CIs/COs.
+	         If only one network is given on the command line, this network
+	         is assumed to be the offset, while the current network is the onset.
+	         If no network is given on the command line, the current network is
+	         assumed to be the onset and its complement is taken to be the offset.
+	         The resulting interpolant is stored as the current network.
+	         To verify that the interpolant agrees with the onset and the offset,
+	         save it in file "inter.blif" and run the following:
+	         (a) "miter -i <onset.blif> <inter.blif>; iprove"
+	         (b) "miter -i <inter.blif> <offset_inv.blif>; iprove"
+	         where <offset_inv.blif> is the network derived by complementing the
+	         outputs of <offset.blif>: "r <offset.blif>; st -i; w <offset_inv.blif>"
+
+usage: load [-h]
+	        loads mapped network previously saved by "save"
+	-h    : print the command usage
+
+usage: load_plugin [-pvh] <plugin_dir\binary_name> <section_name>
+	        loads external binary as a plugin
+	-p    : toggle searching the command in PATH [default = no].
+	-v    : enable verbose output [default = no].
+	-h    : print the command usage
+
+usage: logic [-h]
+	        transforms an AIG into a logic network with SOPs
+	-h    : print the command usage
+
+This command is currently disabled.
+
+This command is currently disabled.
+
+usage: miter [-P <num>] [-cimtnh] <file1> <file2>
+	           computes the miter of the two circuits
+	-P <num> : output partition size [default = unused]
+	-c       : toggles deriving combinational miter (latches as POs) [default = no]
+	-i       : toggles deriving implication miter (file1 => file2) [default = no]
+	-m       : toggles creating multi-output miter [default = no]
+	-t       : toggle XORing pair-wise POs of the miter [default = no]
+	-n       : toggle ignoring names when matching CIs/COs [default = no]
+	-h       : print the command usage
+	file1    : (optional) the file with the first network
+	file2    : (optional) the file with the second network
+	           if no files are given, uses the current network and its spec
+	           if one file is given, uses the current network and the file
+
+	           Please note that, when used without "-n", this command tries to match
+	           primary inputs by name and, to achieve this, it will order them alphabetically,
+	           which results in incorrect QBF miters and confusing counter-examples.
+
+usage: miter2 [-h] <file>
+	         derives specialized miter
+	-h     : print the command usage
+	<file> : file name with node names
+
+usage: move_names [-h] <file>
+	         moves PI/PO/latch names from the other network
+	-h     : print the command usage
+	<file> : file with network that has required names
+
+usage: muxes [-B num] [-gah]
+	          converts the current network into a network derived by
+	          replacing all nodes by DAGs isomorphic to the local BDDs
+	-B <num>: limit on live BDD nodes during collapsing [default = 1000000]
+	-g      : toggle visualizing the global BDDs of primary outputs [default = no].
+	-a      : toggle using ADDs instead of BDDs [default = no].
+	-h      : print the command usage
+
+Usage: mvsis [-h] <com>
+         invokes MVSIS command for the current ABC network
+         (the executable of MVSIS should be in the same directory)
+   -h  : print the command usage
+ <com> : a MVSIS command (or a semicolon-separated list of commands in quotes)
+         Example 1: mvsis fraig_sweep
+         Example 2: mvsis "ps; fxu; ps"
+         Example 3: mvsis source mvsis.rugged
+
+usage: node [-h] <name>
+	         replaces the current network by the network composed of one node
+	-h     : print the command usage
+	name   : the node name
+
+usage: nodedup [-Nvh]
+	         duplicates internal nodes with high fanout
+	-N num : the number of fanouts to start duplication [default = 30]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: npnload <filename>
+	         loads previously saved 6-input function library from file
+	-h     : print the command usage
+
+usage: npnsave <filename>
+	         saves current 6-input function library into file
+	-h     : print the command usage
+
+usage: order [-rvh] <file>
+	         computes a good static CI variable order
+	-r     : toggle reverse ordering [default = no]
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+	<file> : (optional) file with the given variable order
+
+usage: orpos [-rxh]
+	        creates single-output miter by ORing the POs of the current network
+	-r    : performs the reverse transform (OR decomposition) [default = no]
+	-x    : toggles combining the PO using XOR [default = no]
+	-h    : print the command usage
+
+usage: outdec [-Lvh]
+	         performs prime decomposition of the first output
+	-L num : the number of literals in the primes [default = 1]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: putontop [-h] <file>
+	         connects PIs of network in <file> to POs of current network
+	-h     : print the command usage
+	<file> : file name with the second network
+	       : (given several files, all networks are stacked on top of each other)
+
+usage: qreach [-I num] [-vh]
+	         computes unreachable states using AIG-based quantification
+	         assumes that the current network is a transition relation
+	         assumes that the initial state is composed of all zeros
+	-I num : the number of image computations to perform [default = 256]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: qrel [-qvh]
+	         computes transition relation of the sequential network
+	-q     : perform quantification of inputs [default = yes]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: qvar [-I num] [-uvh]
+	         quantifies one variable using the AIG
+	-I num : the zero-based index of a variable to quantify [default = 0]
+	-u     : toggle universal quantification [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: range [-h]
+	         computes the range of output values as one node
+	-h     : print the command usage
+
+usage: reach [-TBF num] [-L file] [-proyvh]
+	         verifies sequential miter using BDD-based reachability
+	-T num : approximate time limit in seconds (0=infinite) [default = 0]
+	-B num : max number of nodes in the intermediate BDDs [default = 50000]
+	-F num : max number of reachability iterations [default = 1000]
+	-L file: the log file name [default = no logging]
+	-p     : enable partitioned image computation [default = yes]
+	-r     : enable dynamic BDD variable reordering [default = yes]
+	-o     : toggles BDD variable reordering during image computation [default = yes]
+	-y     : skip checking property outputs [default = no]
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+
+usage: removepo [-N <num>] [-zh]
+	           remove PO with number <num> if it is const0
+	-N <num> : the zero-based index of the PO to remove [default = -1]
+	-z       : toggle removing const1 instead of const0 [default = const0]
+	-h       : print the command usage
+
+usage: reorder [-vh]
+	         reorders local functions of the nodes using sifting
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+
+usage: restore [-h]
+	        restores the current network
+	-h    : print the command usage
+
+usage: save [-ah]
+	        compares and possibly saves network with mapping
+	-a    : toggle using area as the primary metric [default = no]
+	-h    : print the command usage
+
+usage: send_aig -a
+	         sends current AIG to the bridge
+	-a     : toggle sending AIG from &-space [default = yes]
+	-b     : toggle sending netlist tagged as "abstraction". [default = no]
+	-h     : print the command usage
+
+usage: send_status
+	         sends current status to the bridge
+	-h     : print the command usage
+
+usage: senseinput [-C num] [-vh]
+	         computes sensitivity of POs to PIs under constraint
+	         constraint should be represented as the last PO
+	-C num : the max number of conflicts at a node [default = 1000]
+	-v     : toggle printing verbose information [default = yes]
+	-h     : print the command usage
+
+usage: short_names [-kh]
+	         replaces PI/PO/latch names by short char strings
+	-k     : toggle keeping PI/PO names unchanged [default = no]
+	-h     : print the command usage
+
+Usage: sis [-h] <com>
+         invokes SIS command for the current ABC network
+         (the executable of SIS should be in the same directory)
+   -h  : print the command usage
+ <com> : a SIS command (or a semicolon-separated list of commands in quotes)
+         Example 1: sis eliminate 0
+         Example 2: sis "ps; rd; fx; ps"
+         Example 3: sis source script.rugged
+
+usage: sop [-C num] [-sdnh]
+	         converts node functions to SOP
+	-C num : the limit on the number of cubes at a node [default = 1000000]
+	-s     : toggles cube sort when converting from BDDs [default = yes]
+	-d     : toggles using only positive polarity [default = no]
+	-n     : toggles using only negative polarity [default = no]
+	-h     : print the command usage
+
+usage: splitsop [-N num] [-vh]
+	         splits nodes whose SOP size is larger than the given one
+	-N num : the maximum number of cubes after splitting [default = 100]
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+
+usage: starter [-P num] [-C cmd] [-vh] <file>
+	         runs command lines listed in <file> concurrently on <num> CPUs
+	-P num : the number of concurrent jobs including the controller [default = 3]
+	-C cmd : (optional) ABC command line to execute on benchmarks in <file>
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+	<file> : file name with ABC command lines (or benchmark names, if <cmd> is given)
+
+usage: swappos [-N <num>] [-h]
+	           swap the 0-th PO with the <num>-th PO
+	-N <num> : the zero-based index of the PO to swap [default = -1]
+	-h       : print the command usage
+
+usage: test [-CKDNM] [-aovwh] <file_name>
+	         testbench for new procedures
+	-C num : the max number of cuts [default = 1]
+	-K num : the max number of leaves [default = 4]
+	-D num : the max number of divisors [default = 2]
+	-N num : the max number of node inputs [default = 3]
+	-M num : the max number of ones in the vector [default = 0]
+	-a     : toggle using new algorithm [default = no]
+	-o     : toggle using new ordering [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing very verbose information [default = no]
+	-h     : print the command usage
+
+Background         [1;40m  [1;41m  [1;42m  [1;43m  [1;44m  [1;45m  [1;46m  [1;47m
+Foreground [0m       Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Foreground [1m       Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Foreground [0;30m    Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Foreground [1;30m    Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Foreground [0;31m    Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Foreground [1;31m    Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Foreground [0;32m    Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Foreground [1;32m    Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Foreground [0;33m    Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Foreground [1;33m    Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Foreground [0;34m    Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Foreground [1;34m    Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Foreground [0;35m    Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Foreground [1;35m    Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Foreground [0;36m    Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Foreground [1;36m    Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Foreground [0;37m    Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Foreground [1;37m    Hi      Hi      Hi      Hi      Hi      Hi      Hi      Hi  
+Underlined
+Blinking  
+Inverted  
+Concealed 
+
+usage: topand [-h]
+	         performs AND-decomposition of single-output combinational miter
+	-h     : print the command usage
+	name   : the node name
+
+usage: topmost [-N num] [-h]
+	         replaces the current network by several of its topmost levels
+	-N num : max number of levels [default = 10]
+	-h     : print the command usage
+	name   : the node name
+
+usage: trim [-h]
+	         removes POs fed by constants and PIs w/o fanout
+	-h     : print the command usage
+
+usage: wrap [-h] <file> <file2>
+	           wrapping lines
+	<file>   : input text file
+	<file2>  : output text file
+
+usage: zeropo [-N <num>] [-soh]
+	           replaces the PO driver by constant 0
+	-N <num> : the zero-based index of the PO to replace [default = -1]
+	-s       : performs comb sweep after removimg a PO [default = yes]
+	-o       : toggles using const 1 instead of const 0 [default = no]
+	-h       : print the command usage
+
+   ----------------------------------------------------------------------
+
+Verification commands:
+ &kissat          &sat3            &satoko          absec           
+ blockpo          bm               bm2              bmc             
+ bmc2             bmc3             cec              cexcut          
+ cexload          cexmerge         cexsave          constr          
+ dcec             debug            dprove           dsat            
+ dsec             dualrail         eco              enlarge         
+ fold             fold2            ind              indcut          
+ int              iprove           iso              match           
+ pdr              prove            psat             reconcile       
+ sat              satoko           saucy3           simsec          
+ tempor           testcex          unfold           unfold2         
+ xsat            
+
+usage: &kissat [-CT num] [-sucvh] [-A string] <file.cnf>
+	             run SAT solver Kissat, by Armin Biere (https://github.com/arminbiere/kissat)
+	-C num     : limit on the number of conflicts [default = 0]
+	-T num     : runtime limit in seconds [default = 0]
+	-s         : expect a satisfiable problem [default = no]
+	-u         : expect an unsatisfiable problem [default = no]
+	-c         : prints satisfying assignment if satisfiable [default = no]
+	-v         : prints verbose information [default = no]
+	-A num     : string containing additional command-line args for the Kissat binary [default = unused]
+	             (in particular, <&kissat -A "--help"> prints all command-line args of Kissat)
+	<file.cnf> : (optional) CNF file to solve
+	-h         : print the command usage
+
+usage: &sat3 [-C num] [-sivh]
+	-C num : limit on the number of conflicts [default = 0]
+	-s     : split multi-output miter into individual outputs [default = no]
+	-i     : split multi-output miter and solve incrementally [default = no]
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+
+usage: &satoko [-C num] [-sivh] <file.cnf>
+	             run Satoko by Bruno Schmitt
+	-C num     : limit on the number of conflicts [default = 0]
+	-s         : split multi-output miter into individual outputs [default = no]
+	-i         : split multi-output miter and solve incrementally [default = no]
+	-v         : prints verbose information [default = no]
+	<file.cnf> : (optional) CNF file to solve
+	-h         : print the command usage
+
+usage: absec [-F num] [-mv] <file1> <file2>
+	         performs SEC by applying CEC to several timeframes
+	-F num : the total number of timeframes to use [default = 2]
+	-m     : toggles miter vs. two networks [default = miter]
+	-v     : toggles verbose output [default = no]
+	file1  : (optional) the file with the first network
+	file2  : (optional) the file with the second network
+	         if no files are given, uses the current network and its spec
+	         if one file is given, uses the current network and the file
+
+usage: blockpo [-F num] [-fvh]
+	         forces the miter outputs to be "true" in the first F frames
+	-F num : the number of time frames [default = 0]
+	-v     : toggle printing optimization summary [default = no]
+	-h     : print the command usage
+
+usage: bm [-P] <file1> <file2>
+	        performs Boolean matching (P-equivalence & PP-equivalence)
+	        for equivalent circuits, I/O matches are printed in IOmatch.txt
+	-P    : performs P-equivalnce checking
+	        default is PP-equivalence checking (when -P is not provided)
+	-h    : print the command usage
+	file1 : the file with the first network
+	file2 : the file with the second network
+	        
+	        This command was contributed by Hadi Katebi from U Michigan.
+	        The paper describing the method: H. Katebi and I. L. Markov.
+	        "Large-scale Boolean matching". Proc. DATE 2010. 
+	        http://www.eecs.umich.edu/~imarkov/pubs/conf/date10-match.pdf
+
+usage: bm2  <file1> <file2>
+	        performs Boolean matching (PP-equivalence)
+	        for equivalent circuits, permutation that maps one circuit
+	        to another is printed to standard output (PIs and POs of the
+	        first network have prefix "N1:", while PIs and POs of the
+	        second network have prefix "N2:")
+	-h    : print the command usage
+	file1 : the file with the first network
+	file2 : the file with the second network
+	        
+	        This command was contributed by Hadi Katebi from U Michigan.
+	        The paper describing the method: H. Katebi, K. Sakallah and
+	        I. L. Markov.
+	        "Generalized Boolean Symmetries Through Nested Partition
+	        Refinement". Proc. ICCAD 2013. 
+
+usage: bmc [-FNC num] [-L file] [-rcsvh]
+	         performs bounded model checking with static unrolling
+	-F num : the number of time frames [default = 20]
+	-N num : the max number of nodes in the frames [default = 100000]
+	-C num : the max number of conflicts at a node [default = 0]
+	-L file: the log file name [default = no logging]
+	-r     : toggle the use of rewriting [default = no]
+	-s     : toggle using Satoko by Bruno Schmitt [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: bmc2 [-SFTCGD num] [-L file] [-usvh]
+	         performs bounded model checking with dynamic unrolling
+	-S num : the starting time frame [default = 0]
+	-F num : the max number of time frames (0 = unused) [default = 0]
+	-T num : approximate runtime limit in seconds [default = 0]
+	-C num : the max number of conflicts at a node [default = 0]
+	-G num : the max number of conflicts globally [default = 0]
+	-D num : the delta in the number of nodes [default = 2000]
+	-L file: the log file name [default = no logging]
+	-u     : toggle performing structural OR-decomposition [default = no]
+	-s     : toggle using Satoko by Bruno Schmitt [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: bmc3 [-SFTHGCDJIPQR num] [-LW file] [-axdursgvzh]
+	         performs bounded model checking with dynamic unrolling
+	-S num : the starting time frame [default = 0]
+	-F num : the max number of time frames (0 = unused) [default = 0]
+	-T num : runtime limit, in seconds [default = 0]
+	-H num : runtime limit per output, in milliseconds (with "-a") [default = 0]
+	-G num : runtime gap since the last CEX, in seconds [default = 0]
+	-C num : max conflicts at an output [default = 0]
+	-D num : max conflicts after jumping (0 = infinity) [default = 0]
+	-J num : the number of timeframes to jump (0 = not used) [default = 0]
+	-I num : the number of PIs to abstract [default = 0]
+	-P num : the max number of learned clauses to keep (0=unused) [default = 10000]
+	-Q num : delta value for learned clause removal [default = 2000]
+	-R num : percentage to keep for learned clause removal [default = 80]
+	-L file: the log file name [default = no logging]
+	-W file: the log file name with per-output details [default = no logging]
+	-a     : solve all outputs (do not stop when one is SAT) [default = no]
+	-x     : toggle storing CEXes when solving all outputs [default = no]
+	-d     : toggle dropping (replacing by 0) SAT outputs [default = no]
+	-u     : toggle performing structural OR-decomposition [default = not]
+	-r     : toggle disabling periodic restarts [default = no]
+	-s     : toggle using Satoko by Bruno Schmitt [default = no]
+	-g     : toggle using Glucose 3.0 by Gilles Audemard and Laurent Simon [default = no]
+	-v     : toggle verbose output [default = no]
+	-z     : toggle suppressing report about solved outputs [default = no]
+	-h     : print the command usage
+
+usage: cec [-T num] [-C num] [-I num] [-P num] [-psnvh] <file1> <file2>
+	         performs combinational equivalence checking
+	-T num : approximate runtime limit in seconds [default = 20]
+	-C num : limit on the number of conflicts [default = 10000]
+	-I num : limit on the number of clause inspections [default = 0]
+	-P num : partition size for multi-output networks [default = unused]
+	-p     : toggle automatic partitioning [default = no]
+	-s     : toggle "SAT only" and "FRAIG + SAT" [default = FRAIG + SAT]
+	-n     : toggle how CIs/COs are matched (by name or by order) [default = by name]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+	file1  : (optional) the file with the first network
+	file2  : (optional) the file with the second network
+	         if no files are given, uses the current network and its spec
+	         if one file is given, uses the current network and the file
+
+usage: cexcut [-FG num] [-cnmvh]
+	         creates logic for bad states using the current CEX
+	-F num : 0-based number of the starting frame [default = 0]
+	-G num : 0-based number of the ending frame [default = 1000000000]
+	-c     : toggle outputting unate combinational circuit [default = no]
+	-n     : toggle generating only one bad state [default = no]
+	-m     : toggle generating bad states for all frames after G [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: cexload [-h]
+	        loads the current CEX from the internal storage
+	-h    : print the command usage
+
+usage: cexmerge [-FG num] [-vh]
+	         merges the current CEX into the saved one
+	         and sets the resulting CEX as the saved one
+	-F num : 0-based number of the starting frame [default = 0]
+	-G num : 0-based number of the ending frame [default = 1000000000]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: cexsave [-h]
+	        saves the current CEX into the internal storage
+	-h    : print the command usage
+
+usage: constr [-FCPN num] [-rpisavh]
+	         a toolkit for constraint manipulation
+	         if constraints are absent, detect them functionally
+	         if constraints are present, profiles them using random simulation
+	         (constraints fail when any of them becomes 1 in any timeframe)
+	-F num : the max number of timeframes to consider [default = 1]
+	-C num : the max number of conflicts in SAT solving [default = 1000]
+	-P num : the max number of propagations in SAT solving [default = 1000]
+	-N num : manually set the last <num> POs to be constraints [default = -1]
+	-r     : manually remove the constraints, converting them to POs [default = no]
+	-p     : remove constraints instead of converting them to POs [default = no]
+	-i     : toggle inverting already defined constraints [default = no]
+	-s     : toggle using structural detection methods [default = no]
+	-a     : toggle fast implication detection [default = yes]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: dcec [-T num] [-C num] [-I num] [-mpsvh] <file1> <file2>
+	         performs combinational equivalence checking
+	-T num : approximate runtime limit in seconds [default = 20]
+	-C num : limit on the number of conflicts [default = 10000]
+	-I num : limit on the number of clause inspections [default = 0]
+	-m     : toggle working on two networks or a miter [default = two networks]
+	-p     : toggle automatic partitioning [default = no]
+	-s     : toggle "SAT only" (miter) or "FRAIG + SAT" [default = FRAIG + SAT]
+	-v     : toggles verbose output [default = no]
+	-h     : print the command usage
+	file1  : (optional) the file with the first network
+	file2  : (optional) the file with the second network
+	         if no files are given, uses the current network and its spec
+	         if one file is given, uses the current network and the file
+
+usage: debug [-h]
+	        performs automated debugging of the given procedure
+	-h    : print the command usage
+
+usage: dprove [-AEFCGDVBRT num] [-L file] [-cbarmfijoupvwh]
+	         performs SEC on the sequential miter
+	-A num : the limit on the depth of BMC [default = 20]
+	-E num : the conflict limit during BMC [default = 2000]
+	-F num : the limit on the depth of induction [default = 4]
+	-C num : the conflict limit at a node during induction [default = 1000]
+	-G num : the global conflict limit during induction [default = 5000000]
+	-D num : the conflict limit during interpolation [default = 10000]
+	-V num : the flop count limit for BDD-based reachablity [default = 150]
+	-B num : the BDD size limit in BDD-based reachablity [default = 50000]
+	-R num : the max number of reachability iterations [default = 1000000]
+	-T num : the timeout for property directed reachability [default = 60]
+	-L file: the log file name [default = no logging]
+	-c     : toggles using CEC before attempting SEC [default = yes]
+	-b     : toggles using BMC before attempting SEC [default = yes]
+	-a     : toggles the use of phase abstraction [default = no]
+	-r     : toggles forward retiming at the beginning [default = yes]
+	-m     : toggles min-register retiming [default = yes]
+	-f     : toggles the internal use of fraiging [default = yes]
+	-i     : toggles the use of induction [default = yes]
+	-j     : toggles the use of interpolation [default = yes]
+	-k     : toggles applying interpolation to each output [default = no]
+	-o     : toggles using BDD variable reordering during image computation [default = yes]
+	-u     : toggles reading back unsolved reduced sequential miter [default = no]
+	-p     : toggles trying property directed reachability in the end [default = yes]
+	-v     : toggles verbose output [default = no]
+	-w     : toggles additional verbose output [default = no]
+	-h     : print the command usage
+	Command "dprove" can also be used for sequential synthesis (dprove -brjopu)
+
+usage: dsat [-CILDE num] [-pansvh]
+	         solves the combinational miter using SAT solver MiniSat-1.14
+	         derives CNF from the current network and leaves it unchanged
+	-C num : limit on the number of conflicts [default = 0]
+	-I num : limit on the number of inspections [default = 0]
+	-L num : starting value for learned clause removal [default = 0]
+	-D num : delta value for learned clause removal [default = 0]
+	-E num : ratio percentage for learned clause removal [default = 0]
+	-p     : align polarity of SAT variables [default = no]
+	-a     : toggle ANDing/ORing of miter outputs [default = ORing]
+	-n     : toggle using new solver [default = no]
+	-s     : enable silent computation (no reporting) [default = no]
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+
+usage: dsec [-F num] [-T num] [-armfncvwh] <file1> <file2>
+	         performs inductive sequential equivalence checking
+	-F num : the limit on the depth of induction [default = 4]
+	-T num : the approximate runtime limit (in seconds) [default = 0]
+	-a     : toggles the use of phase abstraction [default = no]
+	-r     : toggles forward retiming at the beginning [default = yes]
+	-m     : toggles min-register retiming [default = yes]
+	-f     : toggles the internal use of fraiging [default = yes]
+	-n     : toggles how CIs/COs are matched (by name or by order) [default = by name]
+	-c     : toggles performing internal netlist check [default = yes]
+	-v     : toggles verbose output [default = no]
+	-w     : toggles additional verbose output [default = no]
+	-h     : print the command usage
+	file1  : (optional) the file with the first network
+	file2  : (optional) the file with the second network
+	         if no files are given, uses the current network and its spec
+	         if one file is given, uses the current network and the file
+
+usage: dualrail [-I num] [-txfczovh]
+	         transforms the current AIG into a dual-rail miter
+	         expressing the property "at least one PO has ternary value"
+	         (to compute an initialization sequence, use switches "-tfc")
+	-I num : the number of first PIs interpreted as ternary [default = 0]
+	-t     : toggle ternary flop init values for all flops [default = const0 init values]
+	-x     : toggle ternary flop init values for DC-valued flops [default = const0 init values]
+	-f     : toggle mitering flops instead of POs [default = POs]
+	-c     : toggle complementing the miter output [default = no]
+	-z     : toggle checking PO==0 instead of PO==X [default = no]
+	-o     : toggle checking PO==1 instead of PO==X [default = no]
+	-v     : toggle printing optimization summary [default = no]
+	-h     : print the command usage
+
+usage: eco [-h]
+	        performs experimental ECO computation
+	-h    : print the command usage
+
+usage: enlarge [-F <num>] [-vh]
+	           performs structural K-step target enlargement
+	-F <num> : the number of timeframes to unroll (<num> > 0) [default = 5]
+	-v       : toggle printing verbose information [default = no]
+	-h       : print the command usage
+
+usage: fold [-cvh]
+	         folds constraints represented as separate outputs
+	         (constraints fail when any of them becomes 1 in any timeframe)
+	-c     : toggle complementing constraints while folding [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-s     : toggle performing sequential cleanup [default = yes]
+	-h     : print the command usage
+
+usage: fold [-cvh]
+	         folds constraints represented as separate outputs
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: ind [-FCT num] [-uaxvwh]
+	         runs the inductive case of the K-step induction
+	-F num : the max number of timeframes [default = 0]
+	-C num : the max number of conflicts by SAT solver [default = 0]
+	-T num : the limit on runtime per output in seconds [default = 0]
+	-u     : toggle adding uniqueness constraints on demand [default = no]
+	-a     : toggle adding uniqueness constraints always [default = no]
+	-x     : toggle returning CEX to induction for the top frame [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing additional verbose information [default = no]
+	-h     : print the command usage
+
+usage: indcut [-FPCMLNB num] [-sbrtvh]
+	         K-step induction strengthened with cut properties
+	-F num : number of time frames for induction (1=simple) [default = 1]
+	-P num : number of time frames in the prefix (0=no prefix) [default = 0]
+	-C num : the max number of clauses to use for strengthening [default = 5000]
+	-M num : the cut size (2 <= M <= 12) [default = 4]
+	-L num : the max number of levels for cut computation [default = 8]
+	-N num : the max number of cuts to compute at a node [default = 16]
+	-B num : the max number of invariant batches to try [default = 1]
+	-s     : toggle increment cut size in each batch [default = no]
+	-b     : toggle enabling BMC check [default = yes]
+	-r     : toggle enabling register clauses [default = yes]
+	-t     : toggle proving target / computing don't-cares [default = yes]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: int [-CFTK num] [-LI file] [-irtpomcgbqkdvh]
+	         uses interpolation to prove the property
+	-C num : the limit on conflicts for one SAT run [default = 0]
+	-F num : the limit on number of frames to unroll [default = 0]
+	-T num : the limit on runtime per output in seconds [default = 0]
+	-K num : the number of steps in inductive checking [default = 1]
+	         (K = 1 works in all cases; K > 1 works without -t and -b)
+	-L file: the log file name [default = no logging]
+	-I file: the file name for dumping interpolant [default = "invar.aig"]
+	-i     : toggle dumping interpolant/invariant into a file [default = no]
+	-r     : toggle rewriting of the unrolled timeframes [default = no]
+	-t     : toggle adding transition into the initial state [default = no]
+	-p     : toggle using original Pudlak's interpolation procedure [default = no]
+	-o     : toggle using optimized Pudlak's interpolation procedure [default = no]
+	-m     : toggle using MiniSat-1.14p (now, Windows-only) [default = no]
+	-c     : toggle using inductive containment check [default = yes]
+	-g     : toggle using bias for global variables using SAT [default = no]
+	-b     : toggle using backward interpolation (works with -t) [default = no]
+	-q     : toggle using property in two last timeframes [default = no]
+	-k     : toggle solving each output separately [default = no]
+	-d     : toggle dropping (replacing by 0) SAT outputs (with -k is used) [default = no]
+	-v     : toggle verbose output [default = no]
+	-h     : print the command usage
+
+usage: iprove [-NCFGMI num] [-L file] [-rfbvh]
+	         performs CEC using a new method
+	-N num : max number of iterations [default = 6]
+	-C num : max starting number of conflicts in mitering [default = 5000]
+	-F num : max starting number of conflicts in fraiging [default = 2]
+	-G num : multiplicative coefficient for fraiging [default = 8]
+	-M num : max last-gasp number of conflicts in mitering [default = 0]
+	-I num : max number of clause inspections in all SAT calls [default = 0]
+	-L file: the log file name [default = no logging]
+	-r     : toggle the use of rewriting [default = yes]
+	-f     : toggle the use of FRAIGing [default = yes]
+	-b     : toggle the use of BDDs [default = no]
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+
+usage: iso [-vh]
+	         removes POs with isomorphic sequential COI
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: match [-D num] [-mv] <file1> <file2>
+	         detects structural similarity using simulation
+	         replaces the current network by the miter of differences
+	-D num : the distance for extending differences [default = 0]
+	-m     : toggles miter vs. two networks [default = two networks]
+	-v     : toggles verbose output [default = yes]
+	file1  : (optional) the file with the first network
+	file2  : (optional) the file with the second network
+	         if no files are given, uses the current network and its spec
+	         if one file is given, uses the current network and the file
+
+usage: pdr [-MFCDQTHGS <num>] [-LI <file>] [-X <prefix>] [-axrmuyfqipdegjonctkvwzh]
+	         model checking using property directed reachability (aka IC3)
+	         pioneered by Aaron R. Bradley (http://theory.stanford.edu/~arbrad/)
+	         with improvements by Niklas Een (http://een.se/niklas/)
+	-M num : limit on unused vars to trigger SAT solver recycling [default = 300]
+	-F num : limit on timeframes explored to stop computation [default = 10000]
+	-C num : limit on conflicts in one SAT call (0 = no limit) [default = 0]
+	-D num : limit on conflicts during ind-generalization (0 = no limit) [default = 0]
+	-Q num : limit on proof obligations before a restart (0 = no limit) [default = 0]
+	-T num : runtime limit, in seconds (0 = no limit) [default = 0]
+	-H num : runtime limit per output, in milliseconds (with "-a") [default = 0]
+	-G num : runtime gap since the last CEX (0 = no limit) [default = 0]
+	-S num : * value to seed the SAT solver with [default = 91648253]
+	-L file: the log file name [default = no logging]
+	-I file: the invariant file name [default = default name]
+	-X pref: when solving all outputs, store CEXes immediately as <pref>*.aiw [default = disabled]
+	-a     : toggle solving all outputs even if one of them is SAT [default = no]
+	-l     : toggle anytime schedule when solving all outputs [default = no]
+	-x     : toggle storing CEXes when solving all outputs [default = no]
+	-r     : toggle using more effort in generalization [default = no]
+	-m     : toggle using monolythic CNF computation [default = no]
+	-u     : toggle updated X-valued simulation [default = no]
+	-y     : toggle using structural flop priorities [default = no]
+	-f     : toggle ordering flops by cost before generalization [default = no]
+	-q     : toggle creating only shortest counter-examples [default = no]
+	-i     : toggle clause pushing from an intermediate timeframe [default = no]
+	-p     : toggle reusing proof-obligations in the last timeframe [default = no]
+	-d     : toggle dumping invariant (valid if init state is all-0) [default = no]
+	-e     : toggle using only support variables in the invariant [default = yes]
+	-g     : toggle skipping expensive generalization step [default = no]
+	-j     : toggle using simplified generalization step [default = no]
+	-o     : toggle using property output as inductive hypothesis [default = yes]
+	-n     : * toggle skipping 'down' in generalization [default = yes]
+	-c     : * toggle handling CTGs in 'down' [default = no]
+	-t     : toggle using abstraction [default = no]
+	-k     : toggle using simplified refinement [default = no]
+	-v     : toggle printing optimization summary [default = no]
+	-w     : toggle printing detailed stats default = no]
+	-z     : toggle suppressing report about solved outputs [default = no]
+	-h     : print the command usage
+
+	* Implementation of switches -S, -n, and -c is contributed by Zyad Hassan.
+	  The theory and experiments supporting this work can be found in the following paper:
+	  Zyad Hassan, Aaron R. Bradley, Fabio Somenzi, "Better Generalization in IC3", FMCAD 2013.
+	  (http://www.cs.utexas.edu/users/hunt/FMCAD/FMCAD13/papers/85-Better-Generalization-IC3.pdf)
+
+usage: prove [-NCFGLI num] [-rfbvh]
+	         solves combinational miter by rewriting, FRAIGing, and SAT
+	         replaces the current network by the cone modified by rewriting
+	         (there is also newer CEC command "iprove")
+	-N num : max number of iterations [default = 6]
+	-C num : max starting number of conflicts in mitering [default = 5000]
+	-F num : max starting number of conflicts in fraiging [default = 2]
+	-G num : multiplicative coefficient for fraiging [default = 8]
+	-L num : max last-gasp number of conflicts in mitering [default = 0]
+	-I num : max number of clause inspections in all SAT calls [default = 0]
+	-r     : toggle the use of rewriting [default = yes]
+	-f     : toggle the use of FRAIGing [default = yes]
+	-b     : toggle the use of BDDs [default = no]
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+
+usage: psat [-APC num] [-psvh]
+	         solves the combinational miter using partitioning
+	         (derives CNF from the current network and leave it unchanged)
+	         for multi-output miters, tries to prove that the AND of POs is always 0
+	         (if POs should be ORed instead of ANDed, use command "orpos")
+	-A num : partitioning algorithm [default = 0]
+	         0 : no partitioning
+	         1 : partitioning by level
+	         2 : DFS post-order
+	         3 : DFS pre-order
+	         4 : bit-slicing
+	         partitions are ordered by level (high level first)
+	-P num : limit on the partition size [default = 10000]
+	-C num : limit on the number of conflicts [default = 1000000]
+	-p     : align polarity of SAT variables [default = yes]
+	-s     : apply logic synthesis to each partition [default = no]
+	-v     : prints verbose information [default = yes]
+	-h     : print the command usage
+
+usage: reconcile [-h] <fileOrigin> <fileReparam>
+	        reconciles current CEX with <fileOrigin>
+	        More specifically:
+	        (i) assumes that <fileReparam> is an AIG derived by input
+	        reparametrization of <fileOrigin> without seq synthesis;
+	        (ii) assumes that current CEX is valid for <fileReparam>;
+	        (iii) derives new CEX for <fileOrigin> and sets this CEX
+	        and <fileOrigin> to be current CEX and current network
+	<fileOrigin>   : file name with the original AIG
+	<fileReparam>  : file name with the reparametrized AIG
+	        (if both file names are not given on the command line,
+	        original/reparam AIG has to be in the main-space/&-space)
+	-h    : print the command usage
+
+usage: sat [-C num] [-I num] [-vh]
+	         solves the combinational miter using SAT solver MiniSat-1.14
+	         derives CNF from the current network and leave it unchanged
+	         (there is also a newer SAT solving command "dsat")
+	-C num : limit on the number of conflicts [default = 0]
+	-I num : limit on the number of inspections [default = 0]
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+
+usage: satoko [-CPDEFGHIJKLMNOQRS num] [-hv]<file>.cnf
+	-C num : limit on the number of conflicts [default = 0]
+	-P num : limit on the number of propagations [default = 0]
+
+	Constants used for restart heuristic:
+	-D num : Constant value used by restart heuristics in forcing restarts [default = 0.800000]
+	-E num : Constant value used by restart heuristics in  blocking restarts [default = 1.400000]
+	-F num : Lower bound n.of conflicts for start blocking restarts [default = 10000]
+	-G num : Size of the moving avarege queue for LBD (force restart) [default = 50]
+	-H num : Size of the moving avarege queue for Trail size (block restart) [default = 5000]
+
+	Constants used for clause database reduction heuristic:
+	-I num : N.of conflicts before first clause databese reduction [default = 2000]
+	-J num : Increment to reduce [default = 300]
+	-K num : Special increment to reduce [default = 1000]
+	-L num : Protecs clauses from deletion for one turn if its LBD is lower [default = 30]
+	-M num : Percentage of learned clauses to remove [default = 50]
+	-N num : Max percentage of garbage in clause database [default = 30]
+
+	Constants used for binary resolution (clause minimization):
+	-O num : Max clause size for binary resolution [default = 30]
+	-Q num : Min clause LBD for binary resolution [default = 6]
+
+	Constants used for branching (VSIDS heuristic):
+	-R num : Clause activity decay factor (when using float clause activity) [default = 0.000000]
+	-S num : Variable activity decay factor [default = 0.950000]
+
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+
+usage: saucy3 [-O <name>] [-F <file>] [-iosqvh]
+
+	            computes functional symmetries of the network
+	            prints symmetry generators to the standard output
+	-O <name> : (optional) compute symmetries only for output given by name
+	            only inputs in the output cone are permuted
+	            (special case) name=all, compute symmetries for each
+	            output, but only one output at a time
+	            [default = compute symmetries by permuting all I/Os]
+	-F <file> : print symmetry generators to file [default = stdout]
+	-i        : permute just the inputs (fix the outputs) [default = no]
+	-o        : permute just the outputs (fix the inputs) [default = no]
+	-s        : only look for swaps of inputs [default = no]
+	-q        : quiet (do not print symmetry generators) [default = no]
+	-v        : verbose (print the search tree) [default = no]
+	-h        : print the command usage
+	            
+	            This command was contributed by Hadi Katebi from U Michigan.
+	            The paper describing the method: H. Katebi, K. Sakallah and
+	            I. L. Markov.
+	            "Generalized Boolean Symmetries Through Nested Partition
+	            Refinement". Proc. ICCAD 2013. 
+	            Saucy webpage: http://vlsicad.eecs.umich.edu/BK/SAUCY/
+
+usage: simsec [-FD num] [-mcyv] <file1> <file2>
+	         performs SEC using structural similarity
+	-F num : the limit on the depth of induction [default = 1]
+	-D num : the distance for extending islands [default = 0]
+	-m     : toggles miter vs. two networks [default = miter]
+	-c     : uses partial vs. full signal correspondence [default = partial]
+	-y     : dumps speculatively reduced miter of the classes [default = no]
+	-v     : toggles verbose output [default = yes]
+	file1  : (optional) the file with the first network
+	file2  : (optional) the file with the second network
+	         if no files are given, uses the current network and its spec
+	         if one file is given, uses the current network and the file
+
+usage: tempor [-FTC <num>] [-bscvwh]
+	           performs temporal decomposition
+	-F <num> : init logic timeframe count (0 = use leading length) [default = 0]
+	-T <num> : runtime limit in seconds for BMC (0=unused) [default = 300]
+	-C <num> : max number of SAT conflicts in BMC (0=unused) [default = 100000]
+	-b       : toggle running BMC2 on the init frames [default = yes]
+	-s       : toggle using transient signals [default = no]
+	-c       : update the current CEX derived for a new AIG after "tempor"
+	           to match the current AIG (the one before "tempor") [default = no]
+	-v       : toggle printing verbose output [default = no]
+	-w       : toggle printing ternary state space [default = no]
+	-h       : print the command usage
+
+usage: testcex [-O num] [-ah]
+	         tests the current cex against the current AIG or the &-AIG
+	-O num : the number of real POs in the PO list [default = 0]
+	-a     : toggle checking the current AIG or the &-AIG [default = &-AIG]
+	-h     : print the command usage
+
+usage: unfold [-FCP num] [-savh]
+	         unfold hidden constraints as separate outputs
+	-F num : the max number of timeframes to consider [default = 1]
+	-C num : the max number of conflicts in SAT solving [default = 1000]
+	-P num : the max number of constraint propagations [default = 1000]
+	-s     : toggle detecting structural constraints [default = no]
+	-a     : toggle fast implication detection [default = yes]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: unfold2 [-FCP num] [-savh]
+	         unfold hidden constraints as separate outputs
+	-C num : the max number of conflicts in SAT solving [default = 1000]
+	-P num : the max number of constraint propagations [default = 1000]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: xsat [-CILDE num] [-hv]<file>.cnf
+	         solves the combinational miter using SAT solver MiniSat-1.14
+	         derives CNF from the current network and leaves it unchanged
+	-C num : limit on the number of conflicts [default = 0]
+	-I num : limit on the number of inspections [default = 0]
+	-L num : starting value for learned clause removal [default = 0]
+	-D num : delta value for learned clause removal [default = 0]
+	-E num : ratio percentage for learned clause removal [default = 0]
+	-v     : prints verbose information [default = no]
+	-h     : print the command usage
+
+   ----------------------------------------------------------------------
+
+Word level commands:
+ %abs             %abs2            %blast           %blastmem       
+ %collapse        %cone            %graft           %hierarchy      
+ %memabs          %memabs2         %pdra            %print          
+ %profile         %ps              %read            %retime         
+ %short_names     %show            %test            %write          
+ %yosys           inv_check        inv_get          inv_min         
+ inv_print        inv_ps           inv_put         
+
+usage: %abs [-AMXFIL num] [-dxvwh]
+	         abstraction for word-level networks
+	-A num : minimum bit-width of an adder/subtractor to abstract [default = 1000000000]
+	-M num : minimum bit-width of a multiplier to abstract [default = 1000000000]
+	-X num : minimum bit-width of a MUX operator to abstract [default = 1000000000]
+	-F num : minimum bit-width of a flip-flop to abstract [default = 1000000000]
+	-I num : maximum number of CEGAR iterations [default = 1000]
+	-L num : maximum number of each type of signals [default = 1000000000]
+	-d     : toggle using another way of creating abstractions [default = no]
+	-x     : toggle XORing outputs of word-level miter [default = yes]
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing verbose PDR output [default = no]
+	-h     : print the command usage
+
+usage: %abs2 [-AMXFI num] [-xvwh]
+	         abstraction for word-level networks
+	-A num : minimum bit-width of an adder/subtractor to abstract [default = 1000000000]
+	-M num : minimum bit-width of a multiplier to abstract [default = 1000000000]
+	-X num : minimum bit-width of a MUX operator to abstract [default = 1000000000]
+	-F num : minimum bit-width of a flip-flop to abstract [default = 1000000000]
+	-I num : maximum number of CEGAR iterations [default = 1000]
+	-x     : toggle XORing outputs of word-level miter [default = yes]
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing verbose PDR output [default = no]
+	-h     : print the command usage
+
+usage: %blast [-ORAM num] [-combqaydestrnizvh]
+	         performs bit-blasting of the word-level design
+	-O num : zero-based index of the first word-level PO to bit-blast [default = -1]
+	-R num : the total number of word-level POs to bit-blast [default = 2]
+	-A num : blast adders smaller than this (0 = unused) [default = 0]
+	-M num : blast multipliers smaller than this (0 = unused) [default = 0]
+	-c     : toggle using AIG w/o const propagation and strashing [default = no]
+	-o     : toggle using additional POs on the word-level boundaries [default = no]
+	-m     : toggle creating boxes for all multipliers in the design [default = no]
+	-b     : toggle generating radix-4 Booth multipliers [default = no]
+	-q     : toggle generating non-restoring square root and divider [default = no]
+	-a     : toggle generating carry-look-ahead adder [default = no]
+	-y     : toggle creating different divide-by-0 condition [default = no]
+	-d     : toggle creating dual-output multi-output miter [default = no]
+	-e     : toggle creating miter with output word bits combined [default = no]
+	-s     : toggle creating decoded MUXes [default = no]
+	-t     : toggle creating regular multi-output miter [default = no]
+	-r     : toggle using interleaved variable ordering [default = no]
+	-n     : toggle dumping signal names into a text file [default = no]
+	-i     : toggle to print input names after blasting [default = no]
+	-z     : toggle saving flop names after blasting [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: %blastmem [-vh]
+	         performs blasting of memory read/write ports
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: %collapse [-T <module>] [-crvh] <file_name>
+	         collapse hierarchical design into an AIG
+	-T     : specify the top module of the design [default = none]
+	-c     : toggle complementing miter outputs after collapsing [default = no]
+	-r     : toggle bit order reversal in the word-level IO [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: %cone [-OR num] [-isvh]
+	         extracts logic cone of one or more word-level outputs
+	-O num : zero-based index of the first word-level output to extract [default = -1]
+	-R num : total number of word-level outputs to extract [default = 1]
+	-i     : toggle using support composed of all primary inputs [default = no]
+	-s     : toggle performing extracting sequential cones [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: %graft [-ivh] <module1_name> <module2_name>
+	         replace instances of module1 by those of module2
+	-i     : toggle using inverse grafting [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: %hierarchy [-vh] <module_name>
+	         marks the module whose instances may later be treated as black boxes
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: %memabs [-I num] [-dwvh]
+	         memory abstraction for word-level networks
+	-I num : maximum number of CEGAR iterations [default = 1000]
+	-d     : toggle dumping abstraction as an AIG [default = no]
+	-w     : toggle printing verbose PDR output [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: %memabs2 [-F num] [-vh]
+	         memory abstraction for word-level networks
+	-F num : the number of timeframes [default = 0]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: %pdra [-AMXFIL num] [-abrcdilpqmxstuvwh]
+	         abstraction for word-level networks
+	-A num : minimum bit-width of an adder/subtractor to abstract [default = 1000000000]
+	-M num : minimum bit-width of a multiplier to abstract [default = 1000000000]
+	-X num : minimum bit-width of a MUX operator to abstract [default = 1000000000]
+	-F num : minimum bit-width of a flip-flop to abstract [default = 1000000000]
+	-I num : maximum number of CEGAR iterations [default = 1000]
+	-L num : maximum number of each type of signals [default = 1000000000]
+	-x     : toggle XORing outputs of word-level miter [default = yes]
+	-a     : toggle running pdr with -nct [default = no]
+	-b     : toggle using proof-based refinement [default = no]
+	-r     : toggle using both cex-based and proof-based refinement [default = yes]
+	-c     : toggle checking clauses in the reloaded trace [default = yes]
+	-d     : toggle using another way of creating abstractions [default = no]
+	-i     : toggle using PPI values in proof-based refinement [default = no]
+	-l     : toggle loading previous PDR traces [default = yes]
+	-s     : toggle shrinking abstractions with BMC [default = no]
+	-t     : toggle restarting pdr from scratch after shrinking abstractions with BMC [default = no]
+	-u     : toggle checking combinationally unsat [default = no]
+	-p     : toggle pushing clauses in the reloaded trace [default = no]
+	-q     : toggle running bmc3 in parallel for CEX [default = no]
+	-m     : toggle refining the whole MFFC of a PPI [default = yes]
+	-v     : toggle printing verbose information [default = no]
+	-w     : toggle printing verbose PDR output [default = no]
+	-h     : print the command usage
+
+usage: %print [-pdvh]
+	         print statistics about the hierarchical design
+	-p     : toggle printing of the hierarchy [default = no]
+	-d     : toggle printing of the design [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+	<file> : text file name with guidance for solving
+
+usage: %profile [-vh]
+	         profiles arithmetic components in the word-level networks
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: %ps [-cbamdtovh]
+	         prints statistics
+	-c     : toggle printing cones [default = no]
+	-b     : toggle printing multipliers [default = no]
+	-a     : toggle printing adders [default = no]
+	-m     : toggle printing memories [default = no]
+	-d     : toggle printing distrubition [default = no]
+	-t     : toggle printing stats for LHS and RHS [default = no]
+	-o     : toggle printing all objects [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: %read [-opivh] <file_name>
+	         reads word-level design from Verilog file
+	-o     : toggle using old SMT-LIB parser [default = no]
+	-p     : toggle printing parse SMT-LIB tree [default = no]
+	-i     : toggle reading interface only [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: %retime [-isdvh]
+	         performs retiming for the NDR design
+	-i     : toggle ignoring delays of IO paths [default = no]
+	-s     : toggle printing simple nodes [default = yes]
+	-d     : toggle dumping the network in Verilog [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: %short_names [-vh]
+	         derives short names for all objects of the network
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: %show [-mh]
+          visualizes the network structure using DOT and GSVIEW
+	-m   :  toggle showing memory subsystem [default = no]
+	-h   :  print the command usage
+
+usage: %test [-vh]
+	         experiments with word-level networks
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: %write [-anfvh]
+	         writes the design into a file
+	-a     : toggle adding a CO for each node [default = no]
+	-n     : toggle splitting into individual nodes [default = no]
+	-f     : toggle skipping flops when writing file [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: %yosys [-T <module>] [-D <defines>] [-bismlcvh] <file_name>
+	         reads Verilog or SystemVerilog using Yosys
+	-T     : specify the top module name (default uses "-auto-top")
+	-D     : specify defines to be used by Yosys (default "not used")
+	-b     : toggle bit-blasting the design into an AIG using Yosys [default = no]
+	-i     : toggle inverting the outputs (useful for miters) [default = no]
+	-s     : toggle no structural hashing during bit-blasting [default = strash]
+	-m     : toggle using "techmap" to blast operators [default = yes]
+	-l     : toggle looking for "techmap.v" in the current directory [default = no]
+	-c     : toggle collapsing design hierarchy using Yosys [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: inv_check [-vh]
+	         checks that the invariant is indeed an inductive invariant
+	         (AIG representing the design should be in the &-space)
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: inv_get [-fvh]
+	         places invariant found by PDR as the current network in the main-space
+	         (in the case of 'sat' or 'undecided', infinity clauses are used)
+	-f     : toggle reading flop names from the &-space [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: inv_min [-lvh]
+	         performs minimization of the current invariant
+	         (AIG representing the design should be in the &-space)
+	-l     : toggle minimizing literals rather than clauses [default = no]
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: inv_print [-vh]
+	         prints the current inductive invariant
+	         (in the case of 'sat' or 'undecided', inifity clauses are used)
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: inv_ps [-vh]
+	         prints statistics for inductive invariant
+	         (in the case of 'sat' or 'undecided', inifity clauses are used)
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
+usage: inv_put [-vh]
+	         inputs the current network in the main-space as an invariant
+	         (AIG representing the design should be in the &-space)
+	-v     : toggle printing verbose information [default = no]
+	-h     : print the command usage
+
diff --git a/abc_script b/plugins/abc_script
similarity index 100%
rename from abc_script
rename to plugins/abc_script
diff --git a/run.sh b/run.sh
index 5b56ae5..5a885b7 100755
--- a/run.sh
+++ b/run.sh
@@ -1,374 +1,373 @@
 #!/bin/bash
 
 FILE=""
 FILE_BASENAME=""
 MODULE=""
 LIBERTY_FILE="nem_basic_yosys.lib"
 LIBERTY_USED="3T"
 visualize=0
 
 # Function to display the menu and get user input
 show_menu() {
     
 
     # Define color codes
     GREEN='\033[0;32m'
     YELLOW='\033[1;33m'
     CYAN='\033[0;36m'
     RESET='\033[0m'
 
     echo "--------------------------------------------------------------"
     echo -e "${CYAN}Current file: $FILE with module: $MODULE${RESET}"
     echo -e "${YELLOW}Please select your options (you can choose multiple options):${RESET}"
     echo
     echo -e "${GREEN}1)${RESET} Synthesize to NEM technology"
     echo -e "${GREEN}2)${RESET} Print initial design"
     echo -e "${GREEN}3)${RESET} Print out NEM optimized design"
     echo -e "${GREEN}4)${RESET} Perform SAT comparison"
     echo -e "${GREEN}5)${RESET} Export FSM as KISS2 format"
     echo -e "${GREEN}6)${RESET} Start shell with modules"
     echo -e "${GREEN}7)${RESET} Switch from normal 3T gate library to new 4T"
-    echo -e "${GREEN}8)${RESET} Run test"
-    echo -e "${GREEN}9)${RESET} export truth table and MUXIG run"
+    echo -e "${GREEN}8)${RESET} Run series of test and create comparison report"
+    echo -e "${GREEN}9)${RESET} Perform MUXIG synthesis run"
     echo -e "${GREEN}10)${RESET} export truth table and MIG run"
     echo -e "${GREEN}11)${RESET} Select a new Verilog file"
     echo -e "${GREEN}0)${RESET} Exit the program"
     echo "--------------------------------------------------------------"
 }
 
 # Request the file to process
 request_data(){
     echo "-:- Enter the file to map to NEM"
     read -e -p "What is the file name?: " FILE
     read -p "What is the name of the top module? (press ENTER for the same as the file name): " MODULE
 
     if [ ! -f "$FILE" ]; then
     echo "File not found"
     request_data
     fi
 
     FILE_BASENAME=$(basename "$FILE" | cut -d. -f1)
     #echo $FILE_BASENAME
 
     if [ -z "$MODULE" ]; then
     #echo "setting name equal to that of the file"
     MODULE=$FILE_BASENAME
     fi
 }
 
 #run a yosys file specified to the function
 run_yosys_file() {
     local yosys_file="$1"
     local depth="$2"
     local additional_yosys_args="$3"
     
     # Start with basic sed commands
     sed_command=$(sed -e "s|{{FILE}}|$FILE|g" \
                       -e "s|{{FILE_BASENAME}}|$FILE_BASENAME|g" \
                       -e "s|{{MODULE}}|$MODULE|g" \
                       -e "s|{{LIBERTY_FILE}}|$LIBERTY_FILE|g" \
                       -e "s|{{LIBERTY_USED}}|$LIBERTY_USED|g"\
                       "./yosys/${yosys_file}.ys")
 
     # Apply additional sed expressions based on DEPTH value
     if [[ $depth -eq 0 ]]; then
         sed_command=$(echo "$sed_command" | sed -e "/#IF {{DEPTH}}==0/d" \
                                                 -e "/#ELSE/,/#END/d")
     elif [[ $depth -eq 1 ]]; then
         sed_command=$(echo "$sed_command" | sed -e "/#IF {{DEPTH}}==0/,/#ELSE/d" \
                                                 -e "/#END/d")
     fi
 
     # Write the result to a temp file and run yosys
     echo "$sed_command" > "./temp/${yosys_file}_temp.ys"
     yosys $additional_yosys_args "./temp/${yosys_file}_temp.ys"
 }
 
 #Switch between 3T and 4T pass through gates
 switch_liberty() {
     if [ "$LIBERTY_FILE" == "nem_basic_yosys.lib" ]; then
         LIBERTY_FILE="nem_basic_yosys_extended.lib"
         LIBERTY_USED="4T"
         echo "Now using extended (4T devices) libary"
     elif [ "$LIBERTY_FILE" == "nem_basic_yosys_extended.lib" ]; then
         LIBERTY_FILE="nem_basic_yosys.lib"
         LIBERTY_USED="3T"
         echo "Now using normal libary"
     else
         echo "Unknown LIBERTY_FILE value: $LIBERTY_FILE"
     fi
 }
 
 compare_area() {
     # Extract area values from .stat files
     local area_3T=$(grep "Chip area for module" "./temp/${FILE_BASENAME}_3T.stat" | awk '{print $6}')
     local area_4T=$(grep "Chip area for module" "./temp/${FILE_BASENAME}_4T.stat" | awk '{print $6}')
     local area_MUX=$(grep "Chip area for module" "./temp/${FILE_BASENAME}_MUX.stat" | awk '{print $6}')
 
     # Calculate ratio as (area_3T / area_4T) * 100
     local ratio_4T=$(echo "($area_4T / $area_3T)" | bc -l)
     local ratio_MUX=$(echo "($area_MUX / $area_3T)" | bc -l)
 
         {
         echo "------------- normal 3T ---------------"
         cat "./temp/${FILE_BASENAME}_3T.stat"
         echo "------------- 4T ---------------"
         cat "./temp/${FILE_BASENAME}_4T.stat"
         echo "------------- Muxig ---------------"
         cat "./temp/${FILE_BASENAME}_MUX.stat"
         echo "------------- Stats ---------------"
         echo "Area 3T: $area_3T"
         echo "Area 4T: $area_4T"
         echo "Ratio 4T->3T: $ratio_4T%"
         echo "Area MUX: $area_MUX"
         echo "Ratio MUX->3T: $ratio_MUX%"
         
         ec
     } > "./output/${FILE_BASENAME}.ratio"
 
     # Output the areas and the ratio
     echo "Area 3T: $area_3T, Area 4T: $area_4T, Ratio 4T->3T: $ratio_4T, Area MUX: $area_MUX, Ratio MUX->3T: $ratio_MUX%" 
 }
 
 create_report() {
 
 # Output CSV file name
 csv_output="./output/output_report.csv"
 
 # Clear the CSV file by redirecting an empty string to it
 > "$csv_output"
 
 # Write the CSV header
 echo "Module,3T,4T,Ratio" > "$csv_output"
 # Print the header of the table
 printf "%-20s %-20s %-20s %-20s %-20s %-20s\n" "Module" "3T" "4T" "Ratio 4T" "MUX" "Ratio MUx"
 printf "%-20s %-20s %-20s %-20s %-20s %-20s\n" "-------" "------" "------" "-----" "-----" "-----"
 
 # Loop through each .ratio file in the directory
 for file in ./output/*.ratio; do
     # Check if the file exists
     if [[ -f "$file" ]]; then
         # Extract the module name
         module_name=$(grep -m 1 -oP '(?<==== ).*(?= ===)' "$file")  # Extract the module name
         
         # Extract areas using grep and sed
         area1=$(grep "Chip area for module" "$file" | sed -n '1s/.*: //p')  # Area 3T
         area2=$(grep "Chip area for module" "$file" | sed -n '2s/.*: //p')  # Area 4T
         area3=$(grep "Chip area for module" "$file" | sed -n '3s/.*: //p')  # Area MUX
 
         # Extract the ratio
         ratio_4T=$(grep -oP '(?<=Ratio 4T->3T: )[\d.]+' "$file")  # Extract the ratio
         ratio_MUX=$(grep -oP '(?<=Ratio MUX->3T: )[\d.]+' "$file")  # Extract the ratio
         # Append the data to the CSV file
         echo "$module_name,$area1,$area2,$ratio_4T,$area3,$ratio_MUX" >> "$csv_output"
         
         # Print the results in the table format
         printf "%-20s %-20s %-20s %-20s\n" "$module_name" "$area1" "$area2" "$ratio"
     fi
 done
 }
 
 
 #START ACTUAL EXECUTION
 
 #Check if in menu mode or in CLI mode
 if [ -z "$1" ]; then
     # in menu mode
     request_data
 else
     
     #in cli mode. Filter through all the parameters
     while getopts ":d:f:m:v:x:r:" opt; do
         case $opt in
             d)  # -d option for directory
                 file_directory="$OPTARG"
                 ;;
             f)  # -f option for file
                 FILE="$OPTARG"
                 ;;
             m)  # -m option for module (requires -f to be set)
                 MODULE="$OPTARG"
                 ;;
             v) # -v visualize before and after synthesis
                 echo "found visualize"
                 visualize=1
                 ;;
             x) # -x switch to extended nem liberty file
                 echo "switching to 4T libert file"
                 switch_liberty
                 ;;
             r) # -r generate report of output
                 echo "generating report"
                 create_report
                 ;;
             \?) # Invalid option
                 echo "Invalid option: -$OPTARG" >&2
                 usage
                 ;;
             :)  # Missing argument for an option
                 echo "Option -$OPTARG requires an argument." >&2
                 usage
                 ;;
         esac
     done
 
     #running synthesis on al lthe files in the directory
     if [ -n "$file_directory" ]; then
         if [ -d "$file_directory" ]; then
             echo "Directory exists: $file_directory"
 
             for file in "$file_directory"/*.v; do
             # Check if it's a regular file
             if [ -f "$file" ]; then
                 # Use grep to find the line that starts with 'module' and extract the module name
                 module_name=$(grep -m 1 -oP '^module\s+\K\w+' "$file")
-                
+                #module_name=
                 # If the module name is found, print the file path and the module name
                 if [ -n "$module_name" ]; then
                     echo "File: $file"
                     echo "Module: $module_name"
                     echo
 
                     FILE=$file
                     FILE_BASENAME=$(basename "$FILE" | cut -d. -f1)
-                    MODULE=$module_name
+                    #MODULE=$module_name
+                    MODULE=$FILE_BASENAME
 
                     #synthesise the file
                     echo "running sequence of test commands"
                     run_yosys_file "synth_nem" 0
                     #run_yosys_file "sat_test" 0
                     switch_liberty
                     run_yosys_file "synth_nem" 0
-                    #run_yosys_file "sat_test" 0
-                    run_yosys_file "bruteforce" 0
                     compare_area
                     switch_liberty
                 else
                     echo "No module found in file: $file"
                     echo
                 fi
             fi
         done
 
         #done with synthesis
         create_report
         exit 0
         
         else
             echo "Directory does not exist: $file_directory"
             exit 1
         fi
     fi
 
     #running synthesis on the file requested
     if [ -n "$FILE" ]; then
         if [ -n "$MODULE" ]; then
             if [ -f "$FILE" ]; then
                 echo "File exists: $file"
                 echo "Module: $module"
                 FILE_BASENAME=$(basename "$FILE" | cut -d. -f1)
                 run_yosys_file "synth_nem" 0
                 if [ "$visualize" -eq 1 ]; then
                 run_yosys_file "visual" 0
                 run_yosys_file "visual" 1
                 else
                 echo "no visualize set"
                 fi
                 exit 0
             else
                 echo "File does not exist: $file"
                 exit 1
             fi
         else
             echo "Missing module (-m) for the file (-f)."
             usage
         fi
     fi
     exit 1
  
 fi
 
 
 # Loop to allow multiple selections
 while true; do
   show_menu
   read -p "Enter your choices (e.g., 1 2 3, or 0 to finish): " -a choices
 
   for choice in "${choices[@]}"; do
     case $choice in
         1)
         echo "performing synthesis"
         run_yosys_file "synth_nem" 0
         ;;
         2)
         echo "Plotting the initial design with $FILE and $MODULE"
         run_yosys_file "visual" 0
         ;;
         3)
         echo "Plotting the NEM design with $FILE and $MODULE"
         run_yosys_file "visual" 1
         ;;
         4)
         echo "Performing SAT test on $FILE and $MODULE"
         run_yosys_file "sat_test" 0
         ;;
         5)
         echo "Exporting FSM overview of the design"
         make clean #to make sure no previous .kiss2 file remains
         run_yosys_file "fsm_export" 0
 
         if [ -f "./temp/${FILE_BASENAME}.kiss2" ]; then
             # If the file exists, run the python script and xdot
             python3 ./yosys/kiss2dot.py ./temp/${FILE_BASENAME}.kiss2 > ./temp/${FILE_BASENAME}.dot
             xdot ./temp/${FILE_BASENAME}.dot
         else
             # If the file doesn't exist, print a message
             echo "Could not detect an FSM in ${MODULE}"
         fi
         ;;
         6)
         echo "Plotting the initial design with $FILE and $MODULE"
         make clean #Clean directories
         run_yosys_file "synth_nem" 0
         make all #build plugins
         ls ./plugins/*.so
         run_yosys_file "start_shell" 0 "$(for so_file in ./plugins/*.so; do echo -m "$so_file"; done)" #create a list of all plugins to load
         ;;
         7)
         echo "Switching libary"
         switch_liberty
         ;;
         8)
         echo "running sequence of test commands"
         run_yosys_file "synth_nem" 0
         #run_yosys_file "visual" 1
         switch_liberty
         run_yosys_file "synth_nem" 0
         #run_yosys_file "visual" 1
         run_yosys_file "bruteforce" 0
         compare_area
         ;;
         9)
         echo "exporting truth table and running in mockturtle for muxig"
         run_yosys_file "bruteforce" 0
         ;;
         10)
         echo "exporting truth table and running in mockturtle for MIG"
         run_yosys_file "bruteforce" 1
         ;;
         11)
         echo "requesting new module"
         request_data
         ;;
         0)
         echo "exiting"
         break 2
         ;;
         *)
         echo "Invalid choice. Please select a number between 1 and 6."
         ;;
     esac
   done
 
   echo
 done
diff --git a/yosys/bruteforce.ys b/yosys/bruteforce.ys
index 3b34cd4..874e5c4 100644
--- a/yosys/bruteforce.ys
+++ b/yosys/bruteforce.ys
@@ -1,44 +1,48 @@
 read_verilog {{FILE}}
 
 #map to basic cells
 techmap
 opt;;
+aigmap;;
 
-write_blif ./temp/{{FILE_BASENAME}}.blif
+splitnets;;
+show -prefix ./temp/{{MODULE}}_bruteforce_aig_{{LIBERTY_USED}} -color orange t:$_NOT_ -color darkred t:$_AND_ -color purple t:$ge -color darkblue t:$ne -color blue t:$le -color maroon t:$add -enum
 
-abc -liberty ./{{LIBERTY_FILE}} -script "+strash; &get -n; collapse; write_eqn ./temp/{{FILE_BASENAME}}.eqn; &write_truths -x ./temp/{{FILE_BASENAME}}.truth"
+write_blif ./temp/{{FILE_BASENAME}}.blif
+write_aiger ./temp/{{FILE_BASENAME}}.aig
+#abc -liberty ./nem_liberty/{{LIBERTY_FILE}} -script "+strash; &get -n; collapse; write_eqn ./temp/{{FILE_BASENAME}}.eqn; &write_truths -x ./temp/{{FILE_BASENAME}}.truth"
 delete
 
 #IF {{DEPTH}}==0
 exec -- ./mockturtle/build/experiments/muxig_rewriting ./temp/{{FILE_BASENAME}}.blif 1
 #ELSE
 exec -- ./mockturtle/build/experiments/muxig_rewriting ./temp/{{FILE_BASENAME}}.blif 0
 #END
 
 exec -- python3 ./yosys/map_ports.py ./temp/{{FILE_BASENAME}}.blif ./temp/{{FILE_BASENAME}}_mockturtle.blif
 
 read_blif ./temp/mapped_{{FILE_BASENAME}}_mockturtle.blif
 
 rename top {{MODULE}}_nem
 
 techmap -map ./yosys/mockturtle_map.v
 
 techmap
 
 opt_expr
 
 clean -purge
 
 
 
 
-abc -liberty {{LIBERTY_FILE}} -script "+attach"
+abc -liberty ./nem_liberty/{{LIBERTY_FILE}} -script "+attach"
 
 clean -purge
 
 
 
 
 write_verilog -selected ./temp/{{FILE_BASENAME}}_nem.v
 #Output stats
-tee -o ./temp/{{FILE_BASENAME}}_MUX.stat stat -liberty ./{{LIBERTY_FILE}}
+tee -o ./temp/{{FILE_BASENAME}}_MUX.stat stat -liberty ./nem_liberty/{{LIBERTY_FILE}}
diff --git a/yosys/map_ports.py b/yosys/map_ports.py
index 285f409..228a8f0 100644
--- a/yosys/map_ports.py
+++ b/yosys/map_ports.py
@@ -1,63 +1,63 @@
 #!/usr/bin/env python3
 import re
 import sys
 import os
 
 if(len(sys.argv)!=3):
-        sys.exit("Use format: map_pors YOSYS_BLIF_FILE MOCKTURTLE_BLIF_FILE")
+        sys.exit("Use format: map_ports YOSYS_BLIF_FILE MOCKTURTLE_BLIF_FILE")
 
 yosys_file = sys.argv[1]
 mockturtle_file = sys.argv[2]
 
 print("mapping: " + mockturtle_file + " to " + yosys_file)
 
 os.system('pwd')
 
 inputVariables = []
 outputVariables = []
 
 with open(yosys_file, 'r') as infile:
     lines = infile.readlines()
 
 
 for line in lines:
     if line.startswith(".inputs"):
         inputs = line.split()
         inputVariables = inputs[1:]
 
     if line.startswith(".outputs"):
         outputs = line.split()
         outputVariables = outputs[1:]
 
 print('input variables',inputVariables)
 print('ouput variables',outputVariables)
 
 replacementList = {}
 
 for x in range(len(inputVariables)):
     inputReplaceVar = "pi" + str(x + 1)
     replacementList.update({inputReplaceVar:inputVariables[x]})
 
 for x in range(len(outputVariables)):
     inputReplaceVar = "po" + str(x)
     replacementList.update({inputReplaceVar:outputVariables[x]})
 
 print('replacement list:',replacementList)
 
 # construct mapped path. 
 mapped_file_parts = mockturtle_file.split('/')
 mapped_file_parts[-1] = "mapped_" + mapped_file_parts[-1]
 mapped_file = "/".join(mapped_file_parts)
 
 
 #replace the replacement items in the blif Mockturtle file back to yosys input and outputs
 with open(mockturtle_file, 'r') as mockfile:
     with open(mapped_file, 'w') as outfile:
         for line in mockfile:
             for src, target in replacementList.items():
                 line = line.replace(src + " ", target + " ")
                 if(target in outputVariables):
                     line = line.replace(src, target)
             outfile.write(line)
 
 print("finished mapping ports")
\ No newline at end of file
diff --git a/yosys/sat_test.ys b/yosys/sat_test.ys
index 13f0a19..166bbcb 100644
--- a/yosys/sat_test.ys
+++ b/yosys/sat_test.ys
@@ -1,30 +1,30 @@
 # test to check sat comparison.
 echo on
 
-read_liberty -ignore_miss_func ./nem_basic_yosys.lib
+read_liberty -ignore_miss_func ./nem_liberty/nem_basic_yosys.lib
 design -save lib # save the Liberty library
 
 read_verilog {{FILE}}
 read_verilog ./temp/{{FILE_BASENAME}}_nem.v
 
 proc
 clean
 
 miter -equiv -make_assert {{MODULE}} {{MODULE}}_nem equal
 
 #show equal
 
 flatten equal
 
 clean
 
 opt -full;;
 
 techmap -map %lib
 
 
 #show -pause equal
 
 stat equal
 
 sat -prove-asserts -set-init-zero -tempinduct -verify -show-regs -show-inputs -show-outputs -dump_vcd trace.vcd equal
diff --git a/yosys/start_shell.ys b/yosys/start_shell.ys
index 0a351a9..32f443f 100644
--- a/yosys/start_shell.ys
+++ b/yosys/start_shell.ys
@@ -1,12 +1,12 @@
 echo on
 read_verilog ./temp/{{FILE_BASENAME}}_nem.v
 hierarchy -top {{MODULE}}_nem
 proc
 opt
 clean
 stat
 
-read_liberty -lib ./nem_basic_yosys.lib
+read_liberty -lib ./nem_liberty/nem_basic_yosys.lib
 #show
 dump -o ./temp/{{FILE_BASENAME}}_nem_dump.v
 critical_path
\ No newline at end of file
diff --git a/yosys/synth_nem.ys b/yosys/synth_nem.ys
index 6a6fbe5..db2af80 100644
--- a/yosys/synth_nem.ys
+++ b/yosys/synth_nem.ys
@@ -1,58 +1,58 @@
 echo on
 
 # read the information
 read_verilog {{FILE}}
 hierarchy -top {{MODULE}}
 
 #unroll the information
 proc;
 opt -full;;
 
 #flatten the counter to its lower parts
 flatten;;
 
 fsm
 
 ##show -prefix ./temp/{{MODULE}}_post_flatten {{MODULE}}
 
 #optimize
 opt -full;;
 
 ##show -prefix ./temp/{{MODULE}}_post_flatten_opt {{MODULE}}
 
 #Map to gates using the standard techmap available
 techmap
 
 #opt -full;;
 
 #mapping memory
-dfflibmap -liberty ./{{LIBERTY_FILE}};;
+dfflibmap -liberty ./nem_liberty/{{LIBERTY_FILE}};;
 
 #optimizing possible memory mapping
 opt -full;;
 
 ##show -prefix ./temp/{{MODULE}}_post_techmap {{MODULE}}
 
 #USE BLIF TO IMPORT TO ABC
 #write_blif ./temp/{{MODULE}}_intermediate.blif
 
 #USE JSON TO IMPORT TO SVG TOOL: https://neilturley.dev/netlistsvg/
 #write_json ./temp/{{FILE_BASENAME}}_{{LIBERTY_USED}}.json
 
 #Replace basic combinational gates with those in our standard cell library
 #abc -liberty ./nem_basic_yosys.lib -script ./abc_script -showtmp
-abc -liberty ./{{LIBERTY_FILE}}
+abc -liberty ./nem_liberty/{{LIBERTY_FILE}}
 
 ##show -prefix ./temp/{{MODULE}}_post_opt {{MODULE}}
 
 #Check if we can optimize further
 opt -full;;
 
 clean -purge
 
 #Write to file
 rename {{MODULE}} {{MODULE}}_nem
 write_verilog ./temp/{{FILE_BASENAME}}_nem.v
 
 #Output stats
-tee -o ./temp/{{FILE_BASENAME}}_{{LIBERTY_USED}}.stat stat -liberty ./{{LIBERTY_FILE}}
+tee -o ./temp/{{FILE_BASENAME}}_{{LIBERTY_USED}}.stat stat -liberty ./nem_liberty/{{LIBERTY_FILE}}
diff --git a/yosys/test.ys b/yosys/test.ys
new file mode 100644
index 0000000..e4383f9
--- /dev/null
+++ b/yosys/test.ys
@@ -0,0 +1,8 @@
+read_verilog sources/ISCAS85/c17/c17.v
+
+read_blif ./temp/c17_mockturtle.blif
+techmap -map ./yosys/mockturtle_map.v
+clean
+recover_names
+
+show
diff --git a/yosys/visual.ys b/yosys/visual.ys
index b1118ab..a462805 100644
--- a/yosys/visual.ys
+++ b/yosys/visual.ys
@@ -1,23 +1,23 @@
 echo on
 
 
 
-read_liberty ./nem_basic_yosys_extended.lib
+read_liberty ./nem_liberty/nem_basic_yosys_extended.lib
 
 #IF {{DEPTH}}==0
 read_verilog {{FILE}}
 hierarchy -top {{MODULE}}
 proc
 clean
 
-
+splitnets;;
 show  -prefix ./temp/{{MODULE}}_initial  -color darkred t:$mux -color green t:$dff -color purple t:$ge -color darkblue t:$ne -color blue t:$le -color maroon t:$add -enum {{MODULE}}
 stat
 #ELSE
 
 read_verilog ./temp/{{FILE_BASENAME}}_nem.v
 hierarchy -top {{MODULE}}_nem
-
+splitnets;;
 show -prefix ./temp/{{MODULE}}_synthesized_{{LIBERTY_USED}} -color orange t:inv* -color darkred t:nor* -color green t:and* -color orange t:xor* -color purple t:or* -color darkblue t:nand* -color red t:xnor* -color maroon t:D_FF -enum {{MODULE}}_nem
 stat
 #END