diff --git a/.gitignore b/.gitignore index cd78447..597f2c7 100644 --- a/.gitignore +++ b/.gitignore @@ -1 +1,5 @@ -temp/ \ No newline at end of file +#make sure no temperory files go with it +temp/ +output/ +plugins/*.d +plugins/*.so \ No newline at end of file diff --git a/nem_basic_yosys_extended.lib b/nem_basic_yosys_extended.lib index 03896f9..2eec0b1 100644 --- a/nem_basic_yosys_extended.lib +++ b/nem_basic_yosys_extended.lib @@ -1,2265 +1,2355 @@ library (nem_basic) { comment : "Manually created liberty with more gates - ignore any timing information"; date : "$April 26th 2024$"; revision : "0.2"; delay_model : table_lookup; capacitive_load_unit (1,pf); time_unit : "1ns"; current_unit : "1uA"; voltage_unit : "1V"; voltage_map (VCC,15); voltage_map (GND,0); default_cell_leakage_power : 0; default_fanout_load : 1; default_max_transition : 500; default_output_pin_cap : 0; input_threshold_pct_rise : 50.0; input_threshold_pct_fall : 50.0; output_threshold_pct_rise : 50.0; output_threshold_pct_fall : 50.0; slew_lower_threshold_pct_rise : 20.0; slew_lower_threshold_pct_fall : 20.0; slew_upper_threshold_pct_rise : 80.0; slew_upper_threshold_pct_fall : 80.0; slew_derate_from_library : 1.0; nom_process : 1; nom_temperature : 125; nom_voltage : 15; operating_conditions (NEM_BASIC_COND) { process : 1; temperature : 125; voltage : 29; } default_operating_conditions : NEM_BASIC_COND; lu_table_template (delay_template_2x2) { variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1("0.01,0.1"); index_2("0.02,0.2"); } lu_table_template (constraint_template_2x2) { variable_1 : constrained_pin_transition; variable_2 : related_pin_transition; index_1("0.01,0.1"); index_2("0.02,0.2"); } cell(inv_3T) { area : 1160; cell_footprint : inv_3T; /* cell_description : "NEM 3T Inverter"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (in) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "!(in)"; max_capacitance : 10; max_fanout : 10; max_transition : 500; timing () { related_pin : "in"; timing_sense : negative_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(buf_3T) { area : 2240; cell_footprint : buf_3T; /* cell_description : "NEM 3T Buffer"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (in) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "in"; max_capacitance : 10; max_fanout : 10; max_transition : 500; timing () { related_pin : "in"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(nand_3T) { area : 2832; cell_footprint : nand_3T; /* cell_description : "NEM 3T 2-Input NAND"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "!(a&b)"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : negative_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : negative_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(and_3T) { area : 3912; cell_footprint : and_3T; /* cell_description : "NEM 3T 2-Input AND"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "a&b"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(nor_3T) { area : 2832; cell_footprint : nor_3T; /* cell_description : "NEM 3T 2-Input NOR"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "!(a|b)"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : negative_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : negative_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(or_3T) { area : 3952; cell_footprint : or_3T; /* cell_description : "NEM 3T 2-Input OR"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "a|b"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(xnor_3T) { area : 7824; cell_footprint : xnor_3T; /* cell_description : "NEM 3T 2-Input XNOR"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "!(a^b)"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(xor_3T) { area : 7824; cell_footprint : xor_3T; /* cell_description : "NEM 3T 2-Input XOR"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "a^b"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(mux_3T) { area : 8000; cell_footprint : mux_3T; /* cell_description : "NEM 3T 2-Input MUX"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } /*bundle(in) { members(in_0,in_1); direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; }*/ pin(in_0){ direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin(in_1){ direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (sel) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "(!sel & in_0) | (sel & in_1)"; max_fanout : 10; timing () { related_pin : "in_0"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "in_1"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "sel"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(mux_4T) { area : 3472; cell_footprint : mux_4T; /* cell_description : "NEM 4T 2-Input MUX"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } /*bundle(in) { members(in_0,in_1); direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; }*/ pin(in_0){ direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin(in_1){ direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (sel) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "(!sel & in_0) | (sel & in_1)"; max_fanout : 10; timing () { related_pin : "in_0"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "in_1"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "sel"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(and_4T) { area : 3472; cell_footprint : and_4T; /* cell_description : "NEM 4T 2-Input AND based on muxiplayers pass logic"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "a&b"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } -cell(and_4T_inv) { +cell(and_not_4T) { area : 3472; cell_footprint : and_4T; /* cell_description : "NEM 4T 2-Input AND based on muxiplayers pass logic having inverted input"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "a&!(b)"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(or_4T) { area : 3472; cell_footprint : or_4T; /* cell_description : "NEM 4T 2-Input OR based on muxiplayers pass logic"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "a|b"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } -cell(or_4T_inv) { +cell(or_not_4T) { area : 3472; cell_footprint : or_4T; /* cell_description : "NEM 4T 2-Input OR based on muxiplayers pass logic having inverted input"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "a|!(b)"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } cell(xor_4T) { area : 4632; cell_footprint : xor_3T; /* cell_description : "NEM 4T 2-Input XOR based on 2 4T and 3T inverter"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (a) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (b) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (out) { direction : "output"; related_ground_pin : GND; related_power_pin : VCC; function : "a^b"; max_fanout : 10; timing () { related_pin : "a"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "b"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } } +cell(xor_4T_test) { + area : 1; + cell_footprint : xor_3T; +/* cell_description : "NEM 4T 2-Input XOR based on 2 4T needs an inverted input"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (c) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "(a^b) | (b&c)"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + pin_opposite("b", "c"); +} + /* cell(SR_latch) { area : 2704; cell_footprint : SR_latch; cell_description : "NEM based S-R type Latch"; pin (S) { direction : "input"; } pin (R) { direction : "input"; } pin (Q) { direction : "output"; function : "IQ"; } pin (Q_bar) { direction : "output"; function : "IQB"; } latch (IQ,IQB) { preset : "S" clear : "R" clear_preset_var1 : L; clear_preset_var2 : L; } statetable (" R S ", " IQ IQB "){ table : "H L : - - : L H ,\ L H : - - : H L ,\ H H : - - : L L ,\ L L : - - : N N"; } } */ cell(D_latch) { area : 9448; cell_footprint : D_latch; /* cell_description : "NEM based D type Latch"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (D) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; /* data_in_type : data;*/ /* timing() { related_pin : "EN"; timing_type : hold_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } timing() { related_pin : "EN"; timing_type : setup_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } */ } pin (EN) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (Q) { direction : "output"; function : "QOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; /* timing () { related_pin : "D"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "EN"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } */ } pin (Q_bar) { direction : "output"; function : "QBOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; /* timing () { related_pin : "D"; timing_sense : negative_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "EN"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } */ } latch (QOUT,QBOUT) { enable : "EN"; data_in : "D"; } } cell(D_latch_rst) { area : 13432; cell_footprint : D_latch_rst; /* cell_description : "NEM based D type Latch with reset"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (D) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; /* data_in_type : data;*/ } pin (EN) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (rst) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (Q) { direction : "output"; function : "QOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "D"; timing_sense : positive_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "EN"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4darkblue.0","0.21,4.1"); } } } pin (Q_bar) { direction : "output"; function : "QBOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "D"; timing_sense : negative_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } timing () { related_pin : "EN"; timing_sense : non_unate; timing_type : combinational; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } latch (QOUT,QBOUT) { enable : "EN"; data_in : "D"; clear : "rst"; } } cell(D_FF) { area : 20056; cell_footprint : D_FF; /* cell_description : "NEM based M-S D type Flip Flop"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (D) { nextstate_type : data; direction : "input"; related_ground_pin : GND; related_power_pin : VCC; max_transition : 0.2; capacitance : 1; timing () { related_pin : "CLK"; timing_type : hold_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } timing () { related_pin : "CLK"; timing_type : setup_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } } pin (CLK) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (Q) { direction : "output"; function : "QOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } pin (Q_bar) { direction : "output"; function : "QBOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } ff (QOUT,QBOUT) { clocked_on : "CLK"; next_state : "D"; } } cell(D_FF_rst) { area : 28184; cell_footprint : D_FF_rst; /* cell_description : "NEM based M-S D type Flip Flop with reset"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (D) { nextstate_type : data; direction : "input"; related_ground_pin : GND; related_power_pin : VCC; max_transition : 0.2; capacitance : 1; timing () { related_pin : "CLK"; timing_type : hold_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } timing () { related_pin : "CLK"; timing_type : setup_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,-4.0","0.21,4.1"); } } } pin (rst) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_type : recovery_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } } timing () { related_pin : "CLK"; timing_type : removal_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } } } pin (CLK) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (Q) { direction : "output"; function : "QOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } pin (Q_bar) { direction : "output"; function : "QBOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } ff (QOUT,QBOUT) { clear : "rst"; clocked_on : "CLK"; next_state : "D"; } } /* SCAN FUNCTIONALITY HASN'T BEEN ADDED YET */ cell(S_FF) { area : 20056; cell_footprint : D_FF; /* cell_description : "NEM based M-S D type Flip Flop with scan functionality";*/ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (D) { nextstate_type : data; direction : "input"; related_ground_pin : GND; related_power_pin : VCC; max_transition : 0.2; capacitance : 1; timing () { related_pin : "CLK"; timing_type : hold_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } timing () { related_pin : "CLK"; timing_type : setup_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } } pin (SI) { nextstate_type : data; direction : "input"; related_ground_pin : GND; related_power_pin : VCC; max_transition : 0.2; capacitance : 1; timing () { related_pin : "CLK"; timing_type : hold_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } timing () { related_pin : "CLK"; timing_type : setup_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } } pin (CLK) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (Q) { direction : "output"; function : "QOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } pin (Q_bar) { direction : "output"; function : "QBOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } ff (QOUT,QBOUT) { clocked_on : "CLK"; next_state : "D"; } } /* SCAN FUNCTIONALITY HASN'T BEEN ADDED YET */ cell(S_FF_rst) { area : 28184; cell_footprint : S_FF_rst; /* cell_description : "NEM based M-S D type Flip Flop with reset and scan functionality"; */ pg_pin (VCC) { pg_type : primary_power; voltage_name : "VCC"; } pg_pin (GND) { pg_type : primary_ground; voltage_name : "GND"; } pin (D) { nextstate_type : data; direction : "input"; related_ground_pin : GND; related_power_pin : VCC; max_transition : 0.2; capacitance : 1; timing () { related_pin : "CLK"; timing_type : hold_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","-0.21,4.1"); } } timing () { related_pin : "CLK"; timing_type : setup_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,-4.0","0.21,4.1"); } } } pin (rst) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_type : recovery_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("-0.2,-2.0","-0.21,-2.1"); } } timing () { related_pin : "CLK"; timing_type : removal_rising; rise_constraint (constraint_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } } } pin (CLK) { direction : "input"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; } pin (Q) { direction : "output"; function : "QOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } pin (Q_bar) { direction : "output"; function : "QBOUT"; related_ground_pin : GND; related_power_pin : VCC; capacitance : 1; timing () { related_pin : "CLK"; timing_sense : non_unate; timing_type : rising_edge; cell_rise (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } rise_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } cell_fall (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,2.0","0.21,2.1"); } fall_transition (delay_template_2x2) { index_1 ("0.01,0.1"); index_2 ("0.02,0.2"); values ("0.2,4.0","0.21,4.1"); } } } ff (QOUT,QBOUT) { clear : "rst"; clocked_on : "CLK"; next_state : "D"; } } } diff --git a/run.sh b/run.sh index 2063b96..4ab990e 100755 --- a/run.sh +++ b/run.sh @@ -1,350 +1,350 @@ #!/bin/bash FILE="" FILE_BASENAME="" MODULE="" LIBERTY_FILE="nem_basic_yosys.lib" LIBERTY_USED="3T" visualize=0 # Function to display the menu and get user input show_menu() { # Define color codes GREEN='\033[0;32m' YELLOW='\033[1;33m' CYAN='\033[0;36m' RESET='\033[0m' echo "--------------------------------------------------------------" echo -e "${CYAN}Current file: $FILE with module: $MODULE${RESET}" echo -e "${YELLOW}Please select your options (you can choose multiple options):${RESET}" echo echo -e "${GREEN}1)${RESET} Synthesize NEM mapped replicate of Verilog implementation" echo -e "${GREEN}2)${RESET} Print initial design" echo -e "${GREEN}3)${RESET} Print out NEM optimized design" echo -e "${GREEN}4)${RESET} Perform SAT comparison" echo -e "${GREEN}5)${RESET} Export FSM as KISS2 format" echo -e "${GREEN}6)${RESET} Start shell with modules" echo -e "${GREEN}7)${RESET} Switch from normal 3T gate library to new 4T" echo -e "${GREEN}8)${RESET} Run test" echo -e "${GREEN}9)${RESET} Select a new Verilog file" echo -e "${GREEN}0)${RESET} Exit the program" echo "--------------------------------------------------------------" } # Request the file to process request_data(){ echo "-:- Enter the file to map to NEM" read -e -p "What is the file name?: " FILE read -p "What is the name of the top module? (press ENTER for the same as the file name): " MODULE if [ ! -f "$FILE" ]; then echo "File not found" request_data fi FILE_BASENAME=$(basename "$FILE" | cut -d. -f1) #echo $FILE_BASENAME if [ -z "$MODULE" ]; then #echo "setting name equal to that of the file" MODULE=$FILE_BASENAME fi } #run a yosys file specified to the function run_yosys_file() { local yosys_file="$1" local depth="$2" local additional_yosys_args="$3" # Start with basic sed commands sed_command=$(sed -e "s|{{FILE}}|$FILE|g" \ -e "s|{{FILE_BASENAME}}|$FILE_BASENAME|g" \ -e "s|{{MODULE}}|$MODULE|g" \ -e "s|{{LIBERTY_FILE}}|$LIBERTY_FILE|g" \ -e "s|{{LIBERTY_USED}}|$LIBERTY_USED|g"\ "./yosys/${yosys_file}.ys") # Apply additional sed expressions based on DEPTH value if [[ $depth -eq 0 ]]; then sed_command=$(echo "$sed_command" | sed -e "/#IF {{DEPTH}}==0/d" \ -e "/#ELSE/,/#END/d") elif [[ $depth -eq 1 ]]; then sed_command=$(echo "$sed_command" | sed -e "/#IF {{DEPTH}}==0/,/#ELSE/d" \ -e "/#END/d") fi # Write the result to a temp file and run yosys echo "$sed_command" > "./temp/${yosys_file}_temp.ys" yosys $additional_yosys_args "./temp/${yosys_file}_temp.ys" } #Switch between 3T and 4T pass through gates switch_liberty() { if [ "$LIBERTY_FILE" == "nem_basic_yosys.lib" ]; then LIBERTY_FILE="nem_basic_yosys_extended.lib" LIBERTY_USED="4T" echo "Now using extended (4T devices) libary" elif [ "$LIBERTY_FILE" == "nem_basic_yosys_extended.lib" ]; then LIBERTY_FILE="nem_basic_yosys.lib" LIBERTY_USED="3T" echo "Now using normal libary" else echo "Unknown LIBERTY_FILE value: $LIBERTY_FILE" fi } compare_area() { # Extract area values from .stat files local area_3T=$(grep "Chip area for module" "./temp/${FILE_BASENAME}_3T.stat" | awk '{print $6}') local area_4T=$(grep "Chip area for module" "./temp/${FILE_BASENAME}_4T.stat" | awk '{print $6}') # Calculate ratio as (area_3T / area_4T) * 100 local ratio=$(echo "($area_4T / $area_3T)" | bc -l) { cat "./temp/${FILE_BASENAME}_3T.stat" cat "./temp/${FILE_BASENAME}_4T.stat" echo "Area 3T: $area_3T" echo "Area 4T: $area_4T" echo "Ratio 4T->3T: $ratio%" } > "./output/${FILE_BASENAME}.ratio" # Output the areas and the ratio echo "Area 3T: $area_3T, Area 4T: $area_4T, ratio 4T->3T: $ratio" } create_report() { # Output CSV file name -csv_output="./output_report.csv" +csv_output="./output/output_report.csv" # Clear the CSV file by redirecting an empty string to it > "$csv_output" # Write the CSV header echo "Module,3T,4T,Ratio" > "$csv_output" # Print the header of the table printf "%-20s %-20s %-20s %-20s\n" "Module" "3T" "4T" "Ratio" printf "%-20s %-20s %-20s %-20s\n" "-------" "------" "------" "-----" # Loop through each .ratio file in the directory for file in ./output/*.ratio; do # Check if the file exists if [[ -f "$file" ]]; then # Extract the module name module_name=$(grep -m 1 -oP '(?<==== ).*(?= ===)' "$file") # Extract the module name # Extract areas using grep and sed area1=$(grep "Chip area for module" "$file" | sed -n '1s/.*: //p') # Area 3T area2=$(grep "Chip area for module" "$file" | sed -n '2s/.*: //p') # Area 4T # Extract the ratio ratio=$(grep -oP '(?<=Ratio 4T->3T: )[\d.]+' "$file") # Extract the ratio # Append the data to the CSV file echo "$module_name,$area1,$area2,$ratio" >> "$csv_output" # Print the results in the table format printf "%-20s %-20s %-20s %-20s\n" "$module_name" "$area1" "$area2" "$ratio" fi done } #START ACTUAL EXECUTION #Check if in menu mode or in CLI mode if [ -z "$1" ]; then # in menu mode request_data else #in cli mode. Filter through all the parameters while getopts ":d:f:m:v:x:r:" opt; do case $opt in d) # -d option for directory file_directory="$OPTARG" ;; f) # -f option for file FILE="$OPTARG" ;; m) # -m option for module (requires -f to be set) MODULE="$OPTARG" ;; v) # -v visualize before and after synthesis echo "found visualize" visualize=1 ;; x) # -x switch to extended nem liberty file echo "switching to 4T libert file" switch_liberty ;; r) # -r generate report of output echo "generating report" create_report ;; \?) # Invalid option echo "Invalid option: -$OPTARG" >&2 usage ;; :) # Missing argument for an option echo "Option -$OPTARG requires an argument." >&2 usage ;; esac done #running synthesis on al lthe files in the directory if [ -n "$file_directory" ]; then if [ -d "$file_directory" ]; then echo "Directory exists: $file_directory" for file in "$file_directory"/*.v; do # Check if it's a regular file if [ -f "$file" ]; then # Use grep to find the line that starts with 'module' and extract the module name module_name=$(grep -m 1 -oP '^module\s+\K\w+' "$file") # If the module name is found, print the file path and the module name if [ -n "$module_name" ]; then echo "File: $file" echo "Module: $module_name" echo FILE=$file FILE_BASENAME=$(basename "$FILE" | cut -d. -f1) MODULE=$module_name #synthesise the file echo "running sequence of test commands" run_yosys_file "synth_nem" 0 #run_yosys_file "sat_test" 0 switch_liberty run_yosys_file "synth_nem" 0 #run_yosys_file "sat_test" 0 compare_area switch_liberty else echo "No module found in file: $file" echo fi fi done #done with synthesis create_report exit 0 else echo "Directory does not exist: $file_directory" exit 1 fi fi #running synthesis on the file requested if [ -n "$FILE" ]; then if [ -n "$MODULE" ]; then if [ -f "$FILE" ]; then echo "File exists: $file" echo "Module: $module" FILE_BASENAME=$(basename "$FILE" | cut -d. -f1) run_yosys_file "synth_nem" 0 if [ "$visualize" -eq 1 ]; then run_yosys_file "visual" 0 run_yosys_file "visual" 1 else echo "no visualize set" fi exit 0 else echo "File does not exist: $file" exit 1 fi else echo "Missing module (-m) for the file (-f)." usage fi fi exit 1 fi # Loop to allow multiple selections while true; do show_menu read -p "Enter your choices (e.g., 1 2 3, or 0 to finish): " -a choices for choice in "${choices[@]}"; do case $choice in 1) echo "performing synthesis" run_yosys_file "synth_nem" 0 ;; 2) echo "Plotting the initial design with $FILE and $MODULE" run_yosys_file "visual" 0 ;; 3) echo "Plotting the NEM design with $FILE and $MODULE" run_yosys_file "visual" 1 ;; 4) echo "Performing SAT test on $FILE and $MODULE" run_yosys_file "sat_test" 0 ;; 5) echo "Exporting FSM overview of the design" make clean #to make sure no previous .kiss2 file remains run_yosys_file "fsm_export" 0 if [ -f "./temp/${FILE_BASENAME}.kiss2" ]; then # If the file exists, run the python script and xdot python3 ./yosys/kiss2dot.py ./temp/${FILE_BASENAME}.kiss2 > ./temp/${FILE_BASENAME}.dot xdot ./temp/${FILE_BASENAME}.dot else # If the file doesn't exist, print a message echo "Could not detect an FSM in ${MODULE}" fi ;; 6) echo "Plotting the initial design with $FILE and $MODULE" make clean #Clean directories run_yosys_file "synth_nem" 0 make all #build plugins ls ./plugins/*.so run_yosys_file "start_shell" 0 "$(for so_file in ./plugins/*.so; do echo -m "$so_file"; done)" #create a list of all plugins to load ;; 7) echo "Switching libary" switch_liberty ;; 8) echo "running sequence of test commands" run_yosys_file "synth_nem" 0 run_yosys_file "visual" 1 switch_liberty run_yosys_file "synth_nem" 0 run_yosys_file "visual" 1 compare_area ;; 9) echo "requesting new module" request_data ;; 0) echo "exiting" break 2 ;; *) echo "Invalid choice. Please select a number between 1 and 6." ;; esac done echo done