diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..cd78447 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +temp/ \ No newline at end of file diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..cd3525d --- /dev/null +++ b/Makefile @@ -0,0 +1,38 @@ +#used for compiling yosys plugins + +# Define directories +PLUGIN_DIR := ./plugins +TEMP_DIR := ./temp + +# Compiler and flags +CXX := gcc # Assuming you're using gcc to avoid newer GLIBCXX version issues +CXXFLAGS := -Wall -Wextra -ggdb -I/home/jasper/uni/i-edge/oss-cad-suite/share/yosys/include \ + -MD -MP -D_YOSYS_ -fPIC -I/home/jasper/uni/i-edge/oss-cad-suite/include \ + -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS \ + -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -I/usr/include/tcl8.6 \ + -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -rdynamic +LDFLAGS := -shared +LIBS := -lm -lrt -lreadline -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 + +# Find all .cc files in the ./plugins directory +SRCS := $(wildcard $(PLUGIN_DIR)/*.cc) + +# Create a list of corresponding .so files +OBJS := $(SRCS:.cc=.so) + +# Default target is to build all .so files +all: $(OBJS) + +# Compile each .cc file to a .so file +$(PLUGIN_DIR)/%.so: $(PLUGIN_DIR)/%.cc + $(CXX) $(CXXFLAGS) -o $@ $(LDFLAGS) $< $(LIBS) + +# Clean up build artifacts and temp files +clean: + rm -f $(PLUGIN_DIR)/*.so $(PLUGIN_DIR)/*.d + rm -rf $(TEMP_DIR)/* + +# Add the dependency files generated with -MD (auto-dependency generation) +-include $(SRCS:.cc=.d) + +.PHONY: all clean diff --git a/README.md b/README.md new file mode 100644 index 0000000..4ebc9e4 --- /dev/null +++ b/README.md @@ -0,0 +1,105 @@ +# Table of content +- [Table of content](#table-of-content) +- [1. NEM synthesis](#1-nem-synthesis) +- [2. data structure](#2-data-structure) +- [3. How to run](#3-how-to-run) +- [4. CLI](#4-cli) +- [5. Optimisation adjusments](#5-optimisation-adjusments) +- [6. Troubleshooting](#6-troubleshooting) + - [6.1. SAT comparison](#61-sat-comparison) + +# 1. NEM synthesis + +This utility was written to use yosys to synthesize from verilog to a netlist existing out of all standard cells available in the current library of NEM cells. It only uses the freely available yosys oss suite. No license required + +# 2. data structure + +The application is ordered as follows: + +``` +\sources\ : All the verilog files for synthesis have to be stored here +\temp\ : Contains all the output files after synthesis or intermediate yosys / graphviz dots files. +\yosys\ : Script that are executed for synthesis, visual, and sat testing. +\nem_basic_yosys.lib : This is the file of all the standard cells used in nem +\nem_basic_yosys_extended.lib : this is the additional cells added based on some new concepts + ``` + +As a user put the desired source files in .\sources\ and had to the next sessions +# 3. How to run + +Pull the repository to your local working directory. + +run: + +```bash +source /enviroment +./run.sh +``` + +and enter the file you want to use. Auto-complete is aviable, an example would be `sources/test_set/adder2.v`. Then enter the main module name. Just press enter if it is the same as the file name, (in the example `adder2`). + +You will be presented with the following options: + +```bash +-------------------------------------------------------------- +Current file: sources/test_set/adder2.v with module: adder2 +Please select your options (you can choose multiple options): + +1) Synthesize NEM mapped replicate of Verilog implementation +2) Print initial design +3) Print out NEM optimized design +4) Perform SAT comparison +5) Export FSM as KISS2 format +6) Start shell with modules +7) Switch from normal 3T gate library to new 4T +8) Run test +9) Select a new Verilog file +0) Exit the program +-------------------------------------------------------------- +Enter your choices (e.g., 1 2 3, or 0 to finish): +``` + +1: As the text explains option 1 will run the synthesis script under `\yosys\` and will output the file as `_nem.v` extension in the `\temp\` folder. Next to that it will output statistics in the `.stat` file under `\temp\`. +2: Shows the abstract design before any syntehsis is done +3: Shows the final synthesized solution +4: Checks if the original verilog file matches the output of the final synthesised solution. +5: search for fsm model and view it +6: Compile plugins and start a shell to run them +7: Switch to extended liberty file with pass through muxiplexers +8: run synthesis and visual for both liberty files +9: switch to different verilog file + +# 4. CLI + +You can also call the `./run.sh` with some arguments to work as a in-line tool if you want to automate stuff. The options are: + +-d [DIRECTORY] synthesise all the files in the directory +-f [FILE_PATH] syntehsise specific path +-m [MODULE_NAME] When -f argument used +-v when present will also visuale the file. +-x Switch liberty file to extended version + +# 5. Optimisation adjusments + +the new extended libary makes use of trivial boolean equivalent muxiplexers and operators for AND and OR operations. More info will be added later. + +# 6. Troubleshooting + +## 6.1. SAT comparison +If the SAT comparison gives a comment that it is not aware of a certain `_DFF_` cell such as `_DFF_PP0` then this specific memeory cell does not exist in the standard cell library therefore it does not have the function to simulate it. These register often have asynchronous reset therefore make sure that your design does not use + +``` +always@(posedge clk or posedge rst) + if (rst) begin + result <= 0; +...... +``` +but instead +``` +always@(posedge clk) + if (rst) begin + result <= 0; +...... +``` + +So that reset happens on the same clk as a normal `_DFF_` register. \ No newline at end of file diff --git a/abc_script b/abc_script new file mode 100644 index 0000000..3c87d8c --- /dev/null +++ b/abc_script @@ -0,0 +1,2 @@ + strash; show; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash; + &get -n; show; &dch -f; &nf {D}; &put; show -g \ No newline at end of file diff --git a/compile_commands.json b/compile_commands.json new file mode 100644 index 0000000..2b3a621 --- /dev/null +++ b/compile_commands.json @@ -0,0 +1,31 @@ +[ + { + "arguments": [ + "/usr/bin/gcc", + "-c", + "-Wall", + "-Wextra", + "-ggdb", + "-I/home/jasper/uni/i-edge/oss-cad-suite/share/yosys/include", + "-D_YOSYS_", + "-fPIC", + "-I/home/jasper/uni/i-edge/oss-cad-suite/include", + "-std=c++17", + "-O3", + "-DYOSYS_ENABLE_READLINE", + "-DYOSYS_ENABLE_PLUGINS", + "-DYOSYS_ENABLE_GLOB", + "-DYOSYS_ENABLE_ZLIB", + "-I/usr/include/tcl8.6", + "-DYOSYS_ENABLE_TCL", + "-DYOSYS_ENABLE_ABC", + "-DYOSYS_ENABLE_COVER", + "-o", + "plugins/my_cmd.so", + "plugins/my_cmd.cc" + ], + "directory": "/home/jasper/uni/i-edge/application", + "file": "/home/jasper/uni/i-edge/application/plugins/my_cmd.cc", + "output": "/home/jasper/uni/i-edge/application/plugins/my_cmd.so" + } +] diff --git a/nem_basic_yosys.lib b/nem_basic_yosys.lib new file mode 100644 index 0000000..7f733ac --- /dev/null +++ b/nem_basic_yosys.lib @@ -0,0 +1,1850 @@ +library (nem_basic) { +comment : "Manually created liberty with more gates - ignore any timing information"; +date : "$April 26th 2024$"; +revision : "0.2"; +delay_model : table_lookup; +capacitive_load_unit (1,pf); +time_unit : "1ns"; +current_unit : "1uA"; +voltage_unit : "1V"; +voltage_map (VCC,15); +voltage_map (GND,0); +default_cell_leakage_power : 0; +default_fanout_load : 1; +default_max_transition : 500; +default_output_pin_cap : 0; +input_threshold_pct_rise : 50.0; +input_threshold_pct_fall : 50.0; +output_threshold_pct_rise : 50.0; +output_threshold_pct_fall : 50.0; +slew_lower_threshold_pct_rise : 20.0; +slew_lower_threshold_pct_fall : 20.0; +slew_upper_threshold_pct_rise : 80.0; +slew_upper_threshold_pct_fall : 80.0; +slew_derate_from_library : 1.0; +nom_process : 1; +nom_temperature : 125; +nom_voltage : 15; + +operating_conditions (NEM_BASIC_COND) { + process : 1; + temperature : 125; + voltage : 29; +} +default_operating_conditions : NEM_BASIC_COND; + +lu_table_template (delay_template_2x2) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.01,0.1"); + index_2("0.02,0.2"); +} + +lu_table_template (constraint_template_2x2) { + variable_1 : constrained_pin_transition; + variable_2 : related_pin_transition; + index_1("0.01,0.1"); + index_2("0.02,0.2"); +} + +cell(inv_3T) { + area : 1160; + cell_footprint : inv_3T; +/* cell_description : "NEM 3T Inverter"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (in) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "!(in)"; + max_capacitance : 10; + max_fanout : 10; + max_transition : 500; + timing () { + related_pin : "in"; + timing_sense : negative_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + +cell(buf_3T) { + area : 2240; + cell_footprint : buf_3T; +/* cell_description : "NEM 3T Buffer"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (in) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "in"; + max_capacitance : 10; + max_fanout : 10; + max_transition : 500; + timing () { + related_pin : "in"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + +cell(nand_3T) { + area : 2832; + cell_footprint : nand_3T; +/* cell_description : "NEM 3T 2-Input NAND"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "!(a&b)"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : negative_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : negative_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + + +cell(and_3T) { + area : 3912; + cell_footprint : and_3T; + /* cell_description : "NEM 3T 2-Input AND"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "a&b"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + +cell(nor_3T) { + area : 2832; + cell_footprint : nor_3T; + /* cell_description : "NEM 3T 2-Input NOR"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "!(a|b)"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : negative_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : negative_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + +cell(or_3T) { + area : 3952; + cell_footprint : or_3T; +/* cell_description : "NEM 3T 2-Input OR"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "a|b"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + +cell(xnor_3T) { + area : 7824; + cell_footprint : xnor_3T; +/* cell_description : "NEM 3T 2-Input XNOR"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "!(a^b)"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + +cell(xor_3T) { + area : 7824; + cell_footprint : xor_3T; +/* cell_description : "NEM 3T 2-Input XOR"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "a^b"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + + +cell(mux_3T) { + area : 8000; + cell_footprint : mux_3T; +/* cell_description : "NEM 3T 2-Input MUX"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + /*bundle(in) { + members(in_0,in_1); + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + }*/ + pin(in_0){ + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin(in_1){ + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (sel) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "(!sel & in_0) | (sel & in_1)"; + max_fanout : 10; + timing () { + related_pin : "in_0"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "in_1"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "sel"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + + +cell(mux_4T) { + area : 3472; + cell_footprint : mux_4T; +/* cell_description : "NEM 4T 2-Input MUX"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + /*bundle(in) { + members(in_0,in_1); + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + }*/ + pin(in_0){ + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin(in_1){ + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (sel) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "(!sel & in_0) | (sel & in_1)"; + max_fanout : 10; + timing () { + related_pin : "in_0"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "in_1"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "sel"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + +/* +cell(SR_latch) { + area : 2704; + cell_footprint : SR_latch; + cell_description : "NEM based S-R type Latch"; + pin (S) { + direction : "input"; + } + pin (R) { + direction : "input"; + } + pin (Q) { + direction : "output"; + function : "IQ"; + } + pin (Q_bar) { + direction : "output"; + function : "IQB"; + } + latch (IQ,IQB) { + preset : "S" + clear : "R" + clear_preset_var1 : L; + clear_preset_var2 : L; + } + statetable (" R S ", " IQ IQB "){ + table : "H L : - - : L H ,\ + L H : - - : H L ,\ + H H : - - : L L ,\ + L L : - - : N N"; + } +} +*/ + +cell(D_latch) { + area : 9448; + cell_footprint : D_latch; +/* cell_description : "NEM based D type Latch"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (D) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + /* data_in_type : data;*/ +/* + timing() { + related_pin : "EN"; + timing_type : hold_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + timing() { + related_pin : "EN"; + timing_type : setup_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } +*/ + } + pin (EN) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (Q) { + direction : "output"; + function : "QOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; +/* + timing () { + related_pin : "D"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "EN"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } +*/ + } + pin (Q_bar) { + direction : "output"; + function : "QBOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; +/* + timing () { + related_pin : "D"; + timing_sense : negative_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "EN"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } +*/ + } + latch (QOUT,QBOUT) { + enable : "EN"; + data_in : "D"; + } +} + + +cell(D_latch_rst) { + area : 13432; + cell_footprint : D_latch_rst; +/* cell_description : "NEM based D type Latch with reset"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (D) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + /* data_in_type : data;*/ + } + pin (EN) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (rst) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (Q) { + direction : "output"; + function : "QOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "D"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "EN"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4darkblue.0","0.21,4.1"); + } + } + } + pin (Q_bar) { + direction : "output"; + function : "QBOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "D"; + timing_sense : negative_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "EN"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + latch (QOUT,QBOUT) { + enable : "EN"; + data_in : "D"; + clear : "rst"; + } +} + +cell(D_FF) { + area : 20056; + cell_footprint : D_FF; +/* cell_description : "NEM based M-S D type Flip Flop"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (D) { + nextstate_type : data; + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + max_transition : 0.2; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_type : hold_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + timing () { + related_pin : "CLK"; + timing_type : setup_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + } + pin (CLK) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (Q) { + direction : "output"; + function : "QOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_sense : non_unate; + timing_type : rising_edge; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + pin (Q_bar) { + direction : "output"; + function : "QBOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_sense : non_unate; + timing_type : rising_edge; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + ff (QOUT,QBOUT) { + clocked_on : "CLK"; + next_state : "D"; + } +} + +cell(D_FF_rst) { + area : 28184; + cell_footprint : D_FF_rst; +/* cell_description : "NEM based M-S D type Flip Flop with reset"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (D) { + nextstate_type : data; + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + max_transition : 0.2; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_type : hold_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + timing () { + related_pin : "CLK"; + timing_type : setup_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,-4.0","0.21,4.1"); + } + } + } + pin (rst) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_type : recovery_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + } + timing () { + related_pin : "CLK"; + timing_type : removal_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + } + } + pin (CLK) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (Q) { + direction : "output"; + function : "QOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_sense : non_unate; + timing_type : rising_edge; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + pin (Q_bar) { + direction : "output"; + function : "QBOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_sense : non_unate; + timing_type : rising_edge; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + ff (QOUT,QBOUT) { + clear : "rst"; + clocked_on : "CLK"; + next_state : "D"; + } +} + +/* SCAN FUNCTIONALITY HASN'T BEEN ADDED YET */ +cell(S_FF) { + area : 20056; + cell_footprint : D_FF; +/* cell_description : "NEM based M-S D type Flip Flop with scan functionality";*/ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (D) { + nextstate_type : data; + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + max_transition : 0.2; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_type : hold_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + timing () { + related_pin : "CLK"; + timing_type : setup_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + } + pin (SI) { + nextstate_type : data; + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + max_transition : 0.2; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_type : hold_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + timing () { + related_pin : "CLK"; + timing_type : setup_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + } + pin (CLK) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (Q) { + direction : "output"; + function : "QOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_sense : non_unate; + timing_type : rising_edge; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + pin (Q_bar) { + direction : "output"; + function : "QBOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_sense : non_unate; + timing_type : rising_edge; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + ff (QOUT,QBOUT) { + clocked_on : "CLK"; + next_state : "D"; + } +} + +/* SCAN FUNCTIONALITY HASN'T BEEN ADDED YET */ +cell(S_FF_rst) { + area : 28184; + cell_footprint : S_FF_rst; +/* cell_description : "NEM based M-S D type Flip Flop with reset and scan functionality"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (D) { + nextstate_type : data; + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + max_transition : 0.2; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_type : hold_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + timing () { + related_pin : "CLK"; + timing_type : setup_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,-4.0","0.21,4.1"); + } + } + } + pin (rst) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_type : recovery_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + } + timing () { + related_pin : "CLK"; + timing_type : removal_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + } + } + pin (CLK) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (Q) { + direction : "output"; + function : "QOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_sense : non_unate; + timing_type : rising_edge; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + pin (Q_bar) { + direction : "output"; + function : "QBOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_sense : non_unate; + timing_type : rising_edge; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + ff (QOUT,QBOUT) { + clear : "rst"; + clocked_on : "CLK"; + next_state : "D"; + } +} +} diff --git a/nem_basic_yosys_extended.lib b/nem_basic_yosys_extended.lib new file mode 100644 index 0000000..03896f9 --- /dev/null +++ b/nem_basic_yosys_extended.lib @@ -0,0 +1,2265 @@ +library (nem_basic) { +comment : "Manually created liberty with more gates - ignore any timing information"; +date : "$April 26th 2024$"; +revision : "0.2"; +delay_model : table_lookup; +capacitive_load_unit (1,pf); +time_unit : "1ns"; +current_unit : "1uA"; +voltage_unit : "1V"; +voltage_map (VCC,15); +voltage_map (GND,0); +default_cell_leakage_power : 0; +default_fanout_load : 1; +default_max_transition : 500; +default_output_pin_cap : 0; +input_threshold_pct_rise : 50.0; +input_threshold_pct_fall : 50.0; +output_threshold_pct_rise : 50.0; +output_threshold_pct_fall : 50.0; +slew_lower_threshold_pct_rise : 20.0; +slew_lower_threshold_pct_fall : 20.0; +slew_upper_threshold_pct_rise : 80.0; +slew_upper_threshold_pct_fall : 80.0; +slew_derate_from_library : 1.0; +nom_process : 1; +nom_temperature : 125; +nom_voltage : 15; + +operating_conditions (NEM_BASIC_COND) { + process : 1; + temperature : 125; + voltage : 29; +} +default_operating_conditions : NEM_BASIC_COND; + +lu_table_template (delay_template_2x2) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.01,0.1"); + index_2("0.02,0.2"); +} + +lu_table_template (constraint_template_2x2) { + variable_1 : constrained_pin_transition; + variable_2 : related_pin_transition; + index_1("0.01,0.1"); + index_2("0.02,0.2"); +} + +cell(inv_3T) { + area : 1160; + cell_footprint : inv_3T; +/* cell_description : "NEM 3T Inverter"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (in) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "!(in)"; + max_capacitance : 10; + max_fanout : 10; + max_transition : 500; + timing () { + related_pin : "in"; + timing_sense : negative_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + +cell(buf_3T) { + area : 2240; + cell_footprint : buf_3T; +/* cell_description : "NEM 3T Buffer"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (in) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "in"; + max_capacitance : 10; + max_fanout : 10; + max_transition : 500; + timing () { + related_pin : "in"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + +cell(nand_3T) { + area : 2832; + cell_footprint : nand_3T; +/* cell_description : "NEM 3T 2-Input NAND"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "!(a&b)"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : negative_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : negative_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + + +cell(and_3T) { + area : 3912; + cell_footprint : and_3T; + /* cell_description : "NEM 3T 2-Input AND"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "a&b"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + +cell(nor_3T) { + area : 2832; + cell_footprint : nor_3T; + /* cell_description : "NEM 3T 2-Input NOR"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "!(a|b)"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : negative_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : negative_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + +cell(or_3T) { + area : 3952; + cell_footprint : or_3T; +/* cell_description : "NEM 3T 2-Input OR"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "a|b"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + +cell(xnor_3T) { + area : 7824; + cell_footprint : xnor_3T; +/* cell_description : "NEM 3T 2-Input XNOR"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "!(a^b)"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + +cell(xor_3T) { + area : 7824; + cell_footprint : xor_3T; +/* cell_description : "NEM 3T 2-Input XOR"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "a^b"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + + +cell(mux_3T) { + area : 8000; + cell_footprint : mux_3T; +/* cell_description : "NEM 3T 2-Input MUX"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + /*bundle(in) { + members(in_0,in_1); + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + }*/ + pin(in_0){ + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin(in_1){ + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (sel) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "(!sel & in_0) | (sel & in_1)"; + max_fanout : 10; + timing () { + related_pin : "in_0"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "in_1"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "sel"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + + +cell(mux_4T) { + area : 3472; + cell_footprint : mux_4T; +/* cell_description : "NEM 4T 2-Input MUX"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + /*bundle(in) { + members(in_0,in_1); + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + }*/ + pin(in_0){ + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin(in_1){ + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (sel) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "(!sel & in_0) | (sel & in_1)"; + max_fanout : 10; + timing () { + related_pin : "in_0"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "in_1"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "sel"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} +cell(and_4T) { + area : 3472; + cell_footprint : and_4T; +/* cell_description : "NEM 4T 2-Input AND based on muxiplayers pass logic"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "a&b"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + +cell(and_4T_inv) { + area : 3472; + cell_footprint : and_4T; +/* cell_description : "NEM 4T 2-Input AND based on muxiplayers pass logic having inverted input"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "a&!(b)"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + +cell(or_4T) { + area : 3472; + cell_footprint : or_4T; +/* cell_description : "NEM 4T 2-Input OR based on muxiplayers pass logic"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "a|b"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + + +cell(or_4T_inv) { + area : 3472; + cell_footprint : or_4T; +/* cell_description : "NEM 4T 2-Input OR based on muxiplayers pass logic having inverted input"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "a|!(b)"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + +cell(xor_4T) { + area : 4632; + cell_footprint : xor_3T; +/* cell_description : "NEM 4T 2-Input XOR based on 2 4T and 3T inverter"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (a) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (b) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (out) { + direction : "output"; + related_ground_pin : GND; + related_power_pin : VCC; + function : "a^b"; + max_fanout : 10; + timing () { + related_pin : "a"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "b"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } +} + +/* +cell(SR_latch) { + area : 2704; + cell_footprint : SR_latch; + cell_description : "NEM based S-R type Latch"; + pin (S) { + direction : "input"; + } + pin (R) { + direction : "input"; + } + pin (Q) { + direction : "output"; + function : "IQ"; + } + pin (Q_bar) { + direction : "output"; + function : "IQB"; + } + latch (IQ,IQB) { + preset : "S" + clear : "R" + clear_preset_var1 : L; + clear_preset_var2 : L; + } + statetable (" R S ", " IQ IQB "){ + table : "H L : - - : L H ,\ + L H : - - : H L ,\ + H H : - - : L L ,\ + L L : - - : N N"; + } +} +*/ + +cell(D_latch) { + area : 9448; + cell_footprint : D_latch; +/* cell_description : "NEM based D type Latch"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (D) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + /* data_in_type : data;*/ +/* + timing() { + related_pin : "EN"; + timing_type : hold_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + timing() { + related_pin : "EN"; + timing_type : setup_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } +*/ + } + pin (EN) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (Q) { + direction : "output"; + function : "QOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; +/* + timing () { + related_pin : "D"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "EN"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } +*/ + } + pin (Q_bar) { + direction : "output"; + function : "QBOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; +/* + timing () { + related_pin : "D"; + timing_sense : negative_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "EN"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } +*/ + } + latch (QOUT,QBOUT) { + enable : "EN"; + data_in : "D"; + } +} + + +cell(D_latch_rst) { + area : 13432; + cell_footprint : D_latch_rst; +/* cell_description : "NEM based D type Latch with reset"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (D) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + /* data_in_type : data;*/ + } + pin (EN) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (rst) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (Q) { + direction : "output"; + function : "QOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "D"; + timing_sense : positive_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "EN"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4darkblue.0","0.21,4.1"); + } + } + } + pin (Q_bar) { + direction : "output"; + function : "QBOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "D"; + timing_sense : negative_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + timing () { + related_pin : "EN"; + timing_sense : non_unate; + timing_type : combinational; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + latch (QOUT,QBOUT) { + enable : "EN"; + data_in : "D"; + clear : "rst"; + } +} + +cell(D_FF) { + area : 20056; + cell_footprint : D_FF; +/* cell_description : "NEM based M-S D type Flip Flop"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (D) { + nextstate_type : data; + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + max_transition : 0.2; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_type : hold_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + timing () { + related_pin : "CLK"; + timing_type : setup_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + } + pin (CLK) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (Q) { + direction : "output"; + function : "QOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_sense : non_unate; + timing_type : rising_edge; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + pin (Q_bar) { + direction : "output"; + function : "QBOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_sense : non_unate; + timing_type : rising_edge; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + ff (QOUT,QBOUT) { + clocked_on : "CLK"; + next_state : "D"; + } +} + +cell(D_FF_rst) { + area : 28184; + cell_footprint : D_FF_rst; +/* cell_description : "NEM based M-S D type Flip Flop with reset"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (D) { + nextstate_type : data; + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + max_transition : 0.2; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_type : hold_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + timing () { + related_pin : "CLK"; + timing_type : setup_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,-4.0","0.21,4.1"); + } + } + } + pin (rst) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_type : recovery_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + } + timing () { + related_pin : "CLK"; + timing_type : removal_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + } + } + pin (CLK) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (Q) { + direction : "output"; + function : "QOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_sense : non_unate; + timing_type : rising_edge; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + pin (Q_bar) { + direction : "output"; + function : "QBOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_sense : non_unate; + timing_type : rising_edge; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + ff (QOUT,QBOUT) { + clear : "rst"; + clocked_on : "CLK"; + next_state : "D"; + } +} + +/* SCAN FUNCTIONALITY HASN'T BEEN ADDED YET */ +cell(S_FF) { + area : 20056; + cell_footprint : D_FF; +/* cell_description : "NEM based M-S D type Flip Flop with scan functionality";*/ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (D) { + nextstate_type : data; + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + max_transition : 0.2; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_type : hold_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + timing () { + related_pin : "CLK"; + timing_type : setup_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + } + pin (SI) { + nextstate_type : data; + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + max_transition : 0.2; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_type : hold_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + timing () { + related_pin : "CLK"; + timing_type : setup_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + } + pin (CLK) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (Q) { + direction : "output"; + function : "QOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_sense : non_unate; + timing_type : rising_edge; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + pin (Q_bar) { + direction : "output"; + function : "QBOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_sense : non_unate; + timing_type : rising_edge; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + ff (QOUT,QBOUT) { + clocked_on : "CLK"; + next_state : "D"; + } +} + +/* SCAN FUNCTIONALITY HASN'T BEEN ADDED YET */ +cell(S_FF_rst) { + area : 28184; + cell_footprint : S_FF_rst; +/* cell_description : "NEM based M-S D type Flip Flop with reset and scan functionality"; */ + pg_pin (VCC) { + pg_type : primary_power; + voltage_name : "VCC"; + } + pg_pin (GND) { + pg_type : primary_ground; + voltage_name : "GND"; + } + pin (D) { + nextstate_type : data; + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + max_transition : 0.2; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_type : hold_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","-0.21,4.1"); + } + } + timing () { + related_pin : "CLK"; + timing_type : setup_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,-4.0","0.21,4.1"); + } + } + } + pin (rst) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_type : recovery_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("-0.2,-2.0","-0.21,-2.1"); + } + } + timing () { + related_pin : "CLK"; + timing_type : removal_rising; + rise_constraint (constraint_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + } + } + pin (CLK) { + direction : "input"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + } + pin (Q) { + direction : "output"; + function : "QOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_sense : non_unate; + timing_type : rising_edge; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + pin (Q_bar) { + direction : "output"; + function : "QBOUT"; + related_ground_pin : GND; + related_power_pin : VCC; + capacitance : 1; + timing () { + related_pin : "CLK"; + timing_sense : non_unate; + timing_type : rising_edge; + cell_rise (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + rise_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + cell_fall (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,2.0","0.21,2.1"); + } + fall_transition (delay_template_2x2) { + index_1 ("0.01,0.1"); + index_2 ("0.02,0.2"); + values ("0.2,4.0","0.21,4.1"); + } + } + } + ff (QOUT,QBOUT) { + clear : "rst"; + clocked_on : "CLK"; + next_state : "D"; + } +} +} diff --git a/plugins/cpp-dump b/plugins/cpp-dump new file mode 160000 index 0000000..fdb8210 --- /dev/null +++ b/plugins/cpp-dump @@ -0,0 +1 @@ +Subproject commit fdb821073bd658767f1acbbb711866989279f22c diff --git a/plugins/critical_path.cc b/plugins/critical_path.cc new file mode 100644 index 0000000..0305f7a --- /dev/null +++ b/plugins/critical_path.cc @@ -0,0 +1,192 @@ +#include +#include "kernel/log.h" +#include "kernel/rtlil.h" +#include "kernel/yosys.h" +#include "kernel/sigtools.h" +#include "kernel/celltypes.h" +#include "kernel/yosys_common.h" + +#include +#include +#include + + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +//Set up pair to map signal to cell driver or trigger +typedef std::pair sig2driver_entry_t; +static SigSet sig2driver, sig2trigger; + +static void populate_sig_driver_trigger_database(RTLIL::Design *design, RTLIL::Module *mod, SigMap *sigmap){ + log("Building database of all cells and their matching connections \n"); + + CellTypes ct(design); + + for (auto cell : mod->cells()) { + for (auto &conn_it : cell->connections()) { + + if (ct.cell_output(cell->type, conn_it.first) || !ct.cell_known(cell->type)) { + RTLIL::SigSpec sig = conn_it.second; + sigmap->apply(sig); + //log("adding output driver %s:%s - %s:%s\n",log_id(cell),log_id(conn_it.first),(sig.is_wire() ? log_id(sig.as_wire()->name): "not wire"),log_id(sig[0].wire)); + sig2driver.insert(sig, sig2driver_entry_t(cell, conn_it.first)); + } + if (ct.cell_input(cell->type, conn_it.first) || !ct.cell_known(cell->type)) { + RTLIL::SigSpec sig = conn_it.second; + sigmap->apply(sig); + //log("adding input trigger %s\n",log_id(cell)); + sig2trigger.insert(sig, sig2driver_entry_t(cell, conn_it.first)); + } + } + } +} + + + +static int find_longest_path(RTLIL::Design *design, SigMap *sigmap_ptr, RTLIL::Wire *current, RTLIL::Wire *wire_out, std::vector* visited, std::vector* longest_path_cache_ptr, int length, int longest_length) +{ + SigMap &sigmap = *sigmap_ptr; + std::vector &longest_path_cache = *longest_path_cache_ptr; + + CellTypes ct(design); //get celltype match to check for outputs + //log("--------------------------------------------------------\n"); + //log("Checking path: %s -> %s\n",log_id(current->name),log_id(wire_out->name)); + + // If we reached the destination, the path length is 0 + if (sigmap(current) == sigmap(wire_out)){ + //log("Found target!!!!!!!!!\n"); + //log("--------------------------------------------------------\n"); + if(length>longest_length){ + //log("new route is longer setting route\n"); + longest_path_cache.clear(); + for(auto sig: *visited){ + //log("%s->",(sig->is_wire() ? log_id(sig->as_wire()):log_id(sig->as_bit().wire))); + longest_path_cache.push_back(*sig); + longest_length = length; + } + //log("\n"); + } + return longest_length; + } + + RTLIL::SigSpec sig_wire = sigmap(current); + + // Mark this wire as visited + visited->push_back(&sig_wire); + + //for(auto sig: *visited){ + // log("%s->",(sig->is_wire() ? log_id(sig->as_wire()):log_id(sig->as_bit().wire))); + //} + //log("\n"); + + std::set cellport_list; //create list to populate with the connected cells + sig2trigger.find(sig_wire, cellport_list); //populate it with the found cells + + //log("before %s, after %s\n",log_id(current),(sig_wire.is_wire() ? log_id(sig_wire.as_wire()->name): "not wire")); + // Explore all connections (edges) from the current wire + for (auto cell: cellport_list){ + //log("wire %s on %s,\n",log_id(cell.second),log_id(cell.first)); + for (auto conn : cell.first->connections()) { + // Avoid revisiting wires to prevent cycles + if ((conn.second.is_wire() || conn.second.is_bit()) && ct.cell_output(cell.first->type, conn.first)) { + // Recursively calculate the longest path from next_wire to wire_out + RTLIL::Wire* next_wire= (conn.second.is_wire() ? conn.second.as_wire(): conn.second.as_bit().wire); //check if it is a wire or only one bit of a wire + + //log("Going recursive on %s\n",log_id(next_wire)); + + longest_length = find_longest_path(design, sigmap_ptr, next_wire, wire_out, visited, longest_path_cache_ptr, length+1,longest_length); + } + } + } + + // Unmark this wire (backtrack) + visited->pop_back(); + + // Cache the result for this wire + //log("-----------------------returning %s---------------------\n",log_id(current->name)); + // Return the longest path found + return longest_length; + + +} + +struct Critical_path : public Pass { + Critical_path() : Pass("critical_path", "will take the current design and calculate the longest path it can find. Afterwards will return a argument to print this in a show") { } + + void execute(std::vector args, RTLIL::Design *design) override + { + sig2driver.clear(); + sig2trigger.clear(); + + for (auto mod : design->modules()) + { + //Check if we are in the main module + if(GetSize(mod->cells())>0){ + // Instantiate SigMap for the current module + SigMap sigmap(mod); + + + + //print module name + log(" %s (%d wires, %d cells)\n", log_id(mod), GetSize(mod->wires()), GetSize(mod->cells())); + populate_sig_driver_trigger_database(design, mod,&sigmap); + + std::vector abst_longest_path; + int abst_path = 0; + + for (auto wire_in : mod->wires()) + { + if(wire_in->port_input){ //Is input + + for(auto wire_out: mod->wires()){ + + if(wire_out->port_output){ //is output + std::vector visited; + std::vector longest_path_cache; + visited.clear(); + longest_path_cache.clear(); + //log("************************************** starting %s->%s ******************************\n",log_id(wire_in),log_id(wire_out)); + int longest_path = find_longest_path(design,&sigmap ,wire_in, wire_out,&visited,&longest_path_cache,0,0); + + if(longest_path>abst_path){ + abst_path = longest_path; + abst_longest_path.clear(); + for(auto sig_pasted: longest_path_cache){ + abst_longest_path.push_back(sig_pasted); + } + abst_longest_path.push_back(sigmap(wire_out)); + } + + //for(auto sig_pasted: longest_path_cache){ + // log("%s->",(sig_pasted.is_wire() ? log_id(sig_pasted.as_wire()) : log_id(sig_pasted.as_bit().wire))); + //} + //log("%s -| longest path %s->%s returned is: %d \n", log_id(wire_out),log_id(wire_in),log_id(wire_out),longest_path); + } + } + } + } + + //Longest path + std::string show_cmd = "show"; + + log("Longest path found in total is %d\n",abst_path); + for(auto sig_pasted: abst_longest_path){ + show_cmd.append(" -color red w:"); + show_cmd.append(sig_pasted.is_wire() ? log_id(sig_pasted.as_wire()) : log_id(sig_pasted.as_bit().wire)); + log("%s,",(sig_pasted.is_wire() ? log_id(sig_pasted.as_wire()) : log_id(sig_pasted.as_bit().wire))); + } + log("\n Created following show: \n"); + + log("%s\n", show_cmd.c_str()); + + //calling the show + Pass::call(design, show_cmd); + + } + } + + } +} Critical_path; + +PRIVATE_NAMESPACE_END diff --git a/plugins/critical_path.d b/plugins/critical_path.d new file mode 100644 index 0000000..568c218 --- /dev/null +++ b/plugins/critical_path.d @@ -0,0 +1,749 @@ +plugins/critical_path.so: plugins/critical_path.cc \ + /usr/include/stdc-predef.h \ + /home/jasper/uni/i-edge/application/plugins/cpp-dump/cpp-dump.hpp \ + /usr/include/c++/14.2.1/algorithm \ + /usr/include/c++/14.2.1/bits/stl_algobase.h \ + /usr/include/c++/14.2.1/x86_64-pc-linux-gnu/bits/c++config.h \ + /usr/include/c++/14.2.1/x86_64-pc-linux-gnu/bits/os_defines.h \ + /usr/include/features.h /usr/include/features-time64.h \ + /usr/include/bits/wordsize.h /usr/include/bits/timesize.h \ + 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+/home/jasper/uni/i-edge/application/plugins/cpp-dump/./cpp-dump/hpp/export_var/././export_object_common.hpp: +/home/jasper/uni/i-edge/application/plugins/cpp-dump/./cpp-dump/hpp/export_var/./export_map.hpp: +/home/jasper/uni/i-edge/application/plugins/cpp-dump/./cpp-dump/hpp/export_var/./export_object.hpp: +/home/jasper/uni/i-edge/application/plugins/cpp-dump/./cpp-dump/hpp/export_var/./export_object_generic.hpp: +/home/jasper/uni/i-edge/application/plugins/cpp-dump/./cpp-dump/hpp/export_var/./export_ostream.hpp: +/home/jasper/uni/i-edge/application/plugins/cpp-dump/./cpp-dump/hpp/export_var/./export_other/export_other.hpp: +/home/jasper/uni/i-edge/application/plugins/cpp-dump/./cpp-dump/hpp/export_var/./export_other/./export_es_value_t.hpp: +/home/jasper/uni/i-edge/application/plugins/cpp-dump/./cpp-dump/hpp/export_var/./export_other/./export_optional.hpp: +/home/jasper/uni/i-edge/application/plugins/cpp-dump/./cpp-dump/hpp/export_var/./export_other/./export_other_object.hpp: +/home/jasper/uni/i-edge/application/plugins/cpp-dump/./cpp-dump/hpp/export_var/./export_other/./export_type_info.hpp: +/usr/include/c++/14.2.1/cxxabi.h: +/usr/include/c++/14.2.1/x86_64-pc-linux-gnu/bits/cxxabi_tweaks.h: +/home/jasper/uni/i-edge/application/plugins/cpp-dump/./cpp-dump/hpp/export_var/./export_pointer.hpp: +/home/jasper/uni/i-edge/application/plugins/cpp-dump/./cpp-dump/hpp/export_var/./export_set.hpp: +/home/jasper/uni/i-edge/application/plugins/cpp-dump/./cpp-dump/hpp/export_var/./export_string.hpp: +/home/jasper/uni/i-edge/application/plugins/cpp-dump/./cpp-dump/hpp/export_var/./export_tuple.hpp: +/home/jasper/uni/i-edge/application/plugins/cpp-dump/./cpp-dump/hpp/export_var/./export_xixo.hpp: +/home/jasper/uni/i-edge/oss-cad-suite/share/yosys/include/kernel/log.h: +/home/jasper/uni/i-edge/oss-cad-suite/share/yosys/include/kernel/yosys_common.h: +/usr/include/c++/14.2.1/fstream: +/usr/include/c++/14.2.1/x86_64-pc-linux-gnu/bits/basic_file.h: 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+/usr/include/bits/types/struct_sigstack.h: +/usr/include/bits/sigthread.h: +/usr/include/bits/signal_ext.h: +/home/jasper/uni/i-edge/oss-cad-suite/share/yosys/include/kernel/yosys.h: +/home/jasper/uni/i-edge/oss-cad-suite/share/yosys/include/kernel/rtlil.h: +/home/jasper/uni/i-edge/oss-cad-suite/share/yosys/include/kernel/constids.inc: +/home/jasper/uni/i-edge/oss-cad-suite/share/yosys/include/kernel/register.h: +/home/jasper/uni/i-edge/oss-cad-suite/share/yosys/include/kernel/sigtools.h: +/home/jasper/uni/i-edge/oss-cad-suite/share/yosys/include/kernel/celltypes.h: diff --git a/plugins/critical_path.so b/plugins/critical_path.so new file mode 100755 index 0000000..e831cb0 Binary files /dev/null and b/plugins/critical_path.so differ diff --git a/plugins/my_cmd.cc_ b/plugins/my_cmd.cc_ new file mode 100644 index 0000000..bb5dc5f --- /dev/null +++ b/plugins/my_cmd.cc_ @@ -0,0 +1,101 @@ +#include +#include "kernel/rtlil.h" +#include "kernel/yosys.h" +#include "kernel/celltypes.h" +#include "kernel/sigtools.h" + +#include +#include +#include + + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +//Set up pair to map signal to cell driver or trigger +typedef std::pair sig2driver_entry_t; +static SigSet sig2driver, sig2trigger; + +void build_database(RTLIL::Design *design, SigMap *sigmap){ + log("Building database of all cells and their matching connections /n"); + + CellTypes ct(design); + + for (auto mod : design->selected_modules()) + { + + sig2driver.clear(); + sig2trigger.clear(); + for (auto cell : mod->cells()) { + for (auto &conn_it : cell->connections()) { + + if (ct.cell_output(cell->type, conn_it.first) || !ct.cell_known(cell->type)) { + RTLIL::SigSpec sig = conn_it.second; + sigmap->apply(sig); + sig2driver.insert(sig, sig2driver_entry_t(cell, conn_it.first)); + } + if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort(ID::Y) && + cell->getPort(ID::Y).size() == 1 && (conn_it.first == ID::A || conn_it.first == ID::B)) { + RTLIL::SigSpec sig = conn_it.second; + sigmap->apply(sig); + sig2trigger.insert(sig, sig2driver_entry_t(cell, conn_it.first)); + } + } + } + } +} + +struct MyPass : public Pass { + MyPass() : Pass("my_cmd", "just a simple test") { } + + void execute(std::vector args, RTLIL::Design *design) override + { + log("Arguments to my_cmd:\n"); + for (auto &arg : args) + log(" %s\n", arg.c_str()); + + + + log("Modules in current design:\n"); + for (auto mod : design->modules()) + { + + // Instantiate SigMap for the current module + SigMap sigmap(mod); + + build_database(design, &sigmap); + + log(" %s (%d wires, %d cells)\n", log_id(mod), GetSize(mod->wires()), GetSize(mod->cells())); + + + + for (auto wire : mod->wires()) + { + // Use sigmap to canonicalize the signal + RTLIL::SigSpec sig = sigmap(wire); + + log("----------/------------\n"); + //print all info on the wire itself + log("current wire %s, width: %d, start_offset %d, port_id %d, port_input %d, port_output %d, upto %d, is_signed %d, %s \n", + log_id(wire->name), wire->width, wire->start_offset, wire->port_id, wire->port_input, wire->port_output, wire->upto, wire->is_signed, log_id(wire->name)); + log("Out: %d, in: %d \n",wire->port_output,wire->port_input); + } + log("----------/------------\n"); + for (auto cell : mod->cells()){ + log("current cell: %s, type %s\n",log_id(cell->name),log_id(cell->type)); + for( auto cellport_list : cell->connections_){ + RTLIL::SigSpec sigInCell = cellport_list.second; + log("in pair: %s, connection to: %s\n",log_id(cellport_list.first),(sigInCell.is_wire() ? log_id(sigInCell.as_wire()->name): "not wire")); + std::set cellport_test; + sig2driver.find(sigInCell, cellport_test); + for(auto cell: cellport_test){ + log("for %s find result: %s:%s, %s\n",(sigInCell.is_wire() ? log_id(sigInCell.as_wire()->name): "not wire"),log_id(cell.first),log_id(cell.first->type),log_id(cell.second)); + } + } + } + } + + } +} MyPass; + +PRIVATE_NAMESPACE_END diff --git a/plugins/stubnet.cc_ b/plugins/stubnet.cc_ new file mode 100644 index 0000000..bd2a42b --- /dev/null +++ b/plugins/stubnet.cc_ @@ -0,0 +1,137 @@ +// This is free and unencumbered software released into the public domain. +// Anyone is free to copy, modify, publish, use, compile, sell, or distribute +// this software, either in source code form or as a compiled binary, for any purpose, +// commercial or non-commercial, and by any means. + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" +#include +#include +#include + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +// This function is called for each module in the design +static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool report_bits) +{ + // Use a SigMap to convert nets to a unique representation + SigMap sigmap(module); + + // Count how many times a single-bit signal is used + std::map bit_usage_count; + + // Count output lines for this module (needed only for summary output at the end) + int line_count = 0; + + log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name)); + + // For all ports on all cells + for (auto &cell_iter : module->cells_) + { + for (auto &conn : cell_iter.second->connections()) + { + // Get the signals on the port (use sigmap to get a unique signal name) + RTLIL::SigSpec sig = sigmap(conn.second); + + // Add each bit to bit_usage_count, unless it is a constant + for (auto &bit : sig) + if (bit.wire != NULL) + bit_usage_count[bit]++; + } + } + + // For each wire in the module + for (auto &wire_iter : module->wires_) + { + RTLIL::Wire *wire = wire_iter.second; + + // Only selected wires + if (!design->selected(module, wire)) + continue; + + // Add +1 usage if this wire is actually a port + int usage_offset = wire->port_id > 0 ? 1 : 0; + + // Record which bits of the (possibly multi-bit) wire are stub signals + std::set stub_bits; + + // Get a signal description for this wire and split it into separate bits + RTLIL::SigSpec sig = sigmap(wire); + + // For each bit (unless it is a constant), check if it is used at least two times + // and add to stub_bits otherwise + for (int i = 0; i < GetSize(sig); i++) + if (sig[i].wire != NULL && (bit_usage_count[sig[i]] + usage_offset) < 2) + stub_bits.insert(i); + + // Continue if no stub bits found + if (stub_bits.size() == 0) + continue; + + // Report stub bits and/or stub wires, don't report single bits if called + // with report_bits set to false + if (GetSize(stub_bits) == GetSize(sig)) + { + log(" Found stub wire: %s\n", RTLIL::id2cstr(wire->name)); + } + else + { + if (!report_bits) + continue; + + log(" Found wire with stub bits: %s [", RTLIL::id2cstr(wire->name)); + for (int bit : stub_bits) + log("%s%d", bit == *stub_bits.begin() ? "" : ", ", bit); + log("]\n"); + } + + // We have outputted a line, increment summary counter + line_count++; + } + + // Report summary + if (report_bits) + log(" Found %d stub wires or wires with stub bits.\n", line_count); + else + log(" Found %d stub wires.\n", line_count); +} + +// Each pass contains a singleton object that is derived from Pass +struct StubnetsPass : public Pass +{ + StubnetsPass() : Pass("stubnets") {} + + void execute(std::vector args, RTLIL::Design *design) override + { + // Variables to mirror information from passed options + bool report_bits = false; + + log_header(design, "Executing STUBNETS pass (find stub nets).\n"); + + // Parse options + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + std::string arg = args[argidx]; + + if (arg == "-report_bits") + { + report_bits = true; + continue; + } + break; + } + + // Handle extra options (e.g., selection) + extra_args(args, argidx, design); + + // Call find_stub_nets() for each module that is either + // selected as a whole or contains selected objects + for (auto &it : design->modules_) + if (design->selected_module(it.first)) + find_stub_nets(design, it.second, report_bits); + } +} StubnetsPass; + +PRIVATE_NAMESPACE_END diff --git a/run.sh b/run.sh new file mode 100755 index 0000000..ce5be4a --- /dev/null +++ b/run.sh @@ -0,0 +1,276 @@ +#!/bin/bash + +FILE="" +FILE_BASENAME="" +MODULE="" +LIBERTY_FILE="nem_basic_yosys.lib" +visualize=0 + +# Function to display the menu and get user input +show_menu() { + + + # Define color codes + GREEN='\033[0;32m' + YELLOW='\033[1;33m' + CYAN='\033[0;36m' + RESET='\033[0m' + + echo "--------------------------------------------------------------" + echo -e "${CYAN}Current file: $FILE with module: $MODULE${RESET}" + echo -e "${YELLOW}Please select your options (you can choose multiple options):${RESET}" + echo + echo -e "${GREEN}1)${RESET} Synthesize NEM mapped replicate of Verilog implementation" + echo -e "${GREEN}2)${RESET} Print initial design" + echo -e "${GREEN}3)${RESET} Print out NEM optimized design" + echo -e "${GREEN}4)${RESET} Perform SAT comparison" + echo -e "${GREEN}5)${RESET} Export FSM as KISS2 format" + echo -e "${GREEN}6)${RESET} Start shell with modules" + echo -e "${GREEN}7)${RESET} Switch from normal 3T gate library to new 4T" + echo -e "${GREEN}8)${RESET} Run test" + echo -e "${GREEN}9)${RESET} Select a new Verilog file" + echo -e "${GREEN}0)${RESET} Exit the program" + echo "--------------------------------------------------------------" +} + +# Request the file to process +request_data(){ + echo "-:- Enter the file to map to NEM" + read -e -p "What is the file name?: " FILE + read -p "What is the name of the top module? (press ENTER for the same as the file name): " MODULE + + if [ ! -f "$FILE" ]; then + echo "File not found" + request_data + fi + + FILE_BASENAME=$(basename "$FILE" | cut -d. -f1) + #echo $FILE_BASENAME + + if [ -z "$MODULE" ]; then + #echo "setting name equal to that of the file" + MODULE=$FILE_BASENAME + fi +} + +#run a yosys file specified to the function +run_yosys_file() { + local yosys_file="$1" + local depth="$2" + local additional_yosys_args="$3" + + # Start with basic sed commands + sed_command=$(sed -e "s|{{FILE}}|$FILE|g" \ + -e "s|{{FILE_BASENAME}}|$FILE_BASENAME|g" \ + -e "s|{{MODULE}}|$MODULE|g" \ + -e "s|{{LIBERTY_FILE}}|$LIBERTY_FILE|g" \ + -e "s|{{LIBERTY_USED}}|$( [[ $LIBERTY_FILE == *extended* ]] && echo '4T' || echo '3T' )|g"\ + "./yosys/${yosys_file}.ys") + + # Apply additional sed expressions based on DEPTH value + if [[ $depth -eq 0 ]]; then + sed_command=$(echo "$sed_command" | sed -e "/#IF {{DEPTH}}==0/d" \ + -e "/#ELSE/,/#END/d") + elif [[ $depth -eq 1 ]]; then + sed_command=$(echo "$sed_command" | sed -e "/#IF {{DEPTH}}==0/,/#ELSE/d" \ + -e "/#END/d") + fi + + # Write the result to a temp file and run yosys + echo "$sed_command" > "./temp/${yosys_file}_temp.ys" + yosys $additional_yosys_args "./temp/${yosys_file}_temp.ys" +} + +#Switch between 3T and 4T pass through gates +switch_liberty() { + if [ "$LIBERTY_FILE" == "nem_basic_yosys.lib" ]; then + LIBERTY_FILE="nem_basic_yosys_extended.lib" + echo "Now using extended (4T devices) libary" + elif [ "$LIBERTY_FILE" == "nem_basic_yosys_extended.lib" ]; then + LIBERTY_FILE="nem_basic_yosys.lib" + echo "Now using normal libary" + else + echo "Unknown LIBERTY_FILE value: $LIBERTY_FILE" + fi +} + + +#START ACTUAL EXECUTION + +#Check if in menu mode or in CLI mode +if [ -z "$1" ]; then + # in menu mode + request_data +else + + #in cli mode. Filter through all the parameters + while getopts ":d:f:m:v:x:" opt; do + case $opt in + d) # -d option for directory + file_directory="$OPTARG" + ;; + f) # -f option for file + FILE="$OPTARG" + ;; + m) # -m option for module (requires -f to be set) + MODULE="$OPTARG" + ;; + v) # -v visualize before and after synthesis + echo "found visualize" + visualize=1 + ;; + x) # -x switch to extended nem liberty file + echo "switching to 4T libert file" + switch_liberty + ;; + \?) # Invalid option + echo "Invalid option: -$OPTARG" >&2 + usage + ;; + :) # Missing argument for an option + echo "Option -$OPTARG requires an argument." >&2 + usage + ;; + esac + done + + #running synthesis on al lthe files in the directory + if [ -n "$file_directory" ]; then + if [ -d "$file_directory" ]; then + echo "Directory exists: $file_directory" + + for file in "$file_directory"/*.v; do + # Check if it's a regular file + if [ -f "$file" ]; then + # Use grep to find the line that starts with 'module' and extract the module name + module_name=$(grep -m 1 -oP '^module\s+\K\w+' "$file") + + # If the module name is found, print the file path and the module name + if [ -n "$module_name" ]; then + echo "File: $file" + echo "Module: $module_name" + echo + + FILE=$file + FILE_BASENAME=$(basename "$FILE" | cut -d. -f1) + MODULE=$module_name + + #synthesise the file + run_yosys_file "synth_nem" 0 + else + echo "No module found in file: $file" + echo + fi + fi + done + + #done with synthesis + exit 0 + + else + echo "Directory does not exist: $file_directory" + exit 1 + fi + fi + + #running synthesis on the file requested + if [ -n "$FILE" ]; then + if [ -n "$MODULE" ]; then + if [ -f "$FILE" ]; then + echo "File exists: $file" + echo "Module: $module" + FILE_BASENAME=$(basename "$FILE" | cut -d. -f1) + run_yosys_file "synth_nem" 0 + if [ "$visualize" -eq 1 ]; then + run_yosys_file "visual" 0 + run_yosys_file "visual" 1 + else + echo "no visualize set" + fi + exit 0 + else + echo "File does not exist: $file" + exit 1 + fi + else + echo "Missing module (-m) for the file (-f)." + usage + fi + fi + +fi + + +# Loop to allow multiple selections +while true; do + show_menu + read -p "Enter your choices (e.g., 1 2 3, or 0 to finish): " -a choices + + for choice in "${choices[@]}"; do + case $choice in + 1) + echo "performing synthesis" + run_yosys_file "synth_nem" 0 + ;; + 2) + echo "Plotting the initial design with $FILE and $MODULE" + run_yosys_file "visual" 0 + ;; + 3) + echo "Plotting the NEM design with $FILE and $MODULE" + run_yosys_file "visual" 1 + ;; + 4) + echo "Performing SAT test on $FILE and $MODULE" + run_yosys_file "sat_test" 0 + ;; + 5) + echo "Exporting FSM overview of the design" + make clean #to make sure no previous .kiss2 file remains + run_yosys_file "fsm_export" 0 + + if [ -f "./temp/${FILE_BASENAME}.kiss2" ]; then + # If the file exists, run the python script and xdot + python3 ./yosys/kiss2dot.py ./temp/${FILE_BASENAME}.kiss2 > ./temp/${FILE_BASENAME}.dot + xdot ./temp/${FILE_BASENAME}.dot + else + # If the file doesn't exist, print a message + echo "Could not detect an FSM in ${MODULE}" + fi + ;; + 6) + echo "Plotting the initial design with $FILE and $MODULE" + make clean #Clean directories + run_yosys_file "synth_nem" 0 + make all #build plugins + ls ./plugins/*.so + run_yosys_file "start_shell" 0 "$(for so_file in ./plugins/*.so; do echo -m "$so_file"; done)" #create a list of all plugins to load + ;; + 7) + echo "Switching libary" + switch_liberty + ;; + 8) + echo "running sequence of test commands" + run_yosys_file "synth_nem" 0 + run_yosys_file "visual" 1 + switch_liberty + run_yosys_file "synth_nem" 0 + run_yosys_file "visual" 1 + ;; + 9) + echo "requesting new module" + request_data + ;; + 0) + echo "exiting" + break 2 + ;; + *) + echo "Invalid choice. Please select a number between 1 and 6." + ;; + esac + done + + echo +done diff --git a/sources/alu.v b/sources/alu.v new file mode 100644 index 0000000..60447bc --- /dev/null +++ b/sources/alu.v @@ -0,0 +1,51 @@ +module alu ( + input clk, + input rst, + input [31:0] a, + input [31:0] b, + input [2:0] opcode, // 000: add, 001: sub, 010: and, 011: or, 100: xor + output reg [31:0] result +); + + reg [31:0] stage1_a, stage1_b; + reg [2:0] stage1_opcode; + reg [31:0] stage2_result; + + // Stage 1: Register Inputs + always @(posedge clk) begin + if (rst) begin + stage1_a <= 0; + stage1_b <= 0; + stage1_opcode <= 0; + end else begin + stage1_a <= a; + stage1_b <= b; + stage1_opcode <= opcode; + end + end + + // Stage 2: ALU Operations + always @(posedge clk) begin + if (rst) begin + stage2_result <= 0; + end else begin + case (stage1_opcode) + 3'b000: stage2_result <= stage1_a + stage1_b; // Add + 3'b001: stage2_result <= stage1_a - stage1_b; // Subtract + //3'b010: stage2_result <= stage1_a & stage1_b; // AND + //3'b011: stage2_result <= stage1_a | stage1_b; // OR + //3'b100: stage2_result <= stage1_a ^ stage1_b; // XOR + default: stage2_result <= 0; + endcase + end + end + + // Stage 3: Output + always @(posedge clk) begin + if (rst) begin + result <= 0; + end else begin + result <= stage2_result; + end + end +endmodule diff --git a/sources/counter-tb.v b/sources/counter-tb.v new file mode 100644 index 0000000..9c6ec01 --- /dev/null +++ b/sources/counter-tb.v @@ -0,0 +1,46 @@ +`timescale 10ns/1ns + +module tb_counter; + + initial begin + $display("Testing counter"); + $dumpfile("counter_tb.vcd"); + $dumpvars(0, tb_counter); + end + + // Inputs + reg clk = 0; + reg rst = 0; + reg mode = 0; + + // Outputs + wire signed [9:0] cnt; + + // Instantiating unit under test (UUT) + counter uut ( + .clk(clk), + .rst(rst), + .mode(mode), + .cnt(cnt) + ); + + // Generating clock + always #5 clk = !clk; + + // Testing the design + initial begin + + // Resetting the design + #5 rst = 1; + #10 rst = 0; + #17 mode = !mode; + #22 mode = !mode; + #12 mode = !mode; + #100 mode = !mode; + + $finish; + end + + initial $monitor("At time %t, value = %h (%0d)", $time, cnt, cnt); + +endmodule diff --git a/sources/counter.v b/sources/counter.v new file mode 100755 index 0000000..646c3c7 --- /dev/null +++ b/sources/counter.v @@ -0,0 +1,109 @@ +module counter ( clk, rst, mode, cnt); + + input wire clk; + input wire rst; + input wire mode; + output reg signed[10-1:0] cnt; + + reg signed[10-1:0] add_val; + + always @* + begin + add_val = 10'sd0; + if (mode) begin + if (cnt!=10'sd14) begin + if (cnt <=10'sd218) begin + add_val <= 10'sd5; + end + end else if (cnt <= 10'sd213 ) begin + add_val <= 10'sd10; + end + end else begin + if (cnt!=10'sd28) begin + if (cnt>=-10'sd233) begin + add_val<=-10'sd9; + end + end else if (cnt >= -10'sd224) begin + add_val <= -10'sd18; + end + + end + end + + always @(posedge clk) begin + if (rst) + cnt <= -10'sd62; + else begin + cnt<= cnt + add_val; + end + end + + `ifdef FORMAL + reg init = 1; + always @(posedge clk) begin + if (init) assume(rst); + else assume(!rst); + init <= 0; + end + + always @(posedge clk) begin + + if (rst) begin + assert (cnt == -10'sd62); + end + + if (!rst) begin + + assert (cnt <= 10'sd223); + assert (cnt >= -10'sd242); + assert (cnt != 10'sd19); + + + + if ($past(mode)) begin + if (!$past(rst)) begin + if ($past(cnt) == (10'sd19-10'sd5)) begin + assert ((cnt - $past(cnt)) == (10'sd10)); + end else if ($past(cnt) <= 10'sd223 && $past(cnt) > (10'sd223-10'sd5)) begin + assert ((cnt - $past(cnt)) == 0); + end else begin + assert ((cnt - $past(cnt)) == 10'sd5); + end + end + end + + // Counting down + if (!$past(mode)) begin + if (!$past(rst)) begin + if ($past(cnt) == (10'sd19+10'sd9)) begin + assert (($past(cnt) - cnt) == (10'sd18)); + end else if ($past(cnt) >= -10'sd242 && $past(cnt) < (-10'sd242+10'sd9)) begin + assert (($past(cnt) - cnt) == 0); + end else begin + assert (($past(cnt) - cnt) == 10'sd9); + end + end + end + + end + end + + `endif +endmodule + +/* Number of wires: 14 + Number of wire bits: 59 + Number of public wires: 5 + Number of public wire bits: 23 + Number of ports: 4 + Number of port bits: 13 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 11 + $add 1 + $adff 1 + $ge 2 + $le 2 + $mux 3 + $ne 2*/ \ No newline at end of file diff --git a/sources/counter_simple.v b/sources/counter_simple.v new file mode 100644 index 0000000..19d2ab7 --- /dev/null +++ b/sources/counter_simple.v @@ -0,0 +1,14 @@ +module counter ( clk, rst, cnt); + + input wire clk; + input wire rst; + output reg signed[1:0] cnt; + + always @(posedge clk) begin + if (rst) + cnt <= 2'sd0; + else begin + cnt <= cnt + 2'sd1; + end + end +endmodule \ No newline at end of file diff --git a/sources/fsm.v b/sources/fsm.v new file mode 100644 index 0000000..7919b00 --- /dev/null +++ b/sources/fsm.v @@ -0,0 +1,32 @@ +module fsm(input clk, rst, ctrl, output [3:0] O); + reg [1:0] state; + always @(posedge clk) begin + O <= 0; + if (rst) begin + state <= 0; + end else case (state) + 0: begin + state <= ctrl ? 1 : 2; + O <= 1; + end + 1: begin + O <= 2; + if (ctrl) begin + state <= 2; + O <= 3; + end + end + 2: begin + O <= 4; + if (ctrl) begin + state <= 3; + O <= 5; + end + end + 3: begin + if (!ctrl) + state <= 2'b00; + end + endcase + end +endmodule \ No newline at end of file diff --git a/sources/fsm_dataset/asycnreset_Binary_6.v b/sources/fsm_dataset/asycnreset_Binary_6.v new file mode 100644 index 0000000..e8059c0 --- /dev/null +++ b/sources/fsm_dataset/asycnreset_Binary_6.v @@ -0,0 +1,41 @@ +module fsm ( + input wire clk, + input wire reset, + input wire in, + output wire out +); + + // Define state encoding using parameters + parameter S0 = 3'b000, + S1 = 3'b001, + S2 = 3'b010, + S3 = 3'b011, + S4 = 3'b100, + S5 = 3'b101; + + reg [2:0] state, next_state; // 3-bit state register + + // Sequential block: state transitions on clock or reset + always @(posedge clk or posedge reset) begin + if (reset) + state <= S0; // Reset to S0 + else + state <= next_state; + end + + // Combinational block: next state logic + always @(*) begin + case (state) + S0: next_state = in ? S1 : S0; + S1: next_state = in ? S2 : S1; + S2: next_state = in ? S3 : S2; + S3: next_state = in ? S4 : S3; + S4: next_state = in ? S5 : S4; + S5: next_state = S0; // Cycle back to S0 after S5 + default: next_state = S0; // Safe default in case of illegal state + endcase + end + + // Combinational block: output logic + assign out = (next_state == S5); +endmodule diff --git a/sources/fsm_dataset/branchingmux_binary_7.v b/sources/fsm_dataset/branchingmux_binary_7.v new file mode 100644 index 0000000..b5ad9d6 --- /dev/null +++ b/sources/fsm_dataset/branchingmux_binary_7.v @@ -0,0 +1,33 @@ +module fsm ( + input wire clk, + input wire reset, + input wire in1, in2, + output wire out +); + reg [2:0] state, next_state; + + // Sequential block: state transitions on clock or reset + always @(posedge clk or posedge reset) begin + if (reset) + state <= 3'b000; // Reset state + else + state <= next_state; + end + + // Combinational block: next state logic + always @(*) begin + case (state) + 3'b000: next_state = in1 ? 3'b001 : 3'b010; + 3'b001: next_state = in2 ? 3'b011 : 3'b100; + 3'b010: next_state = 3'b101; + 3'b011: next_state = 3'b000; // Loop back to initial state + 3'b100: next_state = 3'b000; // Another loop to initial state + 3'b101: next_state = 3'b000; // Terminal state back to initial + default: next_state = 3'b000; // Safe default for illegal states + endcase + end + + // Combinational block: output logic + + assign out = (state == 3'b101); // Output '1' only in state 101 +endmodule diff --git a/sources/fsm_dataset/hiearachical_binary_o8_i5.v b/sources/fsm_dataset/hiearachical_binary_o8_i5.v new file mode 100644 index 0000000..5df3533 --- /dev/null +++ b/sources/fsm_dataset/hiearachical_binary_o8_i5.v @@ -0,0 +1,48 @@ +module fsm ( + input wire clk, + input wire reset, + input wire [1:0] in, + output wire out +); + reg [2:0] main_state; // 3 bits for 8 states + reg [2:0] sub_state; // 3 bits for 5 states (2 bits will suffice for 4 states, but using 3 for simplicity) + + // Main FSM controlling a sub FSM + always @(posedge clk or posedge reset) begin + if (reset) begin + main_state <= 3'b000; // Reset to state 0 + end else begin + case (main_state) + 3'b000: main_state <= in[0] ? 3'b001 : 3'b000; + 3'b001: main_state <= in[0] ? 3'b010 : 3'b001; + 3'b010: main_state <= in[0] ? 3'b011 : 3'b010; + 3'b011: main_state <= in[0] ? 3'b100 : 3'b011; + 3'b100: main_state <= in[0] ? 3'b101 : 3'b100; + 3'b101: main_state <= in[0] ? 3'b110 : 3'b101; + 3'b110: main_state <= in[0] ? 3'b111 : 3'b110; + 3'b111: main_state <= 3'b000; // Cycle back to 0 + default: main_state <= 3'b000; // Safe default + endcase + end + end + + // Sub FSM definition + always @(posedge clk or posedge reset) begin + if (reset) begin + sub_state <= 3'b000; // Reset sub state + end else begin + case (sub_state) + 3'b000: sub_state <= in[1] ? 3'b001 : 3'b000; + 3'b001: sub_state <= in[1] ? 3'b010 : 3'b001; + 3'b010: sub_state <= in[1] ? 3'b011 : 3'b010; + 3'b011: sub_state <= in[1] ? 3'b100 : 3'b011; + 3'b100: sub_state <= 3'b000; // Cycle back to 0 after reaching state 4 + default: sub_state <= 3'b000; // Safe default + endcase + end + end + + // Output logic based on main and sub states + assign out = (main_state == 3'b111 && sub_state == 3'b100); // Example condition for output + +endmodule diff --git a/sources/fsm_dataset/mealy_onehot_5.v b/sources/fsm_dataset/mealy_onehot_5.v new file mode 100644 index 0000000..50c3a18 --- /dev/null +++ b/sources/fsm_dataset/mealy_onehot_5.v @@ -0,0 +1,41 @@ +module fsm ( + input wire clk, + input wire reset, + input wire in1, + input wire in2, + output reg out +); + // Define state encoding using parameters + parameter S0 = 3'b000, + S1 = 3'b001, + S2 = 3'b010, + S3 = 3'b011, + S4 = 3'b100; + + reg [2:0] state, next_state; + + // Sequential block: state transitions on clock or reset + always @(posedge clk or posedge reset) begin + if (reset) + state <= S0; // Reset to S0 + else + state <= next_state; // Move to next state + end + + // Combinational block: next state logic + always @(*) begin + case (state) + S0: next_state = in1 ? S1 : S0; + S1: next_state = in2 ? S2 : S1; + S2: next_state = in1 ? S3 : S2; + S3: next_state = in2 ? S4 : S3; + S4: next_state = S0; // Cycle back to S0 + default: next_state = S0; // Safe default + endcase + end + + // Mealy output logic depends on state and input + always @(*) begin + out = (state == S2 && in1) || (state == S4 && in2); + end +endmodule diff --git a/sources/fsm_dataset/moore_binary_3.v b/sources/fsm_dataset/moore_binary_3.v new file mode 100644 index 0000000..80605ed --- /dev/null +++ b/sources/fsm_dataset/moore_binary_3.v @@ -0,0 +1,45 @@ +module fsm ( + input wire clk, + input wire reset, + input wire in, + output reg out +); + // Define state encoding using parameters + parameter S0 = 2'b00, + S1 = 2'b01, + S2 = 2'b10; + + reg [1:0] state, next_state; + + // State transition logic + always @(posedge clk or posedge reset) begin + if (reset) + state <= S0; // Reset to S0 + else + state <= next_state; // Move to next state + end + + // Next state logic + always @(*) begin + case (state) + S0: next_state = in ? S1 : S0; + S1: next_state = in ? S2 : S1; + S2: next_state = in ? S0 : S2; + default: next_state = S0; // Safe default + endcase + end + + // Output logic (Moore: depends only on the state) + always @(posedge clk or posedge reset) begin + if (reset) + out <= 0; // Reset output + else begin + case (state) + S0: out <= 1; + S1: out <= 0; + S2: out <= 1; + default: out <= 0; // Safe default + endcase + end + end +endmodule diff --git a/sources/fsm_dataset/moore_graycode_12.v b/sources/fsm_dataset/moore_graycode_12.v new file mode 100644 index 0000000..74e31d4 --- /dev/null +++ b/sources/fsm_dataset/moore_graycode_12.v @@ -0,0 +1,53 @@ +module fsm ( + input wire clk, + input wire reset, + input wire [3:0] in, + output reg [1:0] out +); + // Define state encoding using parameters + parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0011, S3 = 4'b0010, + S4 = 4'b0110, S5 = 4'b0111, S6 = 4'b0101, S7 = 4'b0100, + S8 = 4'b1100, S9 = 4'b1101, S10 = 4'b1111, S11 = 4'b1110; + + reg [3:0] state, next_state; + + // State transition logic (sequential) + always @(posedge clk or posedge reset) begin + if (reset) + state <= S0; // Reset to initial state S0 + else + state <= next_state; // Transition to the next state + end + + // Next state logic (combinational) + always @(*) begin + case (state) + S0: next_state = in[0] ? S1 : S0; + S1: next_state = in[1] ? S2 : S1; + S2: next_state = in[2] ? S3 : S2; + S3: next_state = in[3] ? S4 : S3; + S4: next_state = in[0] ? S5 : S4; + S5: next_state = in[1] ? S6 : S5; + S6: next_state = in[2] ? S7 : S6; + S7: next_state = in[3] ? S8 : S7; + S8: next_state = in[0] ? S9 : S8; + S9: next_state = in[1] ? S10 : S9; + S10: next_state = in[2] ? S11 : S10; + S11: next_state = S0; // Loop back to S0 after S11 + default: next_state = S0; // Default case + endcase + end + + // Output logic (Moore-type, depends only on the state) + always @(*) begin + case (state) + S0, S1: out = 2'b00; + S2, S3: out = 2'b01; + S4, S5: out = 2'b10; + S6, S7: out = 2'b11; + S8, S9: out = 2'b01; + S10, S11: out = 2'b10; + default: out = 2'b00; // Safe default + endcase + end +endmodule diff --git a/sources/sum.v b/sources/sum.v new file mode 100644 index 0000000..b828d97 --- /dev/null +++ b/sources/sum.v @@ -0,0 +1,16 @@ +module sum ( clk, A, B, sel, out); + + input wire clk; + input wire A; + input wire B; + input wire sel; + output reg signed out; + + always @(posedge clk) begin + if (sel) + out <= A; + else begin + out <= B; + end + end +endmodule \ No newline at end of file diff --git a/sources/test_set/adder2.v b/sources/test_set/adder2.v new file mode 100644 index 0000000..6054406 --- /dev/null +++ b/sources/test_set/adder2.v @@ -0,0 +1,12 @@ +module adder2 (A, B, Ci, S, Co); + +input[1:0] A; +input[1:0] B; +input Ci; +output[1:0] S; +output Co; +wire[2:0] Sum3; +assign Sum3 = A + B + Ci ; +assign S = Sum3[1:0] ; +assign Co = Sum3[2] ; +endmodule diff --git a/sources/test_set/adder32.v b/sources/test_set/adder32.v new file mode 100644 index 0000000..9fd5d3a --- /dev/null +++ b/sources/test_set/adder32.v @@ -0,0 +1,12 @@ +module adder32 (A, B, Ci, S, Co); + +input[31:0] A; +input[31:0] B; +input Ci; +output[31:0] S; +output Co; +wire[32:0] Sum33; +assign Sum33 = A + B + Ci ; +assign S = Sum33[31:0] ; +assign Co = Sum33[32] ; +endmodule diff --git a/sources/test_set/adder4.v b/sources/test_set/adder4.v new file mode 100644 index 0000000..7240e4b --- /dev/null +++ b/sources/test_set/adder4.v @@ -0,0 +1,12 @@ +module adder4 (A, B, Ci, S, Co); + +input[3:0] A; +input[3:0] B; +input Ci; +output[3:0] S; +output Co; +wire[4:0] Sum5; +assign Sum5 = A + B + Ci ; +assign S = Sum5[3:0] ; +assign Co = Sum5[4] ; +endmodule diff --git a/sources/test_set/adder8.v b/sources/test_set/adder8.v new file mode 100644 index 0000000..91bcdc9 --- /dev/null +++ b/sources/test_set/adder8.v @@ -0,0 +1,12 @@ +module adder8 (A, B, Ci, S, Co); + +input[7:0] A; +input[7:0] B; +input Ci; +output[7:0] S; +output Co; +wire[8:0] Sum9; +assign Sum9 = A + B + Ci ; +assign S = Sum9[7:0] ; +assign Co = Sum9[8] ; +endmodule diff --git a/sources/test_set/alu.v b/sources/test_set/alu.v new file mode 100644 index 0000000..b251268 --- /dev/null +++ b/sources/test_set/alu.v @@ -0,0 +1,51 @@ +module alu ( + input clk, + input rst, + input [31:0] a, + input [31:0] b, + input [2:0] opcode, // 000: add, 001: sub, 010: and, 011: or, 100: xor + output reg [31:0] result +); + + reg [31:0] stage1_a, stage1_b; + reg [2:0] stage1_opcode; + reg [31:0] stage2_result; + + // Stage 1: Register Inputs + always @(posedge clk) begin + if (rst) begin + stage1_a <= 0; + stage1_b <= 0; + stage1_opcode <= 0; + end else begin + stage1_a <= a; + stage1_b <= b; + stage1_opcode <= opcode; + end + end + + // Stage 2: ALU Operations + always @(posedge clk) begin + if (rst) begin + stage2_result <= 0; + end else begin + case (stage1_opcode) + 3'b000: stage2_result <= stage1_a + stage1_b; // Add + 3'b001: stage2_result <= stage1_a - stage1_b; // Subtract + 3'b010: stage2_result <= stage1_a & stage1_b; // AND + 3'b011: stage2_result <= stage1_a | stage1_b; // OR + 3'b100: stage2_result <= stage1_a ^ stage1_b; // XOR + default: stage2_result <= 0; + endcase + end + end + + // Stage 3: Output + always @(posedge clk) begin + if (rst) begin + result <= 0; + end else begin + result <= stage2_result; + end + end +endmodule diff --git a/sources/test_set/asycnreset_Binary_6.v b/sources/test_set/asycnreset_Binary_6.v new file mode 100644 index 0000000..e8059c0 --- /dev/null +++ b/sources/test_set/asycnreset_Binary_6.v @@ -0,0 +1,41 @@ +module fsm ( + input wire clk, + input wire reset, + input wire in, + output wire out +); + + // Define state encoding using parameters + parameter S0 = 3'b000, + S1 = 3'b001, + S2 = 3'b010, + S3 = 3'b011, + S4 = 3'b100, + S5 = 3'b101; + + reg [2:0] state, next_state; // 3-bit state register + + // Sequential block: state transitions on clock or reset + always @(posedge clk or posedge reset) begin + if (reset) + state <= S0; // Reset to S0 + else + state <= next_state; + end + + // Combinational block: next state logic + always @(*) begin + case (state) + S0: next_state = in ? S1 : S0; + S1: next_state = in ? S2 : S1; + S2: next_state = in ? S3 : S2; + S3: next_state = in ? S4 : S3; + S4: next_state = in ? S5 : S4; + S5: next_state = S0; // Cycle back to S0 after S5 + default: next_state = S0; // Safe default in case of illegal state + endcase + end + + // Combinational block: output logic + assign out = (next_state == S5); +endmodule diff --git a/sources/test_set/counter10.v b/sources/test_set/counter10.v new file mode 100644 index 0000000..aeb509c --- /dev/null +++ b/sources/test_set/counter10.v @@ -0,0 +1,14 @@ +module counter ( clk, rst, cnt); + + input wire clk; + input wire rst; + output reg signed[9:0] cnt; + + always @(posedge clk) begin + if (rst) + cnt <= 10'sd0; + else begin + cnt <= cnt + 10'sd1; + end + end +endmodule \ No newline at end of file diff --git a/sources/test_set/counter2.v b/sources/test_set/counter2.v new file mode 100644 index 0000000..19d2ab7 --- /dev/null +++ b/sources/test_set/counter2.v @@ -0,0 +1,14 @@ +module counter ( clk, rst, cnt); + + input wire clk; + input wire rst; + output reg signed[1:0] cnt; + + always @(posedge clk) begin + if (rst) + cnt <= 2'sd0; + else begin + cnt <= cnt + 2'sd1; + end + end +endmodule \ No newline at end of file diff --git a/sources/test_set/mealy_onehot_5.v b/sources/test_set/mealy_onehot_5.v new file mode 100644 index 0000000..365330b --- /dev/null +++ b/sources/test_set/mealy_onehot_5.v @@ -0,0 +1,41 @@ +module fsm ( + input wire clk, + input wire reset, + input wire in1, + input wire in2, + output reg out +); + // Define state encoding using parameters + parameter S0 = 5'b00000, + S1 = 5'b00010, + S2 = 5'b00100, + S3 = 5'b01000, + S4 = 5'b10000; + + reg [2:0] state, next_state; + + // Sequential block: state transitions on clock or reset + always @(posedge clk or posedge reset) begin + if (reset) + state <= S0; // Reset to S0 + else + state <= next_state; // Move to next state + end + + // Combinational block: next state logic + always @(*) begin + case (state) + S0: next_state = in1 ? S1 : S0; + S1: next_state = in2 ? S2 : S1; + S2: next_state = in1 ? S3 : S2; + S3: next_state = in2 ? S4 : S3; + S4: next_state = S0; // Cycle back to S0 + default: next_state = S0; // Safe default + endcase + end + + // Mealy output logic depends on state and input + always @(*) begin + out = (state == S2 && in1) || (state == S4 && in2); + end +endmodule diff --git a/sources/test_set/moore_binary_3.v b/sources/test_set/moore_binary_3.v new file mode 100644 index 0000000..80605ed --- /dev/null +++ b/sources/test_set/moore_binary_3.v @@ -0,0 +1,45 @@ +module fsm ( + input wire clk, + input wire reset, + input wire in, + output reg out +); + // Define state encoding using parameters + parameter S0 = 2'b00, + S1 = 2'b01, + S2 = 2'b10; + + reg [1:0] state, next_state; + + // State transition logic + always @(posedge clk or posedge reset) begin + if (reset) + state <= S0; // Reset to S0 + else + state <= next_state; // Move to next state + end + + // Next state logic + always @(*) begin + case (state) + S0: next_state = in ? S1 : S0; + S1: next_state = in ? S2 : S1; + S2: next_state = in ? S0 : S2; + default: next_state = S0; // Safe default + endcase + end + + // Output logic (Moore: depends only on the state) + always @(posedge clk or posedge reset) begin + if (reset) + out <= 0; // Reset output + else begin + case (state) + S0: out <= 1; + S1: out <= 0; + S2: out <= 1; + default: out <= 0; // Safe default + endcase + end + end +endmodule diff --git a/sources/test_set/moore_graycode_12.v b/sources/test_set/moore_graycode_12.v new file mode 100644 index 0000000..74e31d4 --- /dev/null +++ b/sources/test_set/moore_graycode_12.v @@ -0,0 +1,53 @@ +module fsm ( + input wire clk, + input wire reset, + input wire [3:0] in, + output reg [1:0] out +); + // Define state encoding using parameters + parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0011, S3 = 4'b0010, + S4 = 4'b0110, S5 = 4'b0111, S6 = 4'b0101, S7 = 4'b0100, + S8 = 4'b1100, S9 = 4'b1101, S10 = 4'b1111, S11 = 4'b1110; + + reg [3:0] state, next_state; + + // State transition logic (sequential) + always @(posedge clk or posedge reset) begin + if (reset) + state <= S0; // Reset to initial state S0 + else + state <= next_state; // Transition to the next state + end + + // Next state logic (combinational) + always @(*) begin + case (state) + S0: next_state = in[0] ? S1 : S0; + S1: next_state = in[1] ? S2 : S1; + S2: next_state = in[2] ? S3 : S2; + S3: next_state = in[3] ? S4 : S3; + S4: next_state = in[0] ? S5 : S4; + S5: next_state = in[1] ? S6 : S5; + S6: next_state = in[2] ? S7 : S6; + S7: next_state = in[3] ? S8 : S7; + S8: next_state = in[0] ? S9 : S8; + S9: next_state = in[1] ? S10 : S9; + S10: next_state = in[2] ? S11 : S10; + S11: next_state = S0; // Loop back to S0 after S11 + default: next_state = S0; // Default case + endcase + end + + // Output logic (Moore-type, depends only on the state) + always @(*) begin + case (state) + S0, S1: out = 2'b00; + S2, S3: out = 2'b01; + S4, S5: out = 2'b10; + S6, S7: out = 2'b11; + S8, S9: out = 2'b01; + S10, S11: out = 2'b10; + default: out = 2'b00; // Safe default + endcase + end +endmodule diff --git a/stats b/stats new file mode 100644 index 0000000..fb79460 --- /dev/null +++ b/stats @@ -0,0 +1,82 @@ +=== alu_nem === + + Number of wires: 979 + Number of wire bits: 1200 + Number of public wires: 10 + Number of public wire bits: 200 + Number of ports: 6 + Number of port bits: 101 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1000 + D_FF 131 + and_3T 81 + inv_3T 132 + mux_4T 32 + nand_3T 134 + nor_3T 440 + or_3T 15 + xnor_3T 34 + xor_3T 1 + + Chip area for module '\alu_nem': 5167120.000000 + of which used for sequential elements: 2627336.000000 (50.85%) + +=== alu_nem === With 4T mux and & or & xor + + Number of wires: 850 + Number of wire bits: 1071 + Number of public wires: 10 + Number of public wire bits: 200 + Number of ports: 6 + Number of port bits: 101 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 871 + D_FF 131 + and_4T 180 + inv_3T 57 + mux_4T 32 + nand_3T 243 + nor_3T 122 + or_4T 21 + xor_4T 85 + + Chip area for module '\alu_nem': 4929832.000000 + of which used for sequential elements: 2627336.000000 (53.29%) + +=== alu_nem === With 4T mux and & or & xor but also the or_inv and and_inv + + Number of wires: 842 + Number of wire bits: 1063 + Number of public wires: 10 + Number of public wire bits: 200 + Number of ports: 6 + Number of port bits: 101 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 863 + D_FF 131 + and_4T 29 + and_4T_inv 111 + inv_3T 45 + mux_4T 32 + nand_3T 232 + nor_3T 166 + or_4T 14 + or_4T_inv 18 + xor_4T 85 + + Chip area for module '\alu_nem': 4908680.000000 + of which used for sequential elements: 2627336.000000 (53.52%) + +with modified + +With new gates +4929832/5167120 = 0.954 = 95.4% meaning 4.6% decrease in size + +with inverted and & or +4908680/5167120 = 0.949 = 94.9% meaning 5.1% decrease in size \ No newline at end of file diff --git a/synth.tcl b/synth.tcl new file mode 100644 index 0000000..ccf414a --- /dev/null +++ b/synth.tcl @@ -0,0 +1,49 @@ +if {$::env(TECH) == "cmos"} { + #CMOS LIB + #set_db init_lib_search_path /kits/xkit/xi10/diglibs/D_CELLS/v6_0/liberty_CORE1/v6_0_0/PVT_5_00V_225C_range/ + set_db init_lib_search_path $::env(XKIT_DIR)/xi10/diglibs/D_CELLS/v6_0/liberty_CORE1/v6_0_0/PVT_5_00V_225C_range/ + read_libs D_CELLS_CORE1_typ_5_00V_225C.lib +} + +if {$::env(TECH) == "nem"} { + #NEM LIB + set_db init_lib_search_path $::env(NEM_DIR)/models/liberty/basic + read_libs nem_basic.lib +} + +#HDL CODE +set_db init_hdl_search_path ../rtl/ +read_hdl state_id_cnt.v + +#set_db init_hdl_search_path ../../comparator_lt/rtl/ +#read_hdl comparator_lt.v + +set_db init_hdl_search_path ../../half_adder/rtl/ +read_hdl half_adder.v + +set_db init_hdl_search_path ../../incrementer/rtl/ +read_hdl incrementer.v + +elaborate + +#CONSTRAINTS +read_sdc timing.sdc + +#SYNTHESIS +set_db syn_generic_effort medium +set_db syn_map_effort medium +set_db syn_opt_effort medium + +syn_generic +syn_map +syn_opt + +#OUTPUT +report_timing > report/report_timing.rpt +report_power > report/report_power.rpt +report_area > report/report_area.rpt +report_gates > report/report_gates.rpt +report_memory > report/report_memory.rpt + +write_hdl > output/netlist.v +write_sdc > output/sdc.sdc diff --git a/yosys/fsm_export.ys b/yosys/fsm_export.ys new file mode 100644 index 0000000..478d35c --- /dev/null +++ b/yosys/fsm_export.ys @@ -0,0 +1,30 @@ +read_verilog {{FILE}} +proc +opt -nodffe -nosdff + +dump -o ./temp/fsm_pre.dump +fsm_detect -ignore-self-reset + +#Identify and extract FSMs: + +fsm_extract + +# Basic optimizations: +fsm_opt +opt_clean +fsm_opt + +# Expanding to nearby gate-logic (if called with -expand): +fsm_expand +opt_clean +fsm_opt + +# Re-code FSM states (unless called with -norecode): +fsm_recode -encoding binary + +# Print information about FSMs: +fsm_info + +dump -o ./temp/fsm_post.dump + +fsm_export -o ./temp/{{FILE_BASENAME}}.kiss2 diff --git a/yosys/kiss2dot.py b/yosys/kiss2dot.py new file mode 100644 index 0000000..1ebb9ac --- /dev/null +++ b/yosys/kiss2dot.py @@ -0,0 +1,13 @@ +#!/usr/bin/env python3 + +import fileinput + +print("digraph fsm {") + +for line in fileinput.input(): + if not line.startswith("."): + in_bits, from_state, to_state, out_bits = line.split() + print("%s -> %s [label=\"IN=%s,\\nOUT=%s\"];" % (from_state, to_state, + in_bits.replace("-", "?"), out_bits.replace("-", "?"))) + +print("}") \ No newline at end of file diff --git a/yosys/sat_test.ys b/yosys/sat_test.ys new file mode 100644 index 0000000..13f0a19 --- /dev/null +++ b/yosys/sat_test.ys @@ -0,0 +1,30 @@ +# test to check sat comparison. +echo on + +read_liberty -ignore_miss_func ./nem_basic_yosys.lib +design -save lib # save the Liberty library + +read_verilog {{FILE}} +read_verilog ./temp/{{FILE_BASENAME}}_nem.v + +proc +clean + +miter -equiv -make_assert {{MODULE}} {{MODULE}}_nem equal + +#show equal + +flatten equal + +clean + +opt -full;; + +techmap -map %lib + + +#show -pause equal + +stat equal + +sat -prove-asserts -set-init-zero -tempinduct -verify -show-regs -show-inputs -show-outputs -dump_vcd trace.vcd equal diff --git a/yosys/start_shell.ys b/yosys/start_shell.ys new file mode 100644 index 0000000..0a351a9 --- /dev/null +++ b/yosys/start_shell.ys @@ -0,0 +1,12 @@ +echo on +read_verilog ./temp/{{FILE_BASENAME}}_nem.v +hierarchy -top {{MODULE}}_nem +proc +opt +clean +stat + +read_liberty -lib ./nem_basic_yosys.lib +#show +dump -o ./temp/{{FILE_BASENAME}}_nem_dump.v +critical_path \ No newline at end of file diff --git a/yosys/synth_nem.ys b/yosys/synth_nem.ys new file mode 100644 index 0000000..8f96d9d --- /dev/null +++ b/yosys/synth_nem.ys @@ -0,0 +1,52 @@ +echo on + +# read the information +read_verilog {{FILE}} +hierarchy -top {{MODULE}} + +#unroll the information +proc; +opt -full;; + +#flatten the counter to its lower parts +flatten;; + +fsm + +##show -prefix ./temp/{{MODULE}}_post_flatten {{MODULE}} + +#optimize +opt -full;; + +##show -prefix ./temp/{{MODULE}}_post_flatten_opt {{MODULE}} + +#Map to gates using the standard techmap available +techmap + +#opt -full;; + +#mapping memory +dfflibmap -liberty ./{{LIBERTY_FILE}};; + +#optimizing possible memory mapping +opt -full;; + +##show -prefix ./temp/{{MODULE}}_post_techmap {{MODULE}} + +#write_blif ./temp/{{MODULE}}_intermediate.blif + +#Replace basic combinational gates with those in our standard cell library +#abc -liberty ./nem_basic_yosys.lib -script ./abc_script -showtmp +abc -liberty ./{{LIBERTY_FILE}} + +##show -prefix ./temp/{{MODULE}}_post_opt {{MODULE}} + +#Check if we can optimize further +opt -full;; + +#Write to file +rename {{MODULE}} {{MODULE}}_nem +write_verilog ./temp/{{FILE_BASENAME}}_nem.v + +#Output stats +tee -o ./temp/{{FILE_BASENAME}}_{{LIBERTY_USED}}.stat stat -liberty ./{{LIBERTY_FILE}} diff --git a/yosys/visual.ys b/yosys/visual.ys new file mode 100644 index 0000000..13fdfe0 --- /dev/null +++ b/yosys/visual.ys @@ -0,0 +1,23 @@ +echo on + + + +read_liberty ./nem_basic_yosys_extended.lib + +#IF {{DEPTH}}==0 +read_verilog {{FILE}} +hierarchy -top {{MODULE}} +proc +clean + + +show -prefix ./temp/{{MODULE}}_initial -color darkred t:$mux -color green t:$dff -color purple t:$ge -color darkblue t:$ne -color blue t:$le -color maroon t:$add -enum {{MODULE}} +stat +#ELSE + +read_verilog ./temp/{{FILE_BASENAME}}_nem.v +hierarchy -top {{MODULE}}_nem + +show -prefix ./temp/{{MODULE}}_synthesized_{{LIBERTY_USED}} -color orange t:inv_3T -color darkred t:nor_3T -color green t:and_3T -color purple t:or_3T -color darkblue t:nand_3T -color blue t:xnor_3T -color maroon t:D_FF -enum {{MODULE}}_nem +stat +#END